1//! `x86_64`'s Streaming SIMD Extensions 2 (SSE2)
2
3use crate::core_arch::x86::*;
4
5#[cfg(test)]
6use stdarch_test::assert_instr;
7
8#[allow(improper_ctypes)]
9unsafe extern "C" {
10 #[link_name = "llvm.x86.sse2.cvtsd2si64"]
11 unsafefn cvtsd2si64(a: __m128d) -> i64;
12 #[link_name = "llvm.x86.sse2.cvttsd2si64"]
13 unsafefn cvttsd2si64(a: __m128d) -> i64;
14}
15
16/// Converts the lower double-precision (64-bit) floating-point element in a to
17/// a 64-bit integer.
18///
19/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_si64)
20#[inline]
21#[target_feature(enable = "sse2")]
22#[cfg_attr(test, assert_instr(cvtsd2si))]
23#[stable(feature = "simd_x86", since = "1.27.0")]
24pub fn _mm_cvtsd_si64(a: __m128d) -> i64 {
25 unsafe { cvtsd2si64(a) }
26}
27
28/// Alias for `_mm_cvtsd_si64`
29///
30/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_si64x)
31#[inline]
32#[target_feature(enable = "sse2")]
33#[cfg_attr(test, assert_instr(cvtsd2si))]
34#[stable(feature = "simd_x86", since = "1.27.0")]
35pub fn _mm_cvtsd_si64x(a: __m128d) -> i64 {
36 _mm_cvtsd_si64(a)
37}
38
39/// Converts the lower double-precision (64-bit) floating-point element in `a`
40/// to a 64-bit integer with truncation.
41///
42/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_si64)
43#[inline]
44#[target_feature(enable = "sse2")]
45#[cfg_attr(test, assert_instr(cvttsd2si))]
46#[stable(feature = "simd_x86", since = "1.27.0")]
47pub fn _mm_cvttsd_si64(a: __m128d) -> i64 {
48 unsafe { cvttsd2si64(a) }
49}
50
51/// Alias for `_mm_cvttsd_si64`
52///
53/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_si64x)
54#[inline]
55#[target_feature(enable = "sse2")]
56#[cfg_attr(test, assert_instr(cvttsd2si))]
57#[stable(feature = "simd_x86", since = "1.27.0")]
58pub fn _mm_cvttsd_si64x(a: __m128d) -> i64 {
59 _mm_cvttsd_si64(a)
60}
61
62/// Stores a 64-bit integer value in the specified memory location.
63/// To minimize caching, the data is flagged as non-temporal (unlikely to be
64/// used again soon).
65///
66/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_stream_si64)
67///
68/// # Safety of non-temporal stores
69///
70/// After using this intrinsic, but before any other access to the memory that this intrinsic
71/// mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In
72/// particular, functions that call this intrinsic should generally call `_mm_sfence` before they
73/// return.
74///
75/// See [`_mm_sfence`] for details.
76#[inline]
77#[target_feature(enable = "sse2")]
78#[cfg_attr(test, assert_instr(movnti))]
79#[stable(feature = "simd_x86", since = "1.27.0")]
80pub unsafe fn _mm_stream_si64(mem_addr: *mut i64, a: i64) {
81 // see #1541, we should use inline asm to be sure, because LangRef isn't clear enough
82 crate::arch::asm!(
83 vps!("movnti", ",{a}"),
84 p = in(reg) mem_addr,
85 a = in(reg) a,
86 options(nostack, preserves_flags),
87 );
88}
89
90/// Returns a vector whose lowest element is `a` and all higher elements are
91/// `0`.
92///
93/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi64_si128)
94#[inline]
95#[target_feature(enable = "sse2")]
96#[cfg_attr(test, assert_instr(movq))]
97#[stable(feature = "simd_x86", since = "1.27.0")]
98pub fn _mm_cvtsi64_si128(a: i64) -> __m128i {
99 _mm_set_epi64x(e1:0, e0:a)
100}
101
102/// Returns a vector whose lowest element is `a` and all higher elements are
103/// `0`.
104///
105/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi64x_si128)
106#[inline]
107#[target_feature(enable = "sse2")]
108#[cfg_attr(test, assert_instr(movq))]
109#[stable(feature = "simd_x86", since = "1.27.0")]
110pub fn _mm_cvtsi64x_si128(a: i64) -> __m128i {
111 _mm_cvtsi64_si128(a)
112}
113
114/// Returns the lowest element of `a`.
115///
116/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi128_si64)
117#[inline]
118#[target_feature(enable = "sse2")]
119#[cfg_attr(test, assert_instr(movq))]
120#[stable(feature = "simd_x86", since = "1.27.0")]
121pub fn _mm_cvtsi128_si64(a: __m128i) -> i64 {
122 unsafe { simd_extract!(a.as_i64x2(), 0) }
123}
124
125/// Returns the lowest element of `a`.
126///
127/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi128_si64x)
128#[inline]
129#[target_feature(enable = "sse2")]
130#[cfg_attr(test, assert_instr(movq))]
131#[stable(feature = "simd_x86", since = "1.27.0")]
132pub fn _mm_cvtsi128_si64x(a: __m128i) -> i64 {
133 _mm_cvtsi128_si64(a)
134}
135
136/// Returns `a` with its lower element replaced by `b` after converting it to
137/// an `f64`.
138///
139/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi64_sd)
140#[inline]
141#[target_feature(enable = "sse2")]
142#[cfg_attr(test, assert_instr(cvtsi2sd))]
143#[stable(feature = "simd_x86", since = "1.27.0")]
144pub fn _mm_cvtsi64_sd(a: __m128d, b: i64) -> __m128d {
145 unsafe { simd_insert!(a, 0, b as f64) }
146}
147
148/// Returns `a` with its lower element replaced by `b` after converting it to
149/// an `f64`.
150///
151/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi64x_sd)
152#[inline]
153#[target_feature(enable = "sse2")]
154#[cfg_attr(test, assert_instr(cvtsi2sd))]
155#[stable(feature = "simd_x86", since = "1.27.0")]
156pub fn _mm_cvtsi64x_sd(a: __m128d, b: i64) -> __m128d {
157 _mm_cvtsi64_sd(a, b)
158}
159
160#[cfg(test)]
161mod tests {
162 use crate::core_arch::arch::x86_64::*;
163 use std::boxed;
164 use std::ptr;
165 use stdarch_test::simd_test;
166
167 #[simd_test(enable = "sse2")]
168 unsafe fn test_mm_cvtsd_si64() {
169 let r = _mm_cvtsd_si64(_mm_setr_pd(-2.0, 5.0));
170 assert_eq!(r, -2_i64);
171
172 let r = _mm_cvtsd_si64(_mm_setr_pd(f64::MAX, f64::MIN));
173 assert_eq!(r, i64::MIN);
174 }
175
176 #[simd_test(enable = "sse2")]
177 unsafe fn test_mm_cvtsd_si64x() {
178 let r = _mm_cvtsd_si64x(_mm_setr_pd(f64::NAN, f64::NAN));
179 assert_eq!(r, i64::MIN);
180 }
181
182 #[simd_test(enable = "sse2")]
183 unsafe fn test_mm_cvttsd_si64() {
184 let a = _mm_setr_pd(-1.1, 2.2);
185 let r = _mm_cvttsd_si64(a);
186 assert_eq!(r, -1_i64);
187 }
188
189 #[simd_test(enable = "sse2")]
190 unsafe fn test_mm_cvttsd_si64x() {
191 let a = _mm_setr_pd(f64::NEG_INFINITY, f64::NAN);
192 let r = _mm_cvttsd_si64x(a);
193 assert_eq!(r, i64::MIN);
194 }
195
196 #[simd_test(enable = "sse2")]
197 // Miri cannot support this until it is clear how it fits in the Rust memory model
198 // (non-temporal store)
199 #[cfg_attr(miri, ignore)]
200 unsafe fn test_mm_stream_si64() {
201 let a: i64 = 7;
202 let mut mem = boxed::Box::<i64>::new(-1);
203 _mm_stream_si64(ptr::addr_of_mut!(*mem), a);
204 _mm_sfence();
205 assert_eq!(a, *mem);
206 }
207
208 #[simd_test(enable = "sse2")]
209 unsafe fn test_mm_cvtsi64_si128() {
210 let r = _mm_cvtsi64_si128(5);
211 assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
212 }
213
214 #[simd_test(enable = "sse2")]
215 unsafe fn test_mm_cvtsi128_si64() {
216 let r = _mm_cvtsi128_si64(_mm_setr_epi64x(5, 0));
217 assert_eq!(r, 5);
218 }
219
220 #[simd_test(enable = "sse2")]
221 unsafe fn test_mm_cvtsi64_sd() {
222 let a = _mm_set1_pd(3.5);
223 let r = _mm_cvtsi64_sd(a, 5);
224 assert_eq_m128d(r, _mm_setr_pd(5.0, 3.5));
225 }
226}
227