| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
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| 4 | * http://www.samsung.com |
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| 5 | * |
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| 6 | * Exynos low-level resume code |
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| 7 | */ |
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| 8 | |
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| 9 | #include <linux/linkage.h> |
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| 10 | #include <asm/asm-offsets.h> |
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| 11 | #include <asm/hardware/cache-l2x0.h> |
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| 12 | #include "smc.h" |
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| 13 | |
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| 14 | #define CPU_MASK 0xff0ffff0 |
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| 15 | #define CPU_CORTEX_A9 0x410fc090 |
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| 16 | |
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| 17 | .text |
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| 18 | .align |
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| 19 | |
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| 20 | /* |
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| 21 | * sleep magic, to allow the bootloader to check for an valid |
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| 22 | * image to resume to. Must be the first word before the |
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| 23 | * exynos_cpu_resume entry. |
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| 24 | */ |
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| 25 | |
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| 26 | .word 0x2bedf00d |
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| 27 | |
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| 28 | /* |
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| 29 | * exynos_cpu_resume |
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| 30 | * |
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| 31 | * resume code entry for bootloader to call |
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| 32 | */ |
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| 33 | |
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| 34 | ENTRY(exynos_cpu_resume) |
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| 35 | #ifdef CONFIG_CACHE_L2X0 |
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| 36 | mrc p15, 0, r0, c0, c0, 0 |
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| 37 | ldr r1, =CPU_MASK |
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| 38 | and r0, r0, r1 |
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| 39 | ldr r1, =CPU_CORTEX_A9 |
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| 40 | cmp r0, r1 |
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| 41 | bleq l2c310_early_resume |
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| 42 | #endif |
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| 43 | b cpu_resume |
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| 44 | ENDPROC(exynos_cpu_resume) |
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| 45 | |
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| 46 | .align |
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| 47 | .arch armv7-a |
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| 48 | .arch_extension sec |
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| 49 | ENTRY(exynos_cpu_resume_ns) |
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| 50 | mrc p15, 0, r0, c0, c0, 0 |
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| 51 | ldr r1, =CPU_MASK |
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| 52 | and r0, r0, r1 |
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| 53 | ldr r1, =CPU_CORTEX_A9 |
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| 54 | cmp r0, r1 |
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| 55 | bne skip_cp15 |
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| 56 | |
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| 57 | adr r0, _cp15_save_power |
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| 58 | ldr r1, [r0] |
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| 59 | ldr r1, [r0, r1] |
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| 60 | adr r0, _cp15_save_diag |
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| 61 | ldr r2, [r0] |
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| 62 | ldr r2, [r0, r2] |
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| 63 | mov r0, #SMC_CMD_C15RESUME |
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| 64 | dsb |
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| 65 | smc #0 |
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| 66 | #ifdef CONFIG_CACHE_L2X0 |
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| 67 | adr r0, 1f |
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| 68 | ldr r2, [r0] |
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| 69 | add r0, r2, r0 |
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| 70 | |
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| 71 | /* Check that the address has been initialised. */ |
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| 72 | ldr r1, [r0, #L2X0_R_PHY_BASE] |
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| 73 | teq r1, #0 |
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| 74 | beq skip_l2x0 |
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| 75 | |
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| 76 | /* Check if controller has been enabled. */ |
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| 77 | ldr r2, [r1, #L2X0_CTRL] |
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| 78 | tst r2, #0x1 |
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| 79 | bne skip_l2x0 |
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| 80 | |
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| 81 | ldr r1, [r0, #L2X0_R_TAG_LATENCY] |
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| 82 | ldr r2, [r0, #L2X0_R_DATA_LATENCY] |
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| 83 | ldr r3, [r0, #L2X0_R_PREFETCH_CTRL] |
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| 84 | mov r0, #SMC_CMD_L2X0SETUP1 |
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| 85 | smc #0 |
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| 86 | |
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| 87 | /* Reload saved regs pointer because smc corrupts registers. */ |
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| 88 | adr r0, 1f |
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| 89 | ldr r2, [r0] |
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| 90 | add r0, r2, r0 |
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| 91 | |
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| 92 | ldr r1, [r0, #L2X0_R_PWR_CTRL] |
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| 93 | ldr r2, [r0, #L2X0_R_AUX_CTRL] |
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| 94 | mov r0, #SMC_CMD_L2X0SETUP2 |
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| 95 | smc #0 |
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| 96 | |
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| 97 | mov r0, #SMC_CMD_L2X0INVALL |
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| 98 | smc #0 |
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| 99 | |
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| 100 | mov r1, #1 |
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| 101 | mov r0, #SMC_CMD_L2X0CTRL |
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| 102 | smc #0 |
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| 103 | skip_l2x0: |
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| 104 | #endif /* CONFIG_CACHE_L2X0 */ |
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| 105 | skip_cp15: |
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| 106 | b cpu_resume |
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| 107 | ENDPROC(exynos_cpu_resume_ns) |
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| 108 | |
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| 109 | .align |
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| 110 | _cp15_save_power: |
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| 111 | .long cp15_save_power - . |
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| 112 | _cp15_save_diag: |
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| 113 | .long cp15_save_diag - . |
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| 114 | #ifdef CONFIG_CACHE_L2X0 |
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| 115 | 1: .long l2x0_saved_regs - . |
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| 116 | #endif /* CONFIG_CACHE_L2X0 */ |
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| 117 | |
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| 118 | .data |
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| 119 | .align 2 |
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| 120 | .globl cp15_save_diag |
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| 121 | cp15_save_diag: |
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| 122 | .long 0 @ cp15 diagnostic |
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| 123 | .globl cp15_save_power |
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| 124 | cp15_save_power: |
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| 125 | .long 0 @ cp15 power control |
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| 126 | |
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