1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/mach-tegra/reset.h
4 *
5 * CPU reset dispatcher.
6 *
7 * Copyright (c) 2011, NVIDIA Corporation.
8 */
9
10#ifndef __MACH_TEGRA_RESET_H
11#define __MACH_TEGRA_RESET_H
12
13#define TEGRA_RESET_MASK_PRESENT 0
14#define TEGRA_RESET_MASK_LP1 1
15#define TEGRA_RESET_MASK_LP2 2
16#define TEGRA_RESET_STARTUP_SECONDARY 3
17#define TEGRA_RESET_STARTUP_LP2 4
18#define TEGRA_RESET_STARTUP_LP1 5
19#define TEGRA_RESET_TF_PRESENT 6
20#define TEGRA_RESET_DATA_SIZE 7
21
22#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
23
24#ifndef __ASSEMBLY__
25
26#include "irammap.h"
27
28extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
29
30void __tegra_cpu_reset_handler_start(void);
31void __tegra_cpu_reset_handler(void);
32void __tegra20_cpu1_resettable_status_offset(void);
33void __tegra_cpu_reset_handler_end(void);
34
35#ifdef CONFIG_PM_SLEEP
36#define tegra_cpu_lp1_mask \
37 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
38 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
39 (u32)__tegra_cpu_reset_handler_start)))
40#define tegra_cpu_lp2_mask \
41 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
42 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
43 (u32)__tegra_cpu_reset_handler_start)))
44#endif
45
46#define tegra_cpu_reset_handler_offset \
47 ((u32)__tegra_cpu_reset_handler - \
48 (u32)__tegra_cpu_reset_handler_start)
49
50#define tegra_cpu_reset_handler_size \
51 (__tegra_cpu_reset_handler_end - \
52 __tegra_cpu_reset_handler_start)
53
54void __init tegra_cpu_reset_handler_init(void);
55
56#endif
57#endif
58

source code of linux/arch/arm/mach-tegra/reset.h