| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #include <linux/linkage.h> |
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| 3 | #include <asm/assembler.h> |
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| 4 | #include "abort-macro.S" |
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| 5 | /* |
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| 6 | * Function: v6_early_abort |
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| 7 | * |
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| 8 | * Params : r2 = pt_regs |
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| 9 | * : r4 = aborted context pc |
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| 10 | * : r5 = aborted context psr |
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| 11 | * |
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| 12 | * Returns : r4 - r11, r13 preserved |
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| 13 | * |
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| 14 | * Purpose : obtain information about current aborted instruction. |
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| 15 | * Note: we read user space. This means we might cause a data |
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| 16 | * abort here if the I-TLB and D-TLB aren't seeing the same |
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| 17 | * picture. Unfortunately, this does happen. We live with it. |
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| 18 | */ |
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| 19 | .arch armv6k |
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| 20 | .align 5 |
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| 21 | ENTRY(v6_early_abort) |
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| 22 | mrc p15, 0, r1, c5, c0, 0 @ get FSR |
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| 23 | mrc p15, 0, r0, c6, c0, 0 @ get FAR |
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| 24 | /* |
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| 25 | * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. |
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| 26 | */ |
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| 27 | #ifdef CONFIG_ARM_ERRATA_326103 |
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| 28 | ldr ip, =0x4107b36 |
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| 29 | mrc p15, 0, r3, c0, c0, 0 @ get processor id |
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| 30 | teq ip, r3, lsr #4 @ r0 ARM1136? |
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| 31 | bne 1f |
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| 32 | tst r5, #PSR_J_BIT @ Java? |
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| 33 | tsteq r5, #PSR_T_BIT @ Thumb? |
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| 34 | bne 1f |
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| 35 | bic r1, r1, #1 << 11 @ clear bit 11 of FSR |
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| 36 | ldr r3, [r4] @ read aborted ARM instruction |
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| 37 | ARM_BE8(rev r3, r3) |
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| 38 | |
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| 39 | teq_ldrd tmp=ip, insn=r3 @ insn was LDRD? |
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| 40 | beq 1f @ yes |
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| 41 | tst r3, #1 << 20 @ L = 0 -> write |
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| 42 | orreq r1, r1, #1 << 11 @ yes. |
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| 43 | #endif |
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| 44 | 1: uaccess_disable ip @ disable userspace access |
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| 45 | b do_DataAbort |
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| 46 | |
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