1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * pci.c -- basic PCI support code |
4 | * |
5 | * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> |
6 | */ |
7 | |
8 | #include <linux/kernel.h> |
9 | #include <linux/types.h> |
10 | #include <linux/mm.h> |
11 | #include <linux/init.h> |
12 | #include <linux/pci.h> |
13 | |
14 | /* |
15 | * From arch/i386/kernel/pci-i386.c: |
16 | * |
17 | * We need to avoid collisions with `mirrored' VGA ports |
18 | * and other strange ISA hardware, so we always want the |
19 | * addresses to be allocated in the 0x000-0x0ff region |
20 | * modulo 0x400. |
21 | * |
22 | * Why? Because some silly external IO cards only decode |
23 | * the low 10 bits of the IO address. The 0x00-0xff region |
24 | * is reserved for motherboard devices that decode all 16 |
25 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, |
26 | * but we want to try to avoid allocating at 0x2900-0x2bff |
27 | * which might be mirrored at 0x0100-0x03ff.. |
28 | */ |
29 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
30 | resource_size_t size, resource_size_t align) |
31 | { |
32 | resource_size_t start = res->start; |
33 | |
34 | if ((res->flags & IORESOURCE_IO) && (start & 0x300)) |
35 | start = (start + 0x3ff) & ~0x3ff; |
36 | |
37 | start = (start + align - 1) & ~(align - 1); |
38 | |
39 | return start; |
40 | } |
41 | |
42 | /* |
43 | * This is taken from the ARM code for this. |
44 | */ |
45 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
46 | { |
47 | struct resource *r; |
48 | u16 cmd, newcmd; |
49 | int idx; |
50 | |
51 | pci_read_config_word(dev, PCI_COMMAND, val: &cmd); |
52 | newcmd = cmd; |
53 | |
54 | for (idx = 0; idx < 6; idx++) { |
55 | /* Only set up the requested stuff */ |
56 | if (!(mask & (1 << idx))) |
57 | continue; |
58 | |
59 | r = dev->resource + idx; |
60 | if (!r->start && r->end) { |
61 | pr_err("PCI: Device %s not available because of resource collisions\n" , |
62 | pci_name(dev)); |
63 | return -EINVAL; |
64 | } |
65 | if (r->flags & IORESOURCE_IO) |
66 | newcmd |= PCI_COMMAND_IO; |
67 | if (r->flags & IORESOURCE_MEM) |
68 | newcmd |= PCI_COMMAND_MEMORY; |
69 | } |
70 | |
71 | /* |
72 | * Bridges (eg, cardbus bridges) need to be fully enabled |
73 | */ |
74 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) |
75 | newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
76 | |
77 | |
78 | if (newcmd != cmd) { |
79 | pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n" , |
80 | pci_name(dev), cmd, newcmd); |
81 | pci_write_config_word(dev, PCI_COMMAND, val: newcmd); |
82 | } |
83 | return 0; |
84 | } |
85 | |
86 | void pcibios_fixup_bus(struct pci_bus *bus) |
87 | { |
88 | struct pci_dev *dev; |
89 | |
90 | list_for_each_entry(dev, &bus->devices, bus_list) { |
91 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, val: 8); |
92 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, val: 32); |
93 | } |
94 | } |
95 | |