1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * Copyright (C) 1997, 1998 Ralf Baechle |
7 | * Copyright (C) 1999 SuSE GmbH |
8 | * Copyright (C) 1999-2001 Hewlett-Packard Company |
9 | * Copyright (C) 1999-2001 Grant Grundler |
10 | */ |
11 | #include <linux/eisa.h> |
12 | #include <linux/init.h> |
13 | #include <linux/module.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/pci.h> |
16 | #include <linux/types.h> |
17 | |
18 | #include <asm/io.h> |
19 | #include <asm/superio.h> |
20 | |
21 | #define DEBUG_RESOURCES 0 |
22 | #define DEBUG_CONFIG 0 |
23 | |
24 | #if DEBUG_CONFIG |
25 | # define DBGC(x...) printk(KERN_DEBUG x) |
26 | #else |
27 | # define DBGC(x...) |
28 | #endif |
29 | |
30 | |
31 | #if DEBUG_RESOURCES |
32 | #define DBG_RES(x...) printk(KERN_DEBUG x) |
33 | #else |
34 | #define DBG_RES(x...) |
35 | #endif |
36 | |
37 | struct pci_port_ops *pci_port __ro_after_init; |
38 | struct pci_bios_ops *pci_bios __ro_after_init; |
39 | |
40 | static int pci_hba_count __ro_after_init; |
41 | |
42 | /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */ |
43 | #define PCI_HBA_MAX 32 |
44 | static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __ro_after_init; |
45 | |
46 | |
47 | /******************************************************************** |
48 | ** |
49 | ** I/O port space support |
50 | ** |
51 | *********************************************************************/ |
52 | |
53 | /* EISA port numbers and PCI port numbers share the same interface. Some |
54 | * machines have both EISA and PCI adapters installed. Rather than turn |
55 | * pci_port into an array, we reserve bus 0 for EISA and call the EISA |
56 | * routines if the access is to a port on bus 0. We don't want to fix |
57 | * EISA and ISA drivers which assume port space is <= 0xffff. |
58 | */ |
59 | |
60 | #ifdef CONFIG_EISA |
61 | #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr) |
62 | #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr) |
63 | #else |
64 | #define EISA_IN(size) |
65 | #define EISA_OUT(size) |
66 | #endif |
67 | |
68 | #define PCI_PORT_IN(type, size) \ |
69 | u##size in##type (int addr) \ |
70 | { \ |
71 | int b = PCI_PORT_HBA(addr); \ |
72 | EISA_IN(size); \ |
73 | if (!parisc_pci_hba[b]) return (u##size) -1; \ |
74 | return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \ |
75 | } \ |
76 | EXPORT_SYMBOL(in##type); |
77 | |
78 | PCI_PORT_IN(b, 8) |
79 | PCI_PORT_IN(w, 16) |
80 | PCI_PORT_IN(l, 32) |
81 | |
82 | |
83 | #define PCI_PORT_OUT(type, size) \ |
84 | void out##type (u##size d, int addr) \ |
85 | { \ |
86 | int b = PCI_PORT_HBA(addr); \ |
87 | EISA_OUT(size); \ |
88 | if (!parisc_pci_hba[b]) return; \ |
89 | pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \ |
90 | } \ |
91 | EXPORT_SYMBOL(out##type); |
92 | |
93 | PCI_PORT_OUT(b, 8) |
94 | PCI_PORT_OUT(w, 16) |
95 | PCI_PORT_OUT(l, 32) |
96 | |
97 | |
98 | |
99 | /* |
100 | * BIOS32 replacement. |
101 | */ |
102 | static int __init pcibios_init(void) |
103 | { |
104 | if (!pci_bios) |
105 | return -1; |
106 | |
107 | if (pci_bios->init) { |
108 | pci_bios->init(); |
109 | } else { |
110 | printk(KERN_WARNING "pci_bios != NULL but init() is!\n" ); |
111 | } |
112 | |
113 | /* Set the CLS for PCI as early as possible. */ |
114 | pci_cache_line_size = pci_dfl_cache_line_size; |
115 | |
116 | return 0; |
117 | } |
118 | |
119 | |
120 | /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */ |
121 | void pcibios_fixup_bus(struct pci_bus *bus) |
122 | { |
123 | if (pci_bios->fixup_bus) { |
124 | pci_bios->fixup_bus(bus); |
125 | } else { |
126 | printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n" ); |
127 | } |
128 | } |
129 | |
130 | |
131 | /* |
132 | * Called by pci_set_master() - a driver interface. |
133 | * |
134 | * Legacy PDC guarantees to set: |
135 | * Map Memory BAR's into PA IO space. |
136 | * Map Expansion ROM BAR into one common PA IO space per bus. |
137 | * Map IO BAR's into PCI IO space. |
138 | * Command (see below) |
139 | * Cache Line Size |
140 | * Latency Timer |
141 | * Interrupt Line |
142 | * PPB: secondary latency timer, io/mmio base/limit, |
143 | * bus numbers, bridge control |
144 | * |
145 | */ |
146 | void pcibios_set_master(struct pci_dev *dev) |
147 | { |
148 | u8 lat; |
149 | |
150 | /* If someone already mucked with this, don't touch it. */ |
151 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, val: &lat); |
152 | if (lat >= 16) return; |
153 | |
154 | /* |
155 | ** HP generally has fewer devices on the bus than other architectures. |
156 | ** upper byte is PCI_LATENCY_TIMER. |
157 | */ |
158 | pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, |
159 | val: (0x80 << 8) | pci_cache_line_size); |
160 | } |
161 | |
162 | /* |
163 | * pcibios_init_bridge() initializes cache line and default latency |
164 | * for pci controllers and pci-pci bridges |
165 | */ |
166 | void __ref pcibios_init_bridge(struct pci_dev *dev) |
167 | { |
168 | unsigned short bridge_ctl, bridge_ctl_new; |
169 | |
170 | /* We deal only with pci controllers and pci-pci bridges. */ |
171 | if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
172 | return; |
173 | |
174 | /* PCI-PCI bridge - set the cache line and default latency |
175 | * (32) for primary and secondary buses. |
176 | */ |
177 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, val: 32); |
178 | |
179 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, val: &bridge_ctl); |
180 | |
181 | bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY | |
182 | PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT; |
183 | dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n" , |
184 | bridge_ctl, bridge_ctl_new); |
185 | |
186 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, val: bridge_ctl_new); |
187 | } |
188 | |
189 | /* |
190 | * pcibios align resources() is called every time generic PCI code |
191 | * wants to generate a new address. The process of looking for |
192 | * an available address, each candidate is first "aligned" and |
193 | * then checked if the resource is available until a match is found. |
194 | * |
195 | * Since we are just checking candidates, don't use any fields other |
196 | * than res->start. |
197 | */ |
198 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
199 | resource_size_t size, resource_size_t alignment) |
200 | { |
201 | resource_size_t mask, align, start = res->start; |
202 | |
203 | DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n" , |
204 | pci_name(((struct pci_dev *) data)), |
205 | res->parent, res->start, res->end, |
206 | (int) res->flags, size, alignment); |
207 | |
208 | /* If it's not IO, then it's gotta be MEM */ |
209 | align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; |
210 | |
211 | /* Align to largest of MIN or input size */ |
212 | mask = max(alignment, align) - 1; |
213 | start += mask; |
214 | start &= ~mask; |
215 | |
216 | return start; |
217 | } |
218 | |
219 | /* |
220 | * A driver is enabling the device. We make sure that all the appropriate |
221 | * bits are set to allow the device to operate as the driver is expecting. |
222 | * We enable the port IO and memory IO bits if the device has any BARs of |
223 | * that type, and we enable the PERR and SERR bits unconditionally. |
224 | * Drivers that do not need parity (eg graphics and possibly networking) |
225 | * can clear these bits if they want. |
226 | */ |
227 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
228 | { |
229 | int err; |
230 | u16 cmd, old_cmd; |
231 | |
232 | err = pci_enable_resources(dev, mask); |
233 | if (err < 0) |
234 | return err; |
235 | |
236 | pci_read_config_word(dev, PCI_COMMAND, val: &cmd); |
237 | old_cmd = cmd; |
238 | |
239 | cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); |
240 | |
241 | #if 0 |
242 | /* If bridge/bus controller has FBB enabled, child must too. */ |
243 | if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK) |
244 | cmd |= PCI_COMMAND_FAST_BACK; |
245 | #endif |
246 | |
247 | if (cmd != old_cmd) { |
248 | dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n" , |
249 | old_cmd, cmd); |
250 | pci_write_config_word(dev, PCI_COMMAND, val: cmd); |
251 | } |
252 | return 0; |
253 | } |
254 | |
255 | |
256 | /* PA-RISC specific */ |
257 | void pcibios_register_hba(struct pci_hba_data *hba) |
258 | { |
259 | if (pci_hba_count >= PCI_HBA_MAX) { |
260 | printk(KERN_ERR "PCI: Too many Host Bus Adapters\n" ); |
261 | return; |
262 | } |
263 | |
264 | parisc_pci_hba[pci_hba_count] = hba; |
265 | hba->hba_num = pci_hba_count++; |
266 | } |
267 | |
268 | subsys_initcall(pcibios_init); |
269 | |