1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * ULI M1575 setup code - specific to Freescale boards |
4 | * |
5 | * Copyright 2007 Freescale Semiconductor Inc. |
6 | */ |
7 | |
8 | #include <linux/stddef.h> |
9 | #include <linux/kernel.h> |
10 | #include <linux/pci.h> |
11 | #include <linux/interrupt.h> |
12 | #include <linux/mc146818rtc.h> |
13 | #include <linux/of_irq.h> |
14 | |
15 | #include <asm/pci-bridge.h> |
16 | #include <asm/ppc-pci.h> |
17 | |
18 | #include <sysdev/fsl_pci.h> |
19 | |
20 | #define ULI_PIRQA 0x08 |
21 | #define ULI_PIRQB 0x09 |
22 | #define ULI_PIRQC 0x0a |
23 | #define ULI_PIRQD 0x0b |
24 | #define ULI_PIRQE 0x0c |
25 | #define ULI_PIRQF 0x0d |
26 | #define ULI_PIRQG 0x0e |
27 | |
28 | #define ULI_8259_NONE 0x00 |
29 | #define ULI_8259_IRQ1 0x08 |
30 | #define ULI_8259_IRQ3 0x02 |
31 | #define ULI_8259_IRQ4 0x04 |
32 | #define ULI_8259_IRQ5 0x05 |
33 | #define ULI_8259_IRQ6 0x07 |
34 | #define ULI_8259_IRQ7 0x06 |
35 | #define ULI_8259_IRQ9 0x01 |
36 | #define ULI_8259_IRQ10 0x03 |
37 | #define ULI_8259_IRQ11 0x09 |
38 | #define ULI_8259_IRQ12 0x0b |
39 | #define ULI_8259_IRQ14 0x0d |
40 | #define ULI_8259_IRQ15 0x0f |
41 | |
42 | static u8 uli_pirq_to_irq[8] = { |
43 | ULI_8259_IRQ9, /* PIRQA */ |
44 | ULI_8259_IRQ10, /* PIRQB */ |
45 | ULI_8259_IRQ11, /* PIRQC */ |
46 | ULI_8259_IRQ12, /* PIRQD */ |
47 | ULI_8259_IRQ5, /* PIRQE */ |
48 | ULI_8259_IRQ6, /* PIRQF */ |
49 | ULI_8259_IRQ7, /* PIRQG */ |
50 | ULI_8259_NONE, /* PIRQH */ |
51 | }; |
52 | |
53 | static inline bool is_quirk_valid(void) |
54 | { |
55 | return (machine_is(mpc86xx_hpcn) || |
56 | machine_is(mpc8544_ds) || |
57 | machine_is(p2020_ds) || |
58 | machine_is(mpc8572_ds)); |
59 | } |
60 | |
61 | /* Bridge */ |
62 | static void early_uli5249(struct pci_dev *dev) |
63 | { |
64 | unsigned char temp; |
65 | |
66 | if (!is_quirk_valid()) |
67 | return; |
68 | |
69 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | |
70 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
71 | |
72 | /* read/write lock */ |
73 | pci_read_config_byte(dev, where: 0x7c, val: &temp); |
74 | pci_write_config_byte(dev, where: 0x7c, val: 0x80); |
75 | |
76 | /* set as P2P bridge */ |
77 | pci_write_config_byte(dev, PCI_CLASS_PROG, val: 0x01); |
78 | dev->class |= 0x1; |
79 | |
80 | /* restore lock */ |
81 | pci_write_config_byte(dev, where: 0x7c, val: temp); |
82 | } |
83 | |
84 | |
85 | static void quirk_uli1575(struct pci_dev *dev) |
86 | { |
87 | int i; |
88 | |
89 | if (!is_quirk_valid()) |
90 | return; |
91 | |
92 | /* |
93 | * ULI1575 interrupts route setup |
94 | */ |
95 | |
96 | /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */ |
97 | for (i = 0; i < 4; i++) { |
98 | u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4); |
99 | pci_write_config_byte(dev, where: 0x48 + i, val); |
100 | } |
101 | |
102 | /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */ |
103 | pci_write_config_byte(dev, where: 0x86, ULI_PIRQD); |
104 | |
105 | /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */ |
106 | pci_write_config_byte(dev, where: 0x87, ULI_PIRQA); |
107 | |
108 | /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */ |
109 | pci_write_config_byte(dev, where: 0x88, ULI_PIRQB); |
110 | |
111 | /* Lan controller: dev 27, func 0 - IRQ6 */ |
112 | pci_write_config_byte(dev, where: 0x89, ULI_PIRQF); |
113 | |
114 | /* AC97 Audio controller: dev 29, func 0 - IRQ6 */ |
115 | pci_write_config_byte(dev, where: 0x8a, ULI_PIRQF); |
116 | |
117 | /* Modem controller: dev 29, func 1 - IRQ6 */ |
118 | pci_write_config_byte(dev, where: 0x8b, ULI_PIRQF); |
119 | |
120 | /* HD Audio controller: dev 29, func 2 - IRQ6 */ |
121 | pci_write_config_byte(dev, where: 0x8c, ULI_PIRQF); |
122 | |
123 | /* SATA controller: dev 31, func 1 - IRQ5 */ |
124 | pci_write_config_byte(dev, where: 0x8d, ULI_PIRQE); |
125 | |
126 | /* SMB interrupt: dev 30, func 1 - IRQ7 */ |
127 | pci_write_config_byte(dev, where: 0x8e, ULI_PIRQG); |
128 | |
129 | /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */ |
130 | pci_write_config_byte(dev, where: 0x8f, ULI_PIRQG); |
131 | |
132 | /* USB 2.0 controller: dev 28, func 3 */ |
133 | pci_write_config_byte(dev, where: 0x74, ULI_8259_IRQ11); |
134 | |
135 | /* Primary PATA IDE IRQ: 14 |
136 | * Secondary PATA IDE IRQ: 15 |
137 | */ |
138 | pci_write_config_byte(dev, where: 0x44, val: 0x30 | ULI_8259_IRQ14); |
139 | pci_write_config_byte(dev, where: 0x75, ULI_8259_IRQ15); |
140 | } |
141 | |
142 | static void quirk_final_uli1575(struct pci_dev *dev) |
143 | { |
144 | /* Set i8259 interrupt trigger |
145 | * IRQ 3: Level |
146 | * IRQ 4: Level |
147 | * IRQ 5: Level |
148 | * IRQ 6: Level |
149 | * IRQ 7: Level |
150 | * IRQ 9: Level |
151 | * IRQ 10: Level |
152 | * IRQ 11: Level |
153 | * IRQ 12: Level |
154 | * IRQ 14: Edge |
155 | * IRQ 15: Edge |
156 | */ |
157 | if (!is_quirk_valid()) |
158 | return; |
159 | |
160 | outb(value: 0xfa, port: 0x4d0); |
161 | outb(value: 0x1e, port: 0x4d1); |
162 | |
163 | /* setup RTC */ |
164 | CMOS_WRITE(RTC_SET, RTC_CONTROL); |
165 | CMOS_WRITE(RTC_24H, RTC_CONTROL); |
166 | |
167 | /* ensure month, date, and week alarm fields are ignored */ |
168 | CMOS_WRITE(0, RTC_VALID); |
169 | |
170 | outb_p(value: 0x7c, port: 0x72); |
171 | outb_p(RTC_ALARM_DONT_CARE, port: 0x73); |
172 | |
173 | outb_p(value: 0x7d, port: 0x72); |
174 | outb_p(RTC_ALARM_DONT_CARE, port: 0x73); |
175 | } |
176 | |
177 | /* SATA */ |
178 | static void quirk_uli5288(struct pci_dev *dev) |
179 | { |
180 | unsigned char c; |
181 | unsigned int d; |
182 | |
183 | if (!is_quirk_valid()) |
184 | return; |
185 | |
186 | /* read/write lock */ |
187 | pci_read_config_byte(dev, where: 0x83, val: &c); |
188 | pci_write_config_byte(dev, where: 0x83, val: c|0x80); |
189 | |
190 | pci_read_config_dword(dev, PCI_CLASS_REVISION, val: &d); |
191 | d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8); |
192 | pci_write_config_dword(dev, PCI_CLASS_REVISION, val: d); |
193 | |
194 | /* restore lock */ |
195 | pci_write_config_byte(dev, where: 0x83, val: c); |
196 | |
197 | /* disable emulated PATA mode enabled */ |
198 | pci_read_config_byte(dev, where: 0x84, val: &c); |
199 | pci_write_config_byte(dev, where: 0x84, val: c & ~0x01); |
200 | } |
201 | |
202 | /* PATA */ |
203 | static void quirk_uli5229(struct pci_dev *dev) |
204 | { |
205 | unsigned short temp; |
206 | |
207 | if (!is_quirk_valid()) |
208 | return; |
209 | |
210 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | |
211 | PCI_COMMAND_MASTER | PCI_COMMAND_IO); |
212 | |
213 | /* Enable Native IRQ 14/15 */ |
214 | pci_read_config_word(dev, where: 0x4a, val: &temp); |
215 | pci_write_config_word(dev, where: 0x4a, val: temp | 0x1000); |
216 | } |
217 | |
218 | /* We have to do a dummy read on the P2P for the RTC to work, WTF */ |
219 | static void quirk_final_uli5249(struct pci_dev *dev) |
220 | { |
221 | int i; |
222 | u8 *dummy; |
223 | struct pci_bus *bus = dev->bus; |
224 | struct resource *res; |
225 | resource_size_t end = 0; |
226 | |
227 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) { |
228 | unsigned long flags = pci_resource_flags(dev, i); |
229 | if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM) |
230 | end = pci_resource_end(dev, i); |
231 | } |
232 | |
233 | pci_bus_for_each_resource(bus, res, i) { |
234 | if (res && res->flags & IORESOURCE_MEM) { |
235 | if (res->end == end) |
236 | dummy = ioremap(offset: res->start, size: 0x4); |
237 | else |
238 | dummy = ioremap(offset: res->end - 3, size: 0x4); |
239 | if (dummy) { |
240 | in_8(dummy); |
241 | iounmap(addr: dummy); |
242 | } |
243 | break; |
244 | } |
245 | } |
246 | } |
247 | |
248 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); |
249 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575); |
250 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); |
251 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); |
252 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249); |
253 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575); |
254 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); |
255 | |
256 | static void hpcd_quirk_uli1575(struct pci_dev *dev) |
257 | { |
258 | u32 temp32; |
259 | |
260 | if (!machine_is(mpc86xx_hpcd)) |
261 | return; |
262 | |
263 | /* Disable INTx */ |
264 | pci_read_config_dword(dev, where: 0x48, val: &temp32); |
265 | pci_write_config_dword(dev, where: 0x48, val: (temp32 | 1<<26)); |
266 | |
267 | /* Enable sideband interrupt */ |
268 | pci_read_config_dword(dev, where: 0x90, val: &temp32); |
269 | pci_write_config_dword(dev, where: 0x90, val: (temp32 | 1<<22)); |
270 | } |
271 | |
272 | static void hpcd_quirk_uli5288(struct pci_dev *dev) |
273 | { |
274 | unsigned char c; |
275 | |
276 | if (!machine_is(mpc86xx_hpcd)) |
277 | return; |
278 | |
279 | pci_read_config_byte(dev, where: 0x83, val: &c); |
280 | c |= 0x80; |
281 | pci_write_config_byte(dev, where: 0x83, val: c); |
282 | |
283 | pci_write_config_byte(dev, PCI_CLASS_PROG, val: 0x01); |
284 | pci_write_config_byte(dev, PCI_CLASS_DEVICE, val: 0x06); |
285 | |
286 | pci_read_config_byte(dev, where: 0x83, val: &c); |
287 | c &= 0x7f; |
288 | pci_write_config_byte(dev, where: 0x83, val: c); |
289 | } |
290 | |
291 | /* |
292 | * Since 8259PIC was disabled on the board, the IDE device can not |
293 | * use the legacy IRQ, we need to let the IDE device work under |
294 | * native mode and use the interrupt line like other PCI devices. |
295 | * IRQ14 is a sideband interrupt from IDE device to CPU and we use this |
296 | * as the interrupt for IDE device. |
297 | */ |
298 | static void hpcd_quirk_uli5229(struct pci_dev *dev) |
299 | { |
300 | unsigned char c; |
301 | |
302 | if (!machine_is(mpc86xx_hpcd)) |
303 | return; |
304 | |
305 | pci_read_config_byte(dev, where: 0x4b, val: &c); |
306 | c |= 0x10; |
307 | pci_write_config_byte(dev, where: 0x4b, val: c); |
308 | } |
309 | |
310 | /* |
311 | * SATA interrupt pin bug fix |
312 | * There's a chip bug for 5288, The interrupt pin should be 2, |
313 | * not the read only value 1, So it use INTB#, not INTA# which |
314 | * actually used by the IDE device 5229. |
315 | * As of this bug, during the PCI initialization, 5288 read the |
316 | * irq of IDE device from the device tree, this function fix this |
317 | * bug by re-assigning a correct irq to 5288. |
318 | * |
319 | */ |
320 | static void hpcd_final_uli5288(struct pci_dev *dev) |
321 | { |
322 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
323 | struct device_node *hosenode = hose ? hose->dn : NULL; |
324 | struct of_phandle_args oirq; |
325 | u32 laddr[3]; |
326 | |
327 | if (!machine_is(mpc86xx_hpcd)) |
328 | return; |
329 | |
330 | if (!hosenode) |
331 | return; |
332 | |
333 | oirq.np = hosenode; |
334 | oirq.args[0] = 2; |
335 | oirq.args_count = 1; |
336 | laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8); |
337 | laddr[1] = laddr[2] = 0; |
338 | of_irq_parse_raw(addr: laddr, out_irq: &oirq); |
339 | dev->irq = irq_create_of_mapping(irq_data: &oirq); |
340 | } |
341 | |
342 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575); |
343 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288); |
344 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229); |
345 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288); |
346 | |
347 | static int uli_exclude_device(struct pci_controller *hose, u_char bus, u_char devfn) |
348 | { |
349 | if (hose->dn == fsl_pci_primary && bus == (hose->first_busno + 2)) { |
350 | /* exclude Modem controller */ |
351 | if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1)) |
352 | return PCIBIOS_DEVICE_NOT_FOUND; |
353 | |
354 | /* exclude HD Audio controller */ |
355 | if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2)) |
356 | return PCIBIOS_DEVICE_NOT_FOUND; |
357 | } |
358 | |
359 | return PCIBIOS_SUCCESSFUL; |
360 | } |
361 | |
362 | void __init uli_init(void) |
363 | { |
364 | struct device_node *node; |
365 | struct device_node *pci_with_uli; |
366 | |
367 | /* See if we have a ULI under the primary */ |
368 | |
369 | node = of_find_node_by_name(NULL, name: "uli1575" ); |
370 | while ((pci_with_uli = of_get_parent(node))) { |
371 | of_node_put(node); |
372 | node = pci_with_uli; |
373 | |
374 | if (pci_with_uli == fsl_pci_primary) { |
375 | ppc_md.pci_exclude_device = uli_exclude_device; |
376 | break; |
377 | } |
378 | } |
379 | } |
380 | |