1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * PowerNV Platform dependent EEH operations |
4 | * |
5 | * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. |
6 | */ |
7 | |
8 | #include <linux/atomic.h> |
9 | #include <linux/debugfs.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/export.h> |
12 | #include <linux/init.h> |
13 | #include <linux/interrupt.h> |
14 | #include <linux/irqdomain.h> |
15 | #include <linux/list.h> |
16 | #include <linux/msi.h> |
17 | #include <linux/of.h> |
18 | #include <linux/pci.h> |
19 | #include <linux/proc_fs.h> |
20 | #include <linux/rbtree.h> |
21 | #include <linux/sched.h> |
22 | #include <linux/seq_file.h> |
23 | #include <linux/spinlock.h> |
24 | |
25 | #include <asm/eeh.h> |
26 | #include <asm/eeh_event.h> |
27 | #include <asm/firmware.h> |
28 | #include <asm/io.h> |
29 | #include <asm/iommu.h> |
30 | #include <asm/machdep.h> |
31 | #include <asm/msi_bitmap.h> |
32 | #include <asm/opal.h> |
33 | #include <asm/ppc-pci.h> |
34 | #include <asm/pnv-pci.h> |
35 | |
36 | #include "powernv.h" |
37 | #include "pci.h" |
38 | #include "../../../../drivers/pci/pci.h" |
39 | |
40 | static int eeh_event_irq = -EINVAL; |
41 | |
42 | static void pnv_pcibios_bus_add_device(struct pci_dev *pdev) |
43 | { |
44 | dev_dbg(&pdev->dev, "EEH: Setting up device\n" ); |
45 | eeh_probe_device(pdev); |
46 | } |
47 | |
48 | static irqreturn_t pnv_eeh_event(int irq, void *data) |
49 | { |
50 | /* |
51 | * We simply send a special EEH event if EEH has been |
52 | * enabled. We don't care about EEH events until we've |
53 | * finished processing the outstanding ones. Event processing |
54 | * gets unmasked in next_error() if EEH is enabled. |
55 | */ |
56 | disable_irq_nosync(irq); |
57 | |
58 | if (eeh_enabled()) |
59 | eeh_send_failure_event(NULL); |
60 | |
61 | return IRQ_HANDLED; |
62 | } |
63 | |
64 | #ifdef CONFIG_DEBUG_FS |
65 | static ssize_t pnv_eeh_ei_write(struct file *filp, |
66 | const char __user *user_buf, |
67 | size_t count, loff_t *ppos) |
68 | { |
69 | struct pci_controller *hose = filp->private_data; |
70 | struct eeh_pe *pe; |
71 | int pe_no, type, func; |
72 | unsigned long addr, mask; |
73 | char buf[50]; |
74 | int ret; |
75 | |
76 | if (!eeh_ops || !eeh_ops->err_inject) |
77 | return -ENXIO; |
78 | |
79 | /* Copy over argument buffer */ |
80 | ret = simple_write_to_buffer(to: buf, available: sizeof(buf), ppos, from: user_buf, count); |
81 | if (!ret) |
82 | return -EFAULT; |
83 | |
84 | /* Retrieve parameters */ |
85 | ret = sscanf(buf, "%x:%x:%x:%lx:%lx" , |
86 | &pe_no, &type, &func, &addr, &mask); |
87 | if (ret != 5) |
88 | return -EINVAL; |
89 | |
90 | /* Retrieve PE */ |
91 | pe = eeh_pe_get(hose, pe_no); |
92 | if (!pe) |
93 | return -ENODEV; |
94 | |
95 | /* Do error injection */ |
96 | ret = eeh_ops->err_inject(pe, type, func, addr, mask); |
97 | return ret < 0 ? ret : count; |
98 | } |
99 | |
100 | static const struct file_operations pnv_eeh_ei_fops = { |
101 | .open = simple_open, |
102 | .llseek = no_llseek, |
103 | .write = pnv_eeh_ei_write, |
104 | }; |
105 | |
106 | static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) |
107 | { |
108 | struct pci_controller *hose = data; |
109 | struct pnv_phb *phb = hose->private_data; |
110 | |
111 | out_be64(phb->regs + offset, val); |
112 | return 0; |
113 | } |
114 | |
115 | static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) |
116 | { |
117 | struct pci_controller *hose = data; |
118 | struct pnv_phb *phb = hose->private_data; |
119 | |
120 | *val = in_be64(phb->regs + offset); |
121 | return 0; |
122 | } |
123 | |
124 | #define PNV_EEH_DBGFS_ENTRY(name, reg) \ |
125 | static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ |
126 | { \ |
127 | return pnv_eeh_dbgfs_set(data, reg, val); \ |
128 | } \ |
129 | \ |
130 | static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ |
131 | { \ |
132 | return pnv_eeh_dbgfs_get(data, reg, val); \ |
133 | } \ |
134 | \ |
135 | DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ |
136 | pnv_eeh_dbgfs_get_##name, \ |
137 | pnv_eeh_dbgfs_set_##name, \ |
138 | "0x%llx\n") |
139 | |
140 | PNV_EEH_DBGFS_ENTRY(outb, 0xD10); |
141 | PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); |
142 | PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); |
143 | |
144 | #endif /* CONFIG_DEBUG_FS */ |
145 | |
146 | static void pnv_eeh_enable_phbs(void) |
147 | { |
148 | struct pci_controller *hose; |
149 | struct pnv_phb *phb; |
150 | |
151 | list_for_each_entry(hose, &hose_list, list_node) { |
152 | phb = hose->private_data; |
153 | /* |
154 | * If EEH is enabled, we're going to rely on that. |
155 | * Otherwise, we restore to conventional mechanism |
156 | * to clear frozen PE during PCI config access. |
157 | */ |
158 | if (eeh_enabled()) |
159 | phb->flags |= PNV_PHB_FLAG_EEH; |
160 | else |
161 | phb->flags &= ~PNV_PHB_FLAG_EEH; |
162 | } |
163 | } |
164 | |
165 | /** |
166 | * pnv_eeh_post_init - EEH platform dependent post initialization |
167 | * |
168 | * EEH platform dependent post initialization on powernv. When |
169 | * the function is called, the EEH PEs and devices should have |
170 | * been built. If the I/O cache staff has been built, EEH is |
171 | * ready to supply service. |
172 | */ |
173 | int pnv_eeh_post_init(void) |
174 | { |
175 | struct pci_controller *hose; |
176 | struct pnv_phb *phb; |
177 | int ret = 0; |
178 | |
179 | eeh_show_enabled(); |
180 | |
181 | /* Register OPAL event notifier */ |
182 | eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); |
183 | if (eeh_event_irq < 0) { |
184 | pr_err("%s: Can't register OPAL event interrupt (%d)\n" , |
185 | __func__, eeh_event_irq); |
186 | return eeh_event_irq; |
187 | } |
188 | |
189 | ret = request_irq(irq: eeh_event_irq, handler: pnv_eeh_event, |
190 | flags: IRQ_TYPE_LEVEL_HIGH, name: "opal-eeh" , NULL); |
191 | if (ret < 0) { |
192 | irq_dispose_mapping(virq: eeh_event_irq); |
193 | pr_err("%s: Can't request OPAL event interrupt (%d)\n" , |
194 | __func__, eeh_event_irq); |
195 | return ret; |
196 | } |
197 | |
198 | if (!eeh_enabled()) |
199 | disable_irq(irq: eeh_event_irq); |
200 | |
201 | pnv_eeh_enable_phbs(); |
202 | |
203 | list_for_each_entry(hose, &hose_list, list_node) { |
204 | phb = hose->private_data; |
205 | |
206 | /* Create debugfs entries */ |
207 | #ifdef CONFIG_DEBUG_FS |
208 | if (phb->has_dbgfs || !phb->dbgfs) |
209 | continue; |
210 | |
211 | phb->has_dbgfs = 1; |
212 | debugfs_create_file("err_injct" , 0200, |
213 | phb->dbgfs, hose, |
214 | &pnv_eeh_ei_fops); |
215 | |
216 | debugfs_create_file("err_injct_outbound" , 0600, |
217 | phb->dbgfs, hose, |
218 | &pnv_eeh_dbgfs_ops_outb); |
219 | debugfs_create_file("err_injct_inboundA" , 0600, |
220 | phb->dbgfs, hose, |
221 | &pnv_eeh_dbgfs_ops_inbA); |
222 | debugfs_create_file("err_injct_inboundB" , 0600, |
223 | phb->dbgfs, hose, |
224 | &pnv_eeh_dbgfs_ops_inbB); |
225 | #endif /* CONFIG_DEBUG_FS */ |
226 | } |
227 | |
228 | return ret; |
229 | } |
230 | |
231 | static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) |
232 | { |
233 | int pos = PCI_CAPABILITY_LIST; |
234 | int cnt = 48; /* Maximal number of capabilities */ |
235 | u32 status, id; |
236 | |
237 | if (!pdn) |
238 | return 0; |
239 | |
240 | /* Check if the device supports capabilities */ |
241 | pnv_pci_cfg_read(pdn, PCI_STATUS, size: 2, val: &status); |
242 | if (!(status & PCI_STATUS_CAP_LIST)) |
243 | return 0; |
244 | |
245 | while (cnt--) { |
246 | pnv_pci_cfg_read(pdn, where: pos, size: 1, val: &pos); |
247 | if (pos < 0x40) |
248 | break; |
249 | |
250 | pos &= ~3; |
251 | pnv_pci_cfg_read(pdn, where: pos + PCI_CAP_LIST_ID, size: 1, val: &id); |
252 | if (id == 0xff) |
253 | break; |
254 | |
255 | /* Found */ |
256 | if (id == cap) |
257 | return pos; |
258 | |
259 | /* Next one */ |
260 | pos += PCI_CAP_LIST_NEXT; |
261 | } |
262 | |
263 | return 0; |
264 | } |
265 | |
266 | static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) |
267 | { |
268 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
269 | u32 ; |
270 | int pos = 256, ttl = (4096 - 256) / 8; |
271 | |
272 | if (!edev || !edev->pcie_cap) |
273 | return 0; |
274 | if (pnv_pci_cfg_read(pdn, where: pos, size: 4, val: &header) != PCIBIOS_SUCCESSFUL) |
275 | return 0; |
276 | else if (!header) |
277 | return 0; |
278 | |
279 | while (ttl-- > 0) { |
280 | if (PCI_EXT_CAP_ID(header) == cap && pos) |
281 | return pos; |
282 | |
283 | pos = PCI_EXT_CAP_NEXT(header); |
284 | if (pos < 256) |
285 | break; |
286 | |
287 | if (pnv_pci_cfg_read(pdn, where: pos, size: 4, val: &header) != PCIBIOS_SUCCESSFUL) |
288 | break; |
289 | } |
290 | |
291 | return 0; |
292 | } |
293 | |
294 | static struct eeh_pe *pnv_eeh_get_upstream_pe(struct pci_dev *pdev) |
295 | { |
296 | struct pci_controller *hose = pdev->bus->sysdata; |
297 | struct pnv_phb *phb = hose->private_data; |
298 | struct pci_dev *parent = pdev->bus->self; |
299 | |
300 | #ifdef CONFIG_PCI_IOV |
301 | /* for VFs we use the PF's PE as the upstream PE */ |
302 | if (pdev->is_virtfn) |
303 | parent = pdev->physfn; |
304 | #endif |
305 | |
306 | /* otherwise use the PE of our parent bridge */ |
307 | if (parent) { |
308 | struct pnv_ioda_pe *ioda_pe = pnv_ioda_get_pe(dev: parent); |
309 | |
310 | return eeh_pe_get(phb->hose, ioda_pe->pe_number); |
311 | } |
312 | |
313 | return NULL; |
314 | } |
315 | |
316 | /** |
317 | * pnv_eeh_probe - Do probe on PCI device |
318 | * @pdev: pci_dev to probe |
319 | * |
320 | * Create, or find the existing, eeh_dev for this pci_dev. |
321 | */ |
322 | static struct eeh_dev *pnv_eeh_probe(struct pci_dev *pdev) |
323 | { |
324 | struct pci_dn *pdn = pci_get_pdn(pdev); |
325 | struct pci_controller *hose = pdn->phb; |
326 | struct pnv_phb *phb = hose->private_data; |
327 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
328 | struct eeh_pe *upstream_pe; |
329 | uint32_t pcie_flags; |
330 | int ret; |
331 | int config_addr = (pdn->busno << 8) | (pdn->devfn); |
332 | |
333 | /* |
334 | * When probing the root bridge, which doesn't have any |
335 | * subordinate PCI devices. We don't have OF node for |
336 | * the root bridge. So it's not reasonable to continue |
337 | * the probing. |
338 | */ |
339 | if (!edev || edev->pe) |
340 | return NULL; |
341 | |
342 | /* already configured? */ |
343 | if (edev->pdev) { |
344 | pr_debug("%s: found existing edev for %04x:%02x:%02x.%01x\n" , |
345 | __func__, hose->global_number, config_addr >> 8, |
346 | PCI_SLOT(config_addr), PCI_FUNC(config_addr)); |
347 | return edev; |
348 | } |
349 | |
350 | /* Skip for PCI-ISA bridge */ |
351 | if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) |
352 | return NULL; |
353 | |
354 | eeh_edev_dbg(edev, "Probing device\n" ); |
355 | |
356 | /* Initialize eeh device */ |
357 | edev->mode &= 0xFFFFFF00; |
358 | edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); |
359 | edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); |
360 | edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); |
361 | edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); |
362 | if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { |
363 | edev->mode |= EEH_DEV_BRIDGE; |
364 | if (edev->pcie_cap) { |
365 | pnv_pci_cfg_read(pdn, where: edev->pcie_cap + PCI_EXP_FLAGS, |
366 | size: 2, val: &pcie_flags); |
367 | pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; |
368 | if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) |
369 | edev->mode |= EEH_DEV_ROOT_PORT; |
370 | else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) |
371 | edev->mode |= EEH_DEV_DS_PORT; |
372 | } |
373 | } |
374 | |
375 | edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; |
376 | |
377 | upstream_pe = pnv_eeh_get_upstream_pe(pdev); |
378 | |
379 | /* Create PE */ |
380 | ret = eeh_pe_tree_insert(edev, upstream_pe); |
381 | if (ret) { |
382 | eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n" , ret); |
383 | return NULL; |
384 | } |
385 | |
386 | /* |
387 | * If the PE contains any one of following adapters, the |
388 | * PCI config space can't be accessed when dumping EEH log. |
389 | * Otherwise, we will run into fenced PHB caused by shortage |
390 | * of outbound credits in the adapter. The PCI config access |
391 | * should be blocked until PE reset. MMIO access is dropped |
392 | * by hardware certainly. In order to drop PCI config requests, |
393 | * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which |
394 | * will be checked in the backend for PE state retrieval. If |
395 | * the PE becomes frozen for the first time and the flag has |
396 | * been set for the PE, we will set EEH_PE_CFG_BLOCKED for |
397 | * that PE to block its config space. |
398 | * |
399 | * Broadcom BCM5718 2-ports NICs (14e4:1656) |
400 | * Broadcom Austin 4-ports NICs (14e4:1657) |
401 | * Broadcom Shiner 4-ports 1G NICs (14e4:168a) |
402 | * Broadcom Shiner 2-ports 10G NICs (14e4:168e) |
403 | */ |
404 | if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && |
405 | pdn->device_id == 0x1656) || |
406 | (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && |
407 | pdn->device_id == 0x1657) || |
408 | (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && |
409 | pdn->device_id == 0x168a) || |
410 | (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && |
411 | pdn->device_id == 0x168e)) |
412 | edev->pe->state |= EEH_PE_CFG_RESTRICTED; |
413 | |
414 | /* |
415 | * Cache the PE primary bus, which can't be fetched when |
416 | * full hotplug is in progress. In that case, all child |
417 | * PCI devices of the PE are expected to be removed prior |
418 | * to PE reset. |
419 | */ |
420 | if (!(edev->pe->state & EEH_PE_PRI_BUS)) { |
421 | edev->pe->bus = pci_find_bus(domain: hose->global_number, |
422 | busnr: pdn->busno); |
423 | if (edev->pe->bus) |
424 | edev->pe->state |= EEH_PE_PRI_BUS; |
425 | } |
426 | |
427 | /* |
428 | * Enable EEH explicitly so that we will do EEH check |
429 | * while accessing I/O stuff |
430 | */ |
431 | if (!eeh_has_flag(EEH_ENABLED)) { |
432 | enable_irq(irq: eeh_event_irq); |
433 | pnv_eeh_enable_phbs(); |
434 | eeh_add_flag(EEH_ENABLED); |
435 | } |
436 | |
437 | /* Save memory bars */ |
438 | eeh_save_bars(edev); |
439 | |
440 | eeh_edev_dbg(edev, "EEH enabled on device\n" ); |
441 | |
442 | return edev; |
443 | } |
444 | |
445 | /** |
446 | * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable |
447 | * @pe: EEH PE |
448 | * @option: operation to be issued |
449 | * |
450 | * The function is used to control the EEH functionality globally. |
451 | * Currently, following options are support according to PAPR: |
452 | * Enable EEH, Disable EEH, Enable MMIO and Enable DMA |
453 | */ |
454 | static int pnv_eeh_set_option(struct eeh_pe *pe, int option) |
455 | { |
456 | struct pci_controller *hose = pe->phb; |
457 | struct pnv_phb *phb = hose->private_data; |
458 | bool freeze_pe = false; |
459 | int opt; |
460 | s64 rc; |
461 | |
462 | switch (option) { |
463 | case EEH_OPT_DISABLE: |
464 | return -EPERM; |
465 | case EEH_OPT_ENABLE: |
466 | return 0; |
467 | case EEH_OPT_THAW_MMIO: |
468 | opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; |
469 | break; |
470 | case EEH_OPT_THAW_DMA: |
471 | opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; |
472 | break; |
473 | case EEH_OPT_FREEZE_PE: |
474 | freeze_pe = true; |
475 | opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; |
476 | break; |
477 | default: |
478 | pr_warn("%s: Invalid option %d\n" , __func__, option); |
479 | return -EINVAL; |
480 | } |
481 | |
482 | /* Freeze master and slave PEs if PHB supports compound PEs */ |
483 | if (freeze_pe) { |
484 | if (phb->freeze_pe) { |
485 | phb->freeze_pe(phb, pe->addr); |
486 | return 0; |
487 | } |
488 | |
489 | rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); |
490 | if (rc != OPAL_SUCCESS) { |
491 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n" , |
492 | __func__, rc, phb->hose->global_number, |
493 | pe->addr); |
494 | return -EIO; |
495 | } |
496 | |
497 | return 0; |
498 | } |
499 | |
500 | /* Unfreeze master and slave PEs if PHB supports */ |
501 | if (phb->unfreeze_pe) |
502 | return phb->unfreeze_pe(phb, pe->addr, opt); |
503 | |
504 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); |
505 | if (rc != OPAL_SUCCESS) { |
506 | pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n" , |
507 | __func__, rc, option, phb->hose->global_number, |
508 | pe->addr); |
509 | return -EIO; |
510 | } |
511 | |
512 | return 0; |
513 | } |
514 | |
515 | static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) |
516 | { |
517 | struct pnv_phb *phb = pe->phb->private_data; |
518 | s64 rc; |
519 | |
520 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, |
521 | phb->diag_data_size); |
522 | if (rc != OPAL_SUCCESS) |
523 | pr_warn("%s: Failure %lld getting PHB#%x diag-data\n" , |
524 | __func__, rc, pe->phb->global_number); |
525 | } |
526 | |
527 | static int pnv_eeh_get_phb_state(struct eeh_pe *pe) |
528 | { |
529 | struct pnv_phb *phb = pe->phb->private_data; |
530 | u8 fstate = 0; |
531 | __be16 pcierr = 0; |
532 | s64 rc; |
533 | int result = 0; |
534 | |
535 | rc = opal_pci_eeh_freeze_status(phb->opal_id, |
536 | pe->addr, |
537 | &fstate, |
538 | &pcierr, |
539 | NULL); |
540 | if (rc != OPAL_SUCCESS) { |
541 | pr_warn("%s: Failure %lld getting PHB#%x state\n" , |
542 | __func__, rc, phb->hose->global_number); |
543 | return EEH_STATE_NOT_SUPPORT; |
544 | } |
545 | |
546 | /* |
547 | * Check PHB state. If the PHB is frozen for the |
548 | * first time, to dump the PHB diag-data. |
549 | */ |
550 | if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { |
551 | result = (EEH_STATE_MMIO_ACTIVE | |
552 | EEH_STATE_DMA_ACTIVE | |
553 | EEH_STATE_MMIO_ENABLED | |
554 | EEH_STATE_DMA_ENABLED); |
555 | } else if (!(pe->state & EEH_PE_ISOLATED)) { |
556 | eeh_pe_mark_isolated(pe); |
557 | pnv_eeh_get_phb_diag(pe); |
558 | |
559 | if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) |
560 | pnv_pci_dump_phb_diag_data(hose: pe->phb, log_buff: pe->data); |
561 | } |
562 | |
563 | return result; |
564 | } |
565 | |
566 | static int pnv_eeh_get_pe_state(struct eeh_pe *pe) |
567 | { |
568 | struct pnv_phb *phb = pe->phb->private_data; |
569 | u8 fstate = 0; |
570 | __be16 pcierr = 0; |
571 | s64 rc; |
572 | int result; |
573 | |
574 | /* |
575 | * We don't clobber hardware frozen state until PE |
576 | * reset is completed. In order to keep EEH core |
577 | * moving forward, we have to return operational |
578 | * state during PE reset. |
579 | */ |
580 | if (pe->state & EEH_PE_RESET) { |
581 | result = (EEH_STATE_MMIO_ACTIVE | |
582 | EEH_STATE_DMA_ACTIVE | |
583 | EEH_STATE_MMIO_ENABLED | |
584 | EEH_STATE_DMA_ENABLED); |
585 | return result; |
586 | } |
587 | |
588 | /* |
589 | * Fetch PE state from hardware. If the PHB |
590 | * supports compound PE, let it handle that. |
591 | */ |
592 | if (phb->get_pe_state) { |
593 | fstate = phb->get_pe_state(phb, pe->addr); |
594 | } else { |
595 | rc = opal_pci_eeh_freeze_status(phb->opal_id, |
596 | pe->addr, |
597 | &fstate, |
598 | &pcierr, |
599 | NULL); |
600 | if (rc != OPAL_SUCCESS) { |
601 | pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n" , |
602 | __func__, rc, phb->hose->global_number, |
603 | pe->addr); |
604 | return EEH_STATE_NOT_SUPPORT; |
605 | } |
606 | } |
607 | |
608 | /* Figure out state */ |
609 | switch (fstate) { |
610 | case OPAL_EEH_STOPPED_NOT_FROZEN: |
611 | result = (EEH_STATE_MMIO_ACTIVE | |
612 | EEH_STATE_DMA_ACTIVE | |
613 | EEH_STATE_MMIO_ENABLED | |
614 | EEH_STATE_DMA_ENABLED); |
615 | break; |
616 | case OPAL_EEH_STOPPED_MMIO_FREEZE: |
617 | result = (EEH_STATE_DMA_ACTIVE | |
618 | EEH_STATE_DMA_ENABLED); |
619 | break; |
620 | case OPAL_EEH_STOPPED_DMA_FREEZE: |
621 | result = (EEH_STATE_MMIO_ACTIVE | |
622 | EEH_STATE_MMIO_ENABLED); |
623 | break; |
624 | case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: |
625 | result = 0; |
626 | break; |
627 | case OPAL_EEH_STOPPED_RESET: |
628 | result = EEH_STATE_RESET_ACTIVE; |
629 | break; |
630 | case OPAL_EEH_STOPPED_TEMP_UNAVAIL: |
631 | result = EEH_STATE_UNAVAILABLE; |
632 | break; |
633 | case OPAL_EEH_STOPPED_PERM_UNAVAIL: |
634 | result = EEH_STATE_NOT_SUPPORT; |
635 | break; |
636 | default: |
637 | result = EEH_STATE_NOT_SUPPORT; |
638 | pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n" , |
639 | __func__, phb->hose->global_number, |
640 | pe->addr, fstate); |
641 | } |
642 | |
643 | /* |
644 | * If PHB supports compound PE, to freeze all |
645 | * slave PEs for consistency. |
646 | * |
647 | * If the PE is switching to frozen state for the |
648 | * first time, to dump the PHB diag-data. |
649 | */ |
650 | if (!(result & EEH_STATE_NOT_SUPPORT) && |
651 | !(result & EEH_STATE_UNAVAILABLE) && |
652 | !(result & EEH_STATE_MMIO_ACTIVE) && |
653 | !(result & EEH_STATE_DMA_ACTIVE) && |
654 | !(pe->state & EEH_PE_ISOLATED)) { |
655 | if (phb->freeze_pe) |
656 | phb->freeze_pe(phb, pe->addr); |
657 | |
658 | eeh_pe_mark_isolated(pe); |
659 | pnv_eeh_get_phb_diag(pe); |
660 | |
661 | if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) |
662 | pnv_pci_dump_phb_diag_data(hose: pe->phb, log_buff: pe->data); |
663 | } |
664 | |
665 | return result; |
666 | } |
667 | |
668 | /** |
669 | * pnv_eeh_get_state - Retrieve PE state |
670 | * @pe: EEH PE |
671 | * @delay: delay while PE state is temporarily unavailable |
672 | * |
673 | * Retrieve the state of the specified PE. For IODA-compitable |
674 | * platform, it should be retrieved from IODA table. Therefore, |
675 | * we prefer passing down to hardware implementation to handle |
676 | * it. |
677 | */ |
678 | static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) |
679 | { |
680 | int ret; |
681 | |
682 | if (pe->type & EEH_PE_PHB) |
683 | ret = pnv_eeh_get_phb_state(pe); |
684 | else |
685 | ret = pnv_eeh_get_pe_state(pe); |
686 | |
687 | if (!delay) |
688 | return ret; |
689 | |
690 | /* |
691 | * If the PE state is temporarily unavailable, |
692 | * to inform the EEH core delay for default |
693 | * period (1 second) |
694 | */ |
695 | *delay = 0; |
696 | if (ret & EEH_STATE_UNAVAILABLE) |
697 | *delay = 1000; |
698 | |
699 | return ret; |
700 | } |
701 | |
702 | static s64 pnv_eeh_poll(unsigned long id) |
703 | { |
704 | s64 rc = OPAL_HARDWARE; |
705 | |
706 | while (1) { |
707 | rc = opal_pci_poll(id); |
708 | if (rc <= 0) |
709 | break; |
710 | |
711 | if (system_state < SYSTEM_RUNNING) |
712 | udelay(1000 * rc); |
713 | else |
714 | msleep(msecs: rc); |
715 | } |
716 | |
717 | return rc; |
718 | } |
719 | |
720 | int pnv_eeh_phb_reset(struct pci_controller *hose, int option) |
721 | { |
722 | struct pnv_phb *phb = hose->private_data; |
723 | s64 rc = OPAL_HARDWARE; |
724 | |
725 | pr_debug("%s: Reset PHB#%x, option=%d\n" , |
726 | __func__, hose->global_number, option); |
727 | |
728 | /* Issue PHB complete reset request */ |
729 | if (option == EEH_RESET_FUNDAMENTAL || |
730 | option == EEH_RESET_HOT) |
731 | rc = opal_pci_reset(phb->opal_id, |
732 | OPAL_RESET_PHB_COMPLETE, |
733 | OPAL_ASSERT_RESET); |
734 | else if (option == EEH_RESET_DEACTIVATE) |
735 | rc = opal_pci_reset(phb->opal_id, |
736 | OPAL_RESET_PHB_COMPLETE, |
737 | OPAL_DEASSERT_RESET); |
738 | if (rc < 0) |
739 | goto out; |
740 | |
741 | /* |
742 | * Poll state of the PHB until the request is done |
743 | * successfully. The PHB reset is usually PHB complete |
744 | * reset followed by hot reset on root bus. So we also |
745 | * need the PCI bus settlement delay. |
746 | */ |
747 | if (rc > 0) |
748 | rc = pnv_eeh_poll(id: phb->opal_id); |
749 | if (option == EEH_RESET_DEACTIVATE) { |
750 | if (system_state < SYSTEM_RUNNING) |
751 | udelay(1000 * EEH_PE_RST_SETTLE_TIME); |
752 | else |
753 | msleep(EEH_PE_RST_SETTLE_TIME); |
754 | } |
755 | out: |
756 | if (rc != OPAL_SUCCESS) |
757 | return -EIO; |
758 | |
759 | return 0; |
760 | } |
761 | |
762 | static int pnv_eeh_root_reset(struct pci_controller *hose, int option) |
763 | { |
764 | struct pnv_phb *phb = hose->private_data; |
765 | s64 rc = OPAL_HARDWARE; |
766 | |
767 | pr_debug("%s: Reset PHB#%x, option=%d\n" , |
768 | __func__, hose->global_number, option); |
769 | |
770 | /* |
771 | * During the reset deassert time, we needn't care |
772 | * the reset scope because the firmware does nothing |
773 | * for fundamental or hot reset during deassert phase. |
774 | */ |
775 | if (option == EEH_RESET_FUNDAMENTAL) |
776 | rc = opal_pci_reset(phb->opal_id, |
777 | OPAL_RESET_PCI_FUNDAMENTAL, |
778 | OPAL_ASSERT_RESET); |
779 | else if (option == EEH_RESET_HOT) |
780 | rc = opal_pci_reset(phb->opal_id, |
781 | OPAL_RESET_PCI_HOT, |
782 | OPAL_ASSERT_RESET); |
783 | else if (option == EEH_RESET_DEACTIVATE) |
784 | rc = opal_pci_reset(phb->opal_id, |
785 | OPAL_RESET_PCI_HOT, |
786 | OPAL_DEASSERT_RESET); |
787 | if (rc < 0) |
788 | goto out; |
789 | |
790 | /* Poll state of the PHB until the request is done */ |
791 | if (rc > 0) |
792 | rc = pnv_eeh_poll(id: phb->opal_id); |
793 | if (option == EEH_RESET_DEACTIVATE) |
794 | msleep(EEH_PE_RST_SETTLE_TIME); |
795 | out: |
796 | if (rc != OPAL_SUCCESS) |
797 | return -EIO; |
798 | |
799 | return 0; |
800 | } |
801 | |
802 | static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) |
803 | { |
804 | struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); |
805 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
806 | int aer = edev ? edev->aer_cap : 0; |
807 | u32 ctrl; |
808 | |
809 | pr_debug("%s: Secondary Reset PCI bus %04x:%02x with option %d\n" , |
810 | __func__, pci_domain_nr(dev->bus), |
811 | dev->bus->number, option); |
812 | |
813 | switch (option) { |
814 | case EEH_RESET_FUNDAMENTAL: |
815 | case EEH_RESET_HOT: |
816 | /* Don't report linkDown event */ |
817 | if (aer) { |
818 | eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, |
819 | 4, &ctrl); |
820 | ctrl |= PCI_ERR_UNC_SURPDN; |
821 | eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, |
822 | 4, ctrl); |
823 | } |
824 | |
825 | eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); |
826 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; |
827 | eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); |
828 | |
829 | msleep(EEH_PE_RST_HOLD_TIME); |
830 | break; |
831 | case EEH_RESET_DEACTIVATE: |
832 | eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); |
833 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
834 | eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); |
835 | |
836 | msleep(EEH_PE_RST_SETTLE_TIME); |
837 | |
838 | /* Continue reporting linkDown event */ |
839 | if (aer) { |
840 | eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, |
841 | 4, &ctrl); |
842 | ctrl &= ~PCI_ERR_UNC_SURPDN; |
843 | eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, |
844 | 4, ctrl); |
845 | } |
846 | |
847 | break; |
848 | } |
849 | |
850 | return 0; |
851 | } |
852 | |
853 | static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) |
854 | { |
855 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
856 | struct pnv_phb *phb = hose->private_data; |
857 | struct device_node *dn = pci_device_to_OF_node(pdev); |
858 | uint64_t id = PCI_SLOT_ID(phb->opal_id, pci_dev_id(dev: pdev)); |
859 | uint8_t scope; |
860 | int64_t rc; |
861 | |
862 | /* Hot reset to the bus if firmware cannot handle */ |
863 | if (!dn || !of_get_property(node: dn, name: "ibm,reset-by-firmware" , NULL)) |
864 | return __pnv_eeh_bridge_reset(dev: pdev, option); |
865 | |
866 | pr_debug("%s: FW reset PCI bus %04x:%02x with option %d\n" , |
867 | __func__, pci_domain_nr(pdev->bus), |
868 | pdev->bus->number, option); |
869 | |
870 | switch (option) { |
871 | case EEH_RESET_FUNDAMENTAL: |
872 | scope = OPAL_RESET_PCI_FUNDAMENTAL; |
873 | break; |
874 | case EEH_RESET_HOT: |
875 | scope = OPAL_RESET_PCI_HOT; |
876 | break; |
877 | case EEH_RESET_DEACTIVATE: |
878 | return 0; |
879 | default: |
880 | dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n" , |
881 | __func__, option); |
882 | return -EINVAL; |
883 | } |
884 | |
885 | rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); |
886 | if (rc <= OPAL_SUCCESS) |
887 | goto out; |
888 | |
889 | rc = pnv_eeh_poll(id); |
890 | out: |
891 | return (rc == OPAL_SUCCESS) ? 0 : -EIO; |
892 | } |
893 | |
894 | void pnv_pci_reset_secondary_bus(struct pci_dev *dev) |
895 | { |
896 | struct pci_controller *hose; |
897 | |
898 | if (pci_is_root_bus(pbus: dev->bus)) { |
899 | hose = pci_bus_to_host(dev->bus); |
900 | pnv_eeh_root_reset(hose, EEH_RESET_HOT); |
901 | pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); |
902 | } else { |
903 | pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); |
904 | pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); |
905 | } |
906 | } |
907 | |
908 | static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, |
909 | int pos, u16 mask) |
910 | { |
911 | struct eeh_dev *edev = pdn->edev; |
912 | int i, status = 0; |
913 | |
914 | /* Wait for Transaction Pending bit to be cleared */ |
915 | for (i = 0; i < 4; i++) { |
916 | eeh_ops->read_config(edev, pos, 2, &status); |
917 | if (!(status & mask)) |
918 | return; |
919 | |
920 | msleep(msecs: (1 << i) * 100); |
921 | } |
922 | |
923 | pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n" , |
924 | __func__, type, |
925 | pdn->phb->global_number, pdn->busno, |
926 | PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); |
927 | } |
928 | |
929 | static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) |
930 | { |
931 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
932 | u32 reg = 0; |
933 | |
934 | if (WARN_ON(!edev->pcie_cap)) |
935 | return -ENOTTY; |
936 | |
937 | eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); |
938 | if (!(reg & PCI_EXP_DEVCAP_FLR)) |
939 | return -ENOTTY; |
940 | |
941 | switch (option) { |
942 | case EEH_RESET_HOT: |
943 | case EEH_RESET_FUNDAMENTAL: |
944 | pnv_eeh_wait_for_pending(pdn, type: "" , |
945 | pos: edev->pcie_cap + PCI_EXP_DEVSTA, |
946 | PCI_EXP_DEVSTA_TRPND); |
947 | eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, |
948 | 4, ®); |
949 | reg |= PCI_EXP_DEVCTL_BCR_FLR; |
950 | eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, |
951 | 4, reg); |
952 | msleep(EEH_PE_RST_HOLD_TIME); |
953 | break; |
954 | case EEH_RESET_DEACTIVATE: |
955 | eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, |
956 | 4, ®); |
957 | reg &= ~PCI_EXP_DEVCTL_BCR_FLR; |
958 | eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, |
959 | 4, reg); |
960 | msleep(EEH_PE_RST_SETTLE_TIME); |
961 | break; |
962 | } |
963 | |
964 | return 0; |
965 | } |
966 | |
967 | static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) |
968 | { |
969 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
970 | u32 cap = 0; |
971 | |
972 | if (WARN_ON(!edev->af_cap)) |
973 | return -ENOTTY; |
974 | |
975 | eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap); |
976 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
977 | return -ENOTTY; |
978 | |
979 | switch (option) { |
980 | case EEH_RESET_HOT: |
981 | case EEH_RESET_FUNDAMENTAL: |
982 | /* |
983 | * Wait for Transaction Pending bit to clear. A word-aligned |
984 | * test is used, so we use the control offset rather than status |
985 | * and shift the test bit to match. |
986 | */ |
987 | pnv_eeh_wait_for_pending(pdn, type: "AF" , |
988 | pos: edev->af_cap + PCI_AF_CTRL, |
989 | PCI_AF_STATUS_TP << 8); |
990 | eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, |
991 | 1, PCI_AF_CTRL_FLR); |
992 | msleep(EEH_PE_RST_HOLD_TIME); |
993 | break; |
994 | case EEH_RESET_DEACTIVATE: |
995 | eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0); |
996 | msleep(EEH_PE_RST_SETTLE_TIME); |
997 | break; |
998 | } |
999 | |
1000 | return 0; |
1001 | } |
1002 | |
1003 | static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) |
1004 | { |
1005 | struct eeh_dev *edev; |
1006 | struct pci_dn *pdn; |
1007 | int ret; |
1008 | |
1009 | /* The VF PE should have only one child device */ |
1010 | edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); |
1011 | pdn = eeh_dev_to_pdn(edev); |
1012 | if (!pdn) |
1013 | return -ENXIO; |
1014 | |
1015 | ret = pnv_eeh_do_flr(pdn, option); |
1016 | if (!ret) |
1017 | return ret; |
1018 | |
1019 | return pnv_eeh_do_af_flr(pdn, option); |
1020 | } |
1021 | |
1022 | /** |
1023 | * pnv_eeh_reset - Reset the specified PE |
1024 | * @pe: EEH PE |
1025 | * @option: reset option |
1026 | * |
1027 | * Do reset on the indicated PE. For PCI bus sensitive PE, |
1028 | * we need to reset the parent p2p bridge. The PHB has to |
1029 | * be reinitialized if the p2p bridge is root bridge. For |
1030 | * PCI device sensitive PE, we will try to reset the device |
1031 | * through FLR. For now, we don't have OPAL APIs to do HARD |
1032 | * reset yet, so all reset would be SOFT (HOT) reset. |
1033 | */ |
1034 | static int pnv_eeh_reset(struct eeh_pe *pe, int option) |
1035 | { |
1036 | struct pci_controller *hose = pe->phb; |
1037 | struct pnv_phb *phb; |
1038 | struct pci_bus *bus; |
1039 | int64_t rc; |
1040 | |
1041 | /* |
1042 | * For PHB reset, we always have complete reset. For those PEs whose |
1043 | * primary bus derived from root complex (root bus) or root port |
1044 | * (usually bus#1), we apply hot or fundamental reset on the root port. |
1045 | * For other PEs, we always have hot reset on the PE primary bus. |
1046 | * |
1047 | * Here, we have different design to pHyp, which always clear the |
1048 | * frozen state during PE reset. However, the good idea here from |
1049 | * benh is to keep frozen state before we get PE reset done completely |
1050 | * (until BAR restore). With the frozen state, HW drops illegal IO |
1051 | * or MMIO access, which can incur recursive frozen PE during PE |
1052 | * reset. The side effect is that EEH core has to clear the frozen |
1053 | * state explicitly after BAR restore. |
1054 | */ |
1055 | if (pe->type & EEH_PE_PHB) |
1056 | return pnv_eeh_phb_reset(hose, option); |
1057 | |
1058 | /* |
1059 | * The frozen PE might be caused by PAPR error injection |
1060 | * registers, which are expected to be cleared after hitting |
1061 | * frozen PE as stated in the hardware spec. Unfortunately, |
1062 | * that's not true on P7IOC. So we have to clear it manually |
1063 | * to avoid recursive EEH errors during recovery. |
1064 | */ |
1065 | phb = hose->private_data; |
1066 | if (phb->model == PNV_PHB_MODEL_P7IOC && |
1067 | (option == EEH_RESET_HOT || |
1068 | option == EEH_RESET_FUNDAMENTAL)) { |
1069 | rc = opal_pci_reset(phb->opal_id, |
1070 | OPAL_RESET_PHB_ERROR, |
1071 | OPAL_ASSERT_RESET); |
1072 | if (rc != OPAL_SUCCESS) { |
1073 | pr_warn("%s: Failure %lld clearing error injection registers\n" , |
1074 | __func__, rc); |
1075 | return -EIO; |
1076 | } |
1077 | } |
1078 | |
1079 | if (pe->type & EEH_PE_VF) |
1080 | return pnv_eeh_reset_vf_pe(pe, option); |
1081 | |
1082 | bus = eeh_pe_bus_get(pe); |
1083 | if (!bus) { |
1084 | pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n" , |
1085 | __func__, pe->phb->global_number, pe->addr); |
1086 | return -EIO; |
1087 | } |
1088 | |
1089 | if (pci_is_root_bus(pbus: bus)) |
1090 | return pnv_eeh_root_reset(hose, option); |
1091 | |
1092 | /* |
1093 | * For hot resets try use the generic PCI error recovery reset |
1094 | * functions. These correctly handles the case where the secondary |
1095 | * bus is behind a hotplug slot and it will use the slot provided |
1096 | * reset methods to prevent spurious hotplug events during the reset. |
1097 | * |
1098 | * Fundamental resets need to be handled internally to EEH since the |
1099 | * PCI core doesn't really have a concept of a fundamental reset, |
1100 | * mainly because there's no standard way to generate one. Only a |
1101 | * few devices require an FRESET so it should be fine. |
1102 | */ |
1103 | if (option != EEH_RESET_FUNDAMENTAL) { |
1104 | /* |
1105 | * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the |
1106 | * de-assert step. It's like the OPAL reset API was |
1107 | * poorly designed or something... |
1108 | */ |
1109 | if (option == EEH_RESET_DEACTIVATE) |
1110 | return 0; |
1111 | |
1112 | rc = pci_bus_error_reset(dev: bus->self); |
1113 | if (!rc) |
1114 | return 0; |
1115 | } |
1116 | |
1117 | /* otherwise, use the generic bridge reset. this might call into FW */ |
1118 | if (pci_is_root_bus(pbus: bus->parent)) |
1119 | return pnv_eeh_root_reset(hose, option); |
1120 | return pnv_eeh_bridge_reset(pdev: bus->self, option); |
1121 | } |
1122 | |
1123 | /** |
1124 | * pnv_eeh_get_log - Retrieve error log |
1125 | * @pe: EEH PE |
1126 | * @severity: temporary or permanent error log |
1127 | * @drv_log: driver log to be combined with retrieved error log |
1128 | * @len: length of driver log |
1129 | * |
1130 | * Retrieve the temporary or permanent error from the PE. |
1131 | */ |
1132 | static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, |
1133 | char *drv_log, unsigned long len) |
1134 | { |
1135 | if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) |
1136 | pnv_pci_dump_phb_diag_data(hose: pe->phb, log_buff: pe->data); |
1137 | |
1138 | return 0; |
1139 | } |
1140 | |
1141 | /** |
1142 | * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE |
1143 | * @pe: EEH PE |
1144 | * |
1145 | * The function will be called to reconfigure the bridges included |
1146 | * in the specified PE so that the mulfunctional PE would be recovered |
1147 | * again. |
1148 | */ |
1149 | static int pnv_eeh_configure_bridge(struct eeh_pe *pe) |
1150 | { |
1151 | return 0; |
1152 | } |
1153 | |
1154 | /** |
1155 | * pnv_pe_err_inject - Inject specified error to the indicated PE |
1156 | * @pe: the indicated PE |
1157 | * @type: error type |
1158 | * @func: specific error type |
1159 | * @addr: address |
1160 | * @mask: address mask |
1161 | * |
1162 | * The routine is called to inject specified error, which is |
1163 | * determined by @type and @func, to the indicated PE for |
1164 | * testing purpose. |
1165 | */ |
1166 | static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, |
1167 | unsigned long addr, unsigned long mask) |
1168 | { |
1169 | struct pci_controller *hose = pe->phb; |
1170 | struct pnv_phb *phb = hose->private_data; |
1171 | s64 rc; |
1172 | |
1173 | if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && |
1174 | type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { |
1175 | pr_warn("%s: Invalid error type %d\n" , |
1176 | __func__, type); |
1177 | return -ERANGE; |
1178 | } |
1179 | |
1180 | if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || |
1181 | func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { |
1182 | pr_warn("%s: Invalid error function %d\n" , |
1183 | __func__, func); |
1184 | return -ERANGE; |
1185 | } |
1186 | |
1187 | /* Firmware supports error injection ? */ |
1188 | if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { |
1189 | pr_warn("%s: Firmware doesn't support error injection\n" , |
1190 | __func__); |
1191 | return -ENXIO; |
1192 | } |
1193 | |
1194 | /* Do error injection */ |
1195 | rc = opal_pci_err_inject(phb->opal_id, pe->addr, |
1196 | type, func, addr, mask); |
1197 | if (rc != OPAL_SUCCESS) { |
1198 | pr_warn("%s: Failure %lld injecting error " |
1199 | "%d-%d to PHB#%x-PE#%x\n" , |
1200 | __func__, rc, type, func, |
1201 | hose->global_number, pe->addr); |
1202 | return -EIO; |
1203 | } |
1204 | |
1205 | return 0; |
1206 | } |
1207 | |
1208 | static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) |
1209 | { |
1210 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
1211 | |
1212 | if (!edev || !edev->pe) |
1213 | return false; |
1214 | |
1215 | /* |
1216 | * We will issue FLR or AF FLR to all VFs, which are contained |
1217 | * in VF PE. It relies on the EEH PCI config accessors. So we |
1218 | * can't block them during the window. |
1219 | */ |
1220 | if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) |
1221 | return false; |
1222 | |
1223 | if (edev->pe->state & EEH_PE_CFG_BLOCKED) |
1224 | return true; |
1225 | |
1226 | return false; |
1227 | } |
1228 | |
1229 | static int pnv_eeh_read_config(struct eeh_dev *edev, |
1230 | int where, int size, u32 *val) |
1231 | { |
1232 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
1233 | |
1234 | if (!pdn) |
1235 | return PCIBIOS_DEVICE_NOT_FOUND; |
1236 | |
1237 | if (pnv_eeh_cfg_blocked(pdn)) { |
1238 | *val = 0xFFFFFFFF; |
1239 | return PCIBIOS_SET_FAILED; |
1240 | } |
1241 | |
1242 | return pnv_pci_cfg_read(pdn, where, size, val); |
1243 | } |
1244 | |
1245 | static int pnv_eeh_write_config(struct eeh_dev *edev, |
1246 | int where, int size, u32 val) |
1247 | { |
1248 | struct pci_dn *pdn = eeh_dev_to_pdn(edev); |
1249 | |
1250 | if (!pdn) |
1251 | return PCIBIOS_DEVICE_NOT_FOUND; |
1252 | |
1253 | if (pnv_eeh_cfg_blocked(pdn)) |
1254 | return PCIBIOS_SET_FAILED; |
1255 | |
1256 | return pnv_pci_cfg_write(pdn, where, size, val); |
1257 | } |
1258 | |
1259 | static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) |
1260 | { |
1261 | /* GEM */ |
1262 | if (data->gemXfir || data->gemRfir || |
1263 | data->gemRirqfir || data->gemMask || data->gemRwof) |
1264 | pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n" , |
1265 | be64_to_cpu(data->gemXfir), |
1266 | be64_to_cpu(data->gemRfir), |
1267 | be64_to_cpu(data->gemRirqfir), |
1268 | be64_to_cpu(data->gemMask), |
1269 | be64_to_cpu(data->gemRwof)); |
1270 | |
1271 | /* LEM */ |
1272 | if (data->lemFir || data->lemErrMask || |
1273 | data->lemAction0 || data->lemAction1 || data->lemWof) |
1274 | pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n" , |
1275 | be64_to_cpu(data->lemFir), |
1276 | be64_to_cpu(data->lemErrMask), |
1277 | be64_to_cpu(data->lemAction0), |
1278 | be64_to_cpu(data->lemAction1), |
1279 | be64_to_cpu(data->lemWof)); |
1280 | } |
1281 | |
1282 | static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) |
1283 | { |
1284 | struct pnv_phb *phb = hose->private_data; |
1285 | struct OpalIoP7IOCErrorData *data = |
1286 | (struct OpalIoP7IOCErrorData*)phb->diag_data; |
1287 | long rc; |
1288 | |
1289 | rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); |
1290 | if (rc != OPAL_SUCCESS) { |
1291 | pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n" , |
1292 | __func__, phb->hub_id, rc); |
1293 | return; |
1294 | } |
1295 | |
1296 | switch (be16_to_cpu(data->type)) { |
1297 | case OPAL_P7IOC_DIAG_TYPE_RGC: |
1298 | pr_info("P7IOC diag-data for RGC\n\n" ); |
1299 | pnv_eeh_dump_hub_diag_common(data); |
1300 | if (data->rgc.rgcStatus || data->rgc.rgcLdcp) |
1301 | pr_info(" RGC: %016llx %016llx\n" , |
1302 | be64_to_cpu(data->rgc.rgcStatus), |
1303 | be64_to_cpu(data->rgc.rgcLdcp)); |
1304 | break; |
1305 | case OPAL_P7IOC_DIAG_TYPE_BI: |
1306 | pr_info("P7IOC diag-data for BI %s\n\n" , |
1307 | data->bi.biDownbound ? "Downbound" : "Upbound" ); |
1308 | pnv_eeh_dump_hub_diag_common(data); |
1309 | if (data->bi.biLdcp0 || data->bi.biLdcp1 || |
1310 | data->bi.biLdcp2 || data->bi.biFenceStatus) |
1311 | pr_info(" BI: %016llx %016llx %016llx %016llx\n" , |
1312 | be64_to_cpu(data->bi.biLdcp0), |
1313 | be64_to_cpu(data->bi.biLdcp1), |
1314 | be64_to_cpu(data->bi.biLdcp2), |
1315 | be64_to_cpu(data->bi.biFenceStatus)); |
1316 | break; |
1317 | case OPAL_P7IOC_DIAG_TYPE_CI: |
1318 | pr_info("P7IOC diag-data for CI Port %d\n\n" , |
1319 | data->ci.ciPort); |
1320 | pnv_eeh_dump_hub_diag_common(data); |
1321 | if (data->ci.ciPortStatus || data->ci.ciPortLdcp) |
1322 | pr_info(" CI: %016llx %016llx\n" , |
1323 | be64_to_cpu(data->ci.ciPortStatus), |
1324 | be64_to_cpu(data->ci.ciPortLdcp)); |
1325 | break; |
1326 | case OPAL_P7IOC_DIAG_TYPE_MISC: |
1327 | pr_info("P7IOC diag-data for MISC\n\n" ); |
1328 | pnv_eeh_dump_hub_diag_common(data); |
1329 | break; |
1330 | case OPAL_P7IOC_DIAG_TYPE_I2C: |
1331 | pr_info("P7IOC diag-data for I2C\n\n" ); |
1332 | pnv_eeh_dump_hub_diag_common(data); |
1333 | break; |
1334 | default: |
1335 | pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n" , |
1336 | __func__, phb->hub_id, data->type); |
1337 | } |
1338 | } |
1339 | |
1340 | static int pnv_eeh_get_pe(struct pci_controller *hose, |
1341 | u16 pe_no, struct eeh_pe **pe) |
1342 | { |
1343 | struct pnv_phb *phb = hose->private_data; |
1344 | struct pnv_ioda_pe *pnv_pe; |
1345 | struct eeh_pe *dev_pe; |
1346 | |
1347 | /* |
1348 | * If PHB supports compound PE, to fetch |
1349 | * the master PE because slave PE is invisible |
1350 | * to EEH core. |
1351 | */ |
1352 | pnv_pe = &phb->ioda.pe_array[pe_no]; |
1353 | if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { |
1354 | pnv_pe = pnv_pe->master; |
1355 | WARN_ON(!pnv_pe || |
1356 | !(pnv_pe->flags & PNV_IODA_PE_MASTER)); |
1357 | pe_no = pnv_pe->pe_number; |
1358 | } |
1359 | |
1360 | /* Find the PE according to PE# */ |
1361 | dev_pe = eeh_pe_get(hose, pe_no); |
1362 | if (!dev_pe) |
1363 | return -EEXIST; |
1364 | |
1365 | /* Freeze the (compound) PE */ |
1366 | *pe = dev_pe; |
1367 | if (!(dev_pe->state & EEH_PE_ISOLATED)) |
1368 | phb->freeze_pe(phb, pe_no); |
1369 | |
1370 | /* |
1371 | * At this point, we're sure the (compound) PE should |
1372 | * have been frozen. However, we still need poke until |
1373 | * hitting the frozen PE on top level. |
1374 | */ |
1375 | dev_pe = dev_pe->parent; |
1376 | while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { |
1377 | int ret; |
1378 | ret = eeh_ops->get_state(dev_pe, NULL); |
1379 | if (ret <= 0 || eeh_state_active(ret)) { |
1380 | dev_pe = dev_pe->parent; |
1381 | continue; |
1382 | } |
1383 | |
1384 | /* Frozen parent PE */ |
1385 | *pe = dev_pe; |
1386 | if (!(dev_pe->state & EEH_PE_ISOLATED)) |
1387 | phb->freeze_pe(phb, dev_pe->addr); |
1388 | |
1389 | /* Next one */ |
1390 | dev_pe = dev_pe->parent; |
1391 | } |
1392 | |
1393 | return 0; |
1394 | } |
1395 | |
1396 | /** |
1397 | * pnv_eeh_next_error - Retrieve next EEH error to handle |
1398 | * @pe: Affected PE |
1399 | * |
1400 | * The function is expected to be called by EEH core while it gets |
1401 | * special EEH event (without binding PE). The function calls to |
1402 | * OPAL APIs for next error to handle. The informational error is |
1403 | * handled internally by platform. However, the dead IOC, dead PHB, |
1404 | * fenced PHB and frozen PE should be handled by EEH core eventually. |
1405 | */ |
1406 | static int pnv_eeh_next_error(struct eeh_pe **pe) |
1407 | { |
1408 | struct pci_controller *hose; |
1409 | struct pnv_phb *phb; |
1410 | struct eeh_pe *phb_pe, *parent_pe; |
1411 | __be64 frozen_pe_no; |
1412 | __be16 err_type, severity; |
1413 | long rc; |
1414 | int state, ret = EEH_NEXT_ERR_NONE; |
1415 | |
1416 | /* |
1417 | * While running here, it's safe to purge the event queue. The |
1418 | * event should still be masked. |
1419 | */ |
1420 | eeh_remove_event(NULL, false); |
1421 | |
1422 | list_for_each_entry(hose, &hose_list, list_node) { |
1423 | /* |
1424 | * If the subordinate PCI buses of the PHB has been |
1425 | * removed or is exactly under error recovery, we |
1426 | * needn't take care of it any more. |
1427 | */ |
1428 | phb = hose->private_data; |
1429 | phb_pe = eeh_phb_pe_get(hose); |
1430 | if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) |
1431 | continue; |
1432 | |
1433 | rc = opal_pci_next_error(phb->opal_id, |
1434 | &frozen_pe_no, &err_type, &severity); |
1435 | if (rc != OPAL_SUCCESS) { |
1436 | pr_devel("%s: Invalid return value on " |
1437 | "PHB#%x (0x%lx) from opal_pci_next_error" , |
1438 | __func__, hose->global_number, rc); |
1439 | continue; |
1440 | } |
1441 | |
1442 | /* If the PHB doesn't have error, stop processing */ |
1443 | if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || |
1444 | be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { |
1445 | pr_devel("%s: No error found on PHB#%x\n" , |
1446 | __func__, hose->global_number); |
1447 | continue; |
1448 | } |
1449 | |
1450 | /* |
1451 | * Processing the error. We're expecting the error with |
1452 | * highest priority reported upon multiple errors on the |
1453 | * specific PHB. |
1454 | */ |
1455 | pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n" , |
1456 | __func__, be16_to_cpu(err_type), |
1457 | be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), |
1458 | hose->global_number); |
1459 | switch (be16_to_cpu(err_type)) { |
1460 | case OPAL_EEH_IOC_ERROR: |
1461 | if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { |
1462 | pr_err("EEH: dead IOC detected\n" ); |
1463 | ret = EEH_NEXT_ERR_DEAD_IOC; |
1464 | } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { |
1465 | pr_info("EEH: IOC informative error " |
1466 | "detected\n" ); |
1467 | pnv_eeh_get_and_dump_hub_diag(hose); |
1468 | ret = EEH_NEXT_ERR_NONE; |
1469 | } |
1470 | |
1471 | break; |
1472 | case OPAL_EEH_PHB_ERROR: |
1473 | if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { |
1474 | *pe = phb_pe; |
1475 | pr_err("EEH: dead PHB#%x detected, " |
1476 | "location: %s\n" , |
1477 | hose->global_number, |
1478 | eeh_pe_loc_get(phb_pe)); |
1479 | ret = EEH_NEXT_ERR_DEAD_PHB; |
1480 | } else if (be16_to_cpu(severity) == |
1481 | OPAL_EEH_SEV_PHB_FENCED) { |
1482 | *pe = phb_pe; |
1483 | pr_err("EEH: Fenced PHB#%x detected, " |
1484 | "location: %s\n" , |
1485 | hose->global_number, |
1486 | eeh_pe_loc_get(phb_pe)); |
1487 | ret = EEH_NEXT_ERR_FENCED_PHB; |
1488 | } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { |
1489 | pr_info("EEH: PHB#%x informative error " |
1490 | "detected, location: %s\n" , |
1491 | hose->global_number, |
1492 | eeh_pe_loc_get(phb_pe)); |
1493 | pnv_eeh_get_phb_diag(phb_pe); |
1494 | pnv_pci_dump_phb_diag_data(hose, phb_pe->data); |
1495 | ret = EEH_NEXT_ERR_NONE; |
1496 | } |
1497 | |
1498 | break; |
1499 | case OPAL_EEH_PE_ERROR: |
1500 | /* |
1501 | * If we can't find the corresponding PE, we |
1502 | * just try to unfreeze. |
1503 | */ |
1504 | if (pnv_eeh_get_pe(hose, |
1505 | be64_to_cpu(frozen_pe_no), pe)) { |
1506 | pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n" , |
1507 | hose->global_number, be64_to_cpu(frozen_pe_no)); |
1508 | pr_info("EEH: PHB location: %s\n" , |
1509 | eeh_pe_loc_get(phb_pe)); |
1510 | |
1511 | /* Dump PHB diag-data */ |
1512 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, |
1513 | phb->diag_data, phb->diag_data_size); |
1514 | if (rc == OPAL_SUCCESS) |
1515 | pnv_pci_dump_phb_diag_data(hose, |
1516 | phb->diag_data); |
1517 | |
1518 | /* Try best to clear it */ |
1519 | opal_pci_eeh_freeze_clear(phb->opal_id, |
1520 | be64_to_cpu(frozen_pe_no), |
1521 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
1522 | ret = EEH_NEXT_ERR_NONE; |
1523 | } else if ((*pe)->state & EEH_PE_ISOLATED || |
1524 | eeh_pe_passed(*pe)) { |
1525 | ret = EEH_NEXT_ERR_NONE; |
1526 | } else { |
1527 | pr_err("EEH: Frozen PE#%x " |
1528 | "on PHB#%x detected\n" , |
1529 | (*pe)->addr, |
1530 | (*pe)->phb->global_number); |
1531 | pr_err("EEH: PE location: %s, " |
1532 | "PHB location: %s\n" , |
1533 | eeh_pe_loc_get(*pe), |
1534 | eeh_pe_loc_get(phb_pe)); |
1535 | ret = EEH_NEXT_ERR_FROZEN_PE; |
1536 | } |
1537 | |
1538 | break; |
1539 | default: |
1540 | pr_warn("%s: Unexpected error type %d\n" , |
1541 | __func__, be16_to_cpu(err_type)); |
1542 | } |
1543 | |
1544 | /* |
1545 | * EEH core will try recover from fenced PHB or |
1546 | * frozen PE. In the time for frozen PE, EEH core |
1547 | * enable IO path for that before collecting logs, |
1548 | * but it ruins the site. So we have to dump the |
1549 | * log in advance here. |
1550 | */ |
1551 | if ((ret == EEH_NEXT_ERR_FROZEN_PE || |
1552 | ret == EEH_NEXT_ERR_FENCED_PHB) && |
1553 | !((*pe)->state & EEH_PE_ISOLATED)) { |
1554 | eeh_pe_mark_isolated(*pe); |
1555 | pnv_eeh_get_phb_diag(*pe); |
1556 | |
1557 | if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) |
1558 | pnv_pci_dump_phb_diag_data((*pe)->phb, |
1559 | (*pe)->data); |
1560 | } |
1561 | |
1562 | /* |
1563 | * We probably have the frozen parent PE out there and |
1564 | * we need have to handle frozen parent PE firstly. |
1565 | */ |
1566 | if (ret == EEH_NEXT_ERR_FROZEN_PE) { |
1567 | parent_pe = (*pe)->parent; |
1568 | while (parent_pe) { |
1569 | /* Hit the ceiling ? */ |
1570 | if (parent_pe->type & EEH_PE_PHB) |
1571 | break; |
1572 | |
1573 | /* Frozen parent PE ? */ |
1574 | state = eeh_ops->get_state(parent_pe, NULL); |
1575 | if (state > 0 && !eeh_state_active(state)) |
1576 | *pe = parent_pe; |
1577 | |
1578 | /* Next parent level */ |
1579 | parent_pe = parent_pe->parent; |
1580 | } |
1581 | |
1582 | /* We possibly migrate to another PE */ |
1583 | eeh_pe_mark_isolated(*pe); |
1584 | } |
1585 | |
1586 | /* |
1587 | * If we have no errors on the specific PHB or only |
1588 | * informative error there, we continue poking it. |
1589 | * Otherwise, we need actions to be taken by upper |
1590 | * layer. |
1591 | */ |
1592 | if (ret > EEH_NEXT_ERR_INF) |
1593 | break; |
1594 | } |
1595 | |
1596 | /* Unmask the event */ |
1597 | if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) |
1598 | enable_irq(irq: eeh_event_irq); |
1599 | |
1600 | return ret; |
1601 | } |
1602 | |
1603 | static int pnv_eeh_restore_config(struct eeh_dev *edev) |
1604 | { |
1605 | struct pnv_phb *phb; |
1606 | s64 ret = 0; |
1607 | |
1608 | if (!edev) |
1609 | return -EEXIST; |
1610 | |
1611 | if (edev->physfn) |
1612 | return 0; |
1613 | |
1614 | phb = edev->controller->private_data; |
1615 | ret = opal_pci_reinit(phb->opal_id, |
1616 | OPAL_REINIT_PCI_DEV, edev->bdfn); |
1617 | |
1618 | if (ret) { |
1619 | pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n" , |
1620 | __func__, edev->bdfn, ret); |
1621 | return -EIO; |
1622 | } |
1623 | |
1624 | return ret; |
1625 | } |
1626 | |
1627 | static struct eeh_ops pnv_eeh_ops = { |
1628 | .name = "powernv" , |
1629 | .probe = pnv_eeh_probe, |
1630 | .set_option = pnv_eeh_set_option, |
1631 | .get_state = pnv_eeh_get_state, |
1632 | .reset = pnv_eeh_reset, |
1633 | .get_log = pnv_eeh_get_log, |
1634 | .configure_bridge = pnv_eeh_configure_bridge, |
1635 | .err_inject = pnv_eeh_err_inject, |
1636 | .read_config = pnv_eeh_read_config, |
1637 | .write_config = pnv_eeh_write_config, |
1638 | .next_error = pnv_eeh_next_error, |
1639 | .restore_config = pnv_eeh_restore_config, |
1640 | .notify_resume = NULL |
1641 | }; |
1642 | |
1643 | /** |
1644 | * eeh_powernv_init - Register platform dependent EEH operations |
1645 | * |
1646 | * EEH initialization on powernv platform. This function should be |
1647 | * called before any EEH related functions. |
1648 | */ |
1649 | static int __init eeh_powernv_init(void) |
1650 | { |
1651 | int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; |
1652 | struct pci_controller *hose; |
1653 | struct pnv_phb *phb; |
1654 | int ret = -EINVAL; |
1655 | |
1656 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
1657 | pr_warn("%s: OPAL is required !\n" , __func__); |
1658 | return -EINVAL; |
1659 | } |
1660 | |
1661 | /* Set probe mode */ |
1662 | eeh_add_flag(EEH_PROBE_MODE_DEV); |
1663 | |
1664 | /* |
1665 | * P7IOC blocks PCI config access to frozen PE, but PHB3 |
1666 | * doesn't do that. So we have to selectively enable I/O |
1667 | * prior to collecting error log. |
1668 | */ |
1669 | list_for_each_entry(hose, &hose_list, list_node) { |
1670 | phb = hose->private_data; |
1671 | |
1672 | if (phb->model == PNV_PHB_MODEL_P7IOC) |
1673 | eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); |
1674 | |
1675 | if (phb->diag_data_size > max_diag_size) |
1676 | max_diag_size = phb->diag_data_size; |
1677 | |
1678 | break; |
1679 | } |
1680 | |
1681 | /* |
1682 | * eeh_init() allocates the eeh_pe and its aux data buf so the |
1683 | * size needs to be set before calling eeh_init(). |
1684 | */ |
1685 | eeh_set_pe_aux_size(max_diag_size); |
1686 | ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; |
1687 | |
1688 | ret = eeh_init(&pnv_eeh_ops); |
1689 | if (!ret) |
1690 | pr_info("EEH: PowerNV platform initialized\n" ); |
1691 | else |
1692 | pr_info("EEH: Failed to initialize PowerNV platform (%d)\n" , ret); |
1693 | |
1694 | return ret; |
1695 | } |
1696 | machine_arch_initcall(powernv, eeh_powernv_init); |
1697 | |