| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * trampoline.S: Jump start slave processors on sparc64. |
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| 4 | * |
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| 5 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) |
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| 6 | */ |
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| 7 | |
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| 8 | |
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| 9 | #include <linux/pgtable.h> |
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| 10 | #include <asm/head.h> |
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| 11 | #include <asm/asi.h> |
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| 12 | #include <asm/lsu.h> |
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| 13 | #include <asm/dcr.h> |
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| 14 | #include <asm/dcu.h> |
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| 15 | #include <asm/pstate.h> |
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| 16 | #include <asm/page.h> |
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| 17 | #include <asm/spitfire.h> |
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| 18 | #include <asm/processor.h> |
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| 19 | #include <asm/thread_info.h> |
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| 20 | #include <asm/mmu.h> |
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| 21 | #include <asm/hypervisor.h> |
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| 22 | #include <asm/cpudata.h> |
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| 23 | |
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| 24 | .data |
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| 25 | .align 8 |
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| 26 | call_method: |
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| 27 | .asciz "call-method" |
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| 28 | .align 8 |
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| 29 | itlb_load: |
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| 30 | .asciz "SUNW,itlb-load" |
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| 31 | .align 8 |
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| 32 | dtlb_load: |
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| 33 | .asciz "SUNW,dtlb-load" |
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| 34 | |
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| 35 | #define TRAMP_STACK_SIZE 1024 |
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| 36 | .align 16 |
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| 37 | tramp_stack: |
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| 38 | .skip TRAMP_STACK_SIZE |
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| 39 | |
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| 40 | .align 8 |
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| 41 | .globl sparc64_cpu_startup, sparc64_cpu_startup_end |
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| 42 | sparc64_cpu_startup: |
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| 43 | BRANCH_IF_SUN4V(g1, niagara_startup) |
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| 44 | BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup) |
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| 45 | BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup) |
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| 46 | |
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| 47 | ba,pt %xcc, spitfire_startup |
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| 48 | nop |
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| 49 | |
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| 50 | cheetah_plus_startup: |
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| 51 | /* Preserve OBP chosen DCU and DCR register settings. */ |
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| 52 | ba,pt %xcc, cheetah_generic_startup |
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| 53 | nop |
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| 54 | |
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| 55 | cheetah_startup: |
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| 56 | mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 |
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| 57 | wr %g1, %asr18 |
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| 58 | |
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| 59 | sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 |
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| 60 | or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 |
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| 61 | sllx %g5, 32, %g5 |
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| 62 | or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5 |
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| 63 | stxa %g5, [%g0] ASI_DCU_CONTROL_REG |
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| 64 | membar #Sync |
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| 65 | /* fallthru */ |
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| 66 | |
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| 67 | cheetah_generic_startup: |
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| 68 | mov TSB_EXTENSION_P, %g3 |
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| 69 | stxa %g0, [%g3] ASI_DMMU |
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| 70 | stxa %g0, [%g3] ASI_IMMU |
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| 71 | membar #Sync |
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| 72 | |
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| 73 | mov TSB_EXTENSION_S, %g3 |
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| 74 | stxa %g0, [%g3] ASI_DMMU |
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| 75 | membar #Sync |
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| 76 | |
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| 77 | mov TSB_EXTENSION_N, %g3 |
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| 78 | stxa %g0, [%g3] ASI_DMMU |
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| 79 | stxa %g0, [%g3] ASI_IMMU |
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| 80 | membar #Sync |
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| 81 | /* fallthru */ |
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| 82 | |
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| 83 | niagara_startup: |
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| 84 | /* Disable STICK_INT interrupts. */ |
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| 85 | sethi %hi(0x80000000), %g5 |
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| 86 | sllx %g5, 32, %g5 |
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| 87 | wr %g5, %asr25 |
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| 88 | |
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| 89 | ba,pt %xcc, startup_continue |
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| 90 | nop |
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| 91 | |
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| 92 | spitfire_startup: |
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| 93 | mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1 |
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| 94 | stxa %g1, [%g0] ASI_LSU_CONTROL |
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| 95 | membar #Sync |
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| 96 | |
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| 97 | startup_continue: |
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| 98 | mov %o0, %l0 |
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| 99 | BRANCH_IF_SUN4V(g1, niagara_lock_tlb) |
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| 100 | |
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| 101 | sethi %hi(0x80000000), %g2 |
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| 102 | sllx %g2, 32, %g2 |
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| 103 | wr %g2, 0, %tick_cmpr |
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| 104 | |
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| 105 | /* Call OBP by hand to lock KERNBASE into i/d tlbs. |
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| 106 | * We lock 'num_kernel_image_mappings' consequetive entries. |
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| 107 | */ |
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| 108 | sethi %hi(prom_entry_lock), %g2 |
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| 109 | 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1 |
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| 110 | brnz,pn %g1, 1b |
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| 111 | nop |
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| 112 | |
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| 113 | /* Get onto temporary stack which will be in the locked |
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| 114 | * kernel image. |
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| 115 | */ |
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| 116 | sethi %hi(tramp_stack), %g1 |
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| 117 | or %g1, %lo(tramp_stack), %g1 |
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| 118 | add %g1, TRAMP_STACK_SIZE, %g1 |
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| 119 | sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp |
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| 120 | flushw |
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| 121 | |
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| 122 | /* Setup the loop variables: |
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| 123 | * %l3: VADDR base |
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| 124 | * %l4: TTE base |
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| 125 | * %l5: Loop iterator, iterates from 0 to 'num_kernel_image_mappings' |
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| 126 | * %l6: Number of TTE entries to map |
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| 127 | * %l7: Highest TTE entry number, we count down |
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| 128 | */ |
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| 129 | sethi %hi(KERNBASE), %l3 |
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| 130 | sethi %hi(kern_locked_tte_data), %l4 |
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| 131 | ldx [%l4 + %lo(kern_locked_tte_data)], %l4 |
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| 132 | clr %l5 |
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| 133 | sethi %hi(num_kernel_image_mappings), %l6 |
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| 134 | lduw [%l6 + %lo(num_kernel_image_mappings)], %l6 |
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| 135 | |
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| 136 | mov 15, %l7 |
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| 137 | BRANCH_IF_ANY_CHEETAH(g1,g5,2f) |
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| 138 | |
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| 139 | mov 63, %l7 |
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| 140 | 2: |
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| 141 | |
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| 142 | 3: |
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| 143 | /* Lock into I-MMU */ |
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| 144 | sethi %hi(call_method), %g2 |
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| 145 | or %g2, %lo(call_method), %g2 |
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| 146 | stx %g2, [%sp + 2047 + 128 + 0x00] |
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| 147 | mov 5, %g2 |
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| 148 | stx %g2, [%sp + 2047 + 128 + 0x08] |
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| 149 | mov 1, %g2 |
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| 150 | stx %g2, [%sp + 2047 + 128 + 0x10] |
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| 151 | sethi %hi(itlb_load), %g2 |
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| 152 | or %g2, %lo(itlb_load), %g2 |
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| 153 | stx %g2, [%sp + 2047 + 128 + 0x18] |
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| 154 | sethi %hi(prom_mmu_ihandle_cache), %g2 |
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| 155 | lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2 |
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| 156 | stx %g2, [%sp + 2047 + 128 + 0x20] |
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| 157 | |
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| 158 | /* Each TTE maps 4MB, convert index to offset. */ |
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| 159 | sllx %l5, 22, %g1 |
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| 160 | |
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| 161 | add %l3, %g1, %g2 |
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| 162 | stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR |
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| 163 | add %l4, %g1, %g2 |
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| 164 | stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE |
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| 165 | |
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| 166 | /* TTE index is highest minus loop index. */ |
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| 167 | sub %l7, %l5, %g2 |
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| 168 | stx %g2, [%sp + 2047 + 128 + 0x38] |
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| 169 | |
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| 170 | sethi %hi(p1275buf), %g2 |
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| 171 | or %g2, %lo(p1275buf), %g2 |
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| 172 | ldx [%g2 + 0x08], %o1 |
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| 173 | call %o1 |
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| 174 | add %sp, (2047 + 128), %o0 |
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| 175 | |
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| 176 | /* Lock into D-MMU */ |
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| 177 | sethi %hi(call_method), %g2 |
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| 178 | or %g2, %lo(call_method), %g2 |
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| 179 | stx %g2, [%sp + 2047 + 128 + 0x00] |
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| 180 | mov 5, %g2 |
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| 181 | stx %g2, [%sp + 2047 + 128 + 0x08] |
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| 182 | mov 1, %g2 |
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| 183 | stx %g2, [%sp + 2047 + 128 + 0x10] |
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| 184 | sethi %hi(dtlb_load), %g2 |
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| 185 | or %g2, %lo(dtlb_load), %g2 |
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| 186 | stx %g2, [%sp + 2047 + 128 + 0x18] |
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| 187 | sethi %hi(prom_mmu_ihandle_cache), %g2 |
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| 188 | lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2 |
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| 189 | stx %g2, [%sp + 2047 + 128 + 0x20] |
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| 190 | |
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| 191 | /* Each TTE maps 4MB, convert index to offset. */ |
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| 192 | sllx %l5, 22, %g1 |
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| 193 | |
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| 194 | add %l3, %g1, %g2 |
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| 195 | stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR |
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| 196 | add %l4, %g1, %g2 |
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| 197 | stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE |
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| 198 | |
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| 199 | /* TTE index is highest minus loop index. */ |
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| 200 | sub %l7, %l5, %g2 |
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| 201 | stx %g2, [%sp + 2047 + 128 + 0x38] |
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| 202 | |
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| 203 | sethi %hi(p1275buf), %g2 |
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| 204 | or %g2, %lo(p1275buf), %g2 |
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| 205 | ldx [%g2 + 0x08], %o1 |
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| 206 | call %o1 |
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| 207 | add %sp, (2047 + 128), %o0 |
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| 208 | |
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| 209 | add %l5, 1, %l5 |
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| 210 | cmp %l5, %l6 |
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| 211 | bne,pt %xcc, 3b |
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| 212 | nop |
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| 213 | |
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| 214 | sethi %hi(prom_entry_lock), %g2 |
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| 215 | stb %g0, [%g2 + %lo(prom_entry_lock)] |
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| 216 | |
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| 217 | ba,pt %xcc, after_lock_tlb |
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| 218 | nop |
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| 219 | |
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| 220 | niagara_lock_tlb: |
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| 221 | sethi %hi(KERNBASE), %l3 |
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| 222 | sethi %hi(kern_locked_tte_data), %l4 |
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| 223 | ldx [%l4 + %lo(kern_locked_tte_data)], %l4 |
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| 224 | clr %l5 |
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| 225 | sethi %hi(num_kernel_image_mappings), %l6 |
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| 226 | lduw [%l6 + %lo(num_kernel_image_mappings)], %l6 |
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| 227 | |
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| 228 | 1: |
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| 229 | mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 |
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| 230 | sllx %l5, 22, %g2 |
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| 231 | add %l3, %g2, %o0 |
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| 232 | clr %o1 |
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| 233 | add %l4, %g2, %o2 |
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| 234 | mov HV_MMU_IMMU, %o3 |
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| 235 | ta HV_FAST_TRAP |
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| 236 | |
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| 237 | mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 |
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| 238 | sllx %l5, 22, %g2 |
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| 239 | add %l3, %g2, %o0 |
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| 240 | clr %o1 |
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| 241 | add %l4, %g2, %o2 |
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| 242 | mov HV_MMU_DMMU, %o3 |
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| 243 | ta HV_FAST_TRAP |
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| 244 | |
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| 245 | add %l5, 1, %l5 |
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| 246 | cmp %l5, %l6 |
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| 247 | bne,pt %xcc, 1b |
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| 248 | nop |
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| 249 | |
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| 250 | after_lock_tlb: |
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| 251 | wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate |
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| 252 | wr %g0, 0, %fprs |
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| 253 | |
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| 254 | wr %g0, ASI_P, %asi |
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| 255 | |
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| 256 | mov PRIMARY_CONTEXT, %g7 |
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| 257 | |
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| 258 | 661: stxa %g0, [%g7] ASI_DMMU |
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| 259 | .section .sun4v_1insn_patch, "ax" |
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| 260 | .word 661b |
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| 261 | stxa %g0, [%g7] ASI_MMU |
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| 262 | .previous |
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| 263 | |
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| 264 | membar #Sync |
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| 265 | mov SECONDARY_CONTEXT, %g7 |
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| 266 | |
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| 267 | 661: stxa %g0, [%g7] ASI_DMMU |
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| 268 | .section .sun4v_1insn_patch, "ax" |
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| 269 | .word 661b |
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| 270 | stxa %g0, [%g7] ASI_MMU |
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| 271 | .previous |
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| 272 | |
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| 273 | membar #Sync |
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| 274 | |
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| 275 | /* Everything we do here, until we properly take over the |
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| 276 | * trap table, must be done with extreme care. We cannot |
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| 277 | * make any references to %g6 (current thread pointer), |
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| 278 | * %g4 (current task pointer), or %g5 (base of current cpu's |
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| 279 | * per-cpu area) until we properly take over the trap table |
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| 280 | * from the firmware and hypervisor. |
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| 281 | * |
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| 282 | * Get onto temporary stack which is in the locked kernel image. |
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| 283 | */ |
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| 284 | sethi %hi(tramp_stack), %g1 |
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| 285 | or %g1, %lo(tramp_stack), %g1 |
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| 286 | add %g1, TRAMP_STACK_SIZE, %g1 |
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| 287 | sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp |
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| 288 | mov 0, %fp |
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| 289 | |
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| 290 | /* Put garbage in these registers to trap any access to them. */ |
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| 291 | set 0xdeadbeef, %g4 |
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| 292 | set 0xdeadbeef, %g5 |
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| 293 | set 0xdeadbeef, %g6 |
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| 294 | |
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| 295 | call init_irqwork_curcpu |
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| 296 | nop |
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| 297 | |
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| 298 | sethi %hi(tlb_type), %g3 |
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| 299 | lduw [%g3 + %lo(tlb_type)], %g2 |
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| 300 | cmp %g2, 3 |
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| 301 | bne,pt %icc, 1f |
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| 302 | nop |
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| 303 | |
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| 304 | call hard_smp_processor_id |
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| 305 | nop |
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| 306 | |
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| 307 | call sun4v_register_mondo_queues |
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| 308 | nop |
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| 309 | |
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| 310 | 1: call init_cur_cpu_trap |
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| 311 | ldx [%l0], %o0 |
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| 312 | |
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| 313 | /* Start using proper page size encodings in ctx register. */ |
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| 314 | sethi %hi(sparc64_kern_pri_context), %g3 |
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| 315 | ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 |
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| 316 | mov PRIMARY_CONTEXT, %g1 |
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| 317 | |
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| 318 | 661: stxa %g2, [%g1] ASI_DMMU |
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| 319 | .section .sun4v_1insn_patch, "ax" |
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| 320 | .word 661b |
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| 321 | stxa %g2, [%g1] ASI_MMU |
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| 322 | .previous |
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| 323 | |
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| 324 | membar #Sync |
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| 325 | |
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| 326 | wrpr %g0, 0, %wstate |
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| 327 | |
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| 328 | sethi %hi(prom_entry_lock), %g2 |
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| 329 | 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1 |
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| 330 | brnz,pn %g1, 1b |
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| 331 | nop |
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| 332 | |
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| 333 | /* As a hack, put &init_thread_union into %g6. |
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| 334 | * prom_world() loads from here to restore the %asi |
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| 335 | * register. |
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| 336 | */ |
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| 337 | sethi %hi(init_thread_union), %g6 |
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| 338 | or %g6, %lo(init_thread_union), %g6 |
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| 339 | |
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| 340 | sethi %hi(is_sun4v), %o0 |
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| 341 | lduw [%o0 + %lo(is_sun4v)], %o0 |
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| 342 | brz,pt %o0, 2f |
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| 343 | nop |
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| 344 | |
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| 345 | TRAP_LOAD_TRAP_BLOCK(%g2, %g3) |
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| 346 | add %g2, TRAP_PER_CPU_FAULT_INFO, %g2 |
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| 347 | stxa %g2, [%g0] ASI_SCRATCHPAD |
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| 348 | |
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| 349 | /* Compute physical address: |
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| 350 | * |
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| 351 | * paddr = kern_base + (mmfsa_vaddr - KERNBASE) |
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| 352 | */ |
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| 353 | sethi %hi(KERNBASE), %g3 |
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| 354 | sub %g2, %g3, %g2 |
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| 355 | sethi %hi(kern_base), %g3 |
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| 356 | ldx [%g3 + %lo(kern_base)], %g3 |
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| 357 | add %g2, %g3, %o1 |
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| 358 | sethi %hi(sparc64_ttable_tl0), %o0 |
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| 359 | |
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| 360 | set prom_set_trap_table_name, %g2 |
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| 361 | stx %g2, [%sp + 2047 + 128 + 0x00] |
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| 362 | mov 2, %g2 |
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| 363 | stx %g2, [%sp + 2047 + 128 + 0x08] |
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| 364 | mov 0, %g2 |
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| 365 | stx %g2, [%sp + 2047 + 128 + 0x10] |
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| 366 | stx %o0, [%sp + 2047 + 128 + 0x18] |
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| 367 | stx %o1, [%sp + 2047 + 128 + 0x20] |
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| 368 | sethi %hi(p1275buf), %g2 |
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| 369 | or %g2, %lo(p1275buf), %g2 |
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| 370 | ldx [%g2 + 0x08], %o1 |
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| 371 | call %o1 |
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| 372 | add %sp, (2047 + 128), %o0 |
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| 373 | |
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| 374 | ba,pt %xcc, 3f |
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| 375 | nop |
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| 376 | |
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| 377 | 2: sethi %hi(sparc64_ttable_tl0), %o0 |
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| 378 | set prom_set_trap_table_name, %g2 |
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| 379 | stx %g2, [%sp + 2047 + 128 + 0x00] |
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| 380 | mov 1, %g2 |
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| 381 | stx %g2, [%sp + 2047 + 128 + 0x08] |
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| 382 | mov 0, %g2 |
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| 383 | stx %g2, [%sp + 2047 + 128 + 0x10] |
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| 384 | stx %o0, [%sp + 2047 + 128 + 0x18] |
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| 385 | sethi %hi(p1275buf), %g2 |
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| 386 | or %g2, %lo(p1275buf), %g2 |
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| 387 | ldx [%g2 + 0x08], %o1 |
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| 388 | call %o1 |
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| 389 | add %sp, (2047 + 128), %o0 |
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| 390 | |
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| 391 | 3: sethi %hi(prom_entry_lock), %g2 |
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| 392 | stb %g0, [%g2 + %lo(prom_entry_lock)] |
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| 393 | |
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| 394 | ldx [%l0], %g6 |
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| 395 | ldx [%g6 + TI_TASK], %g4 |
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| 396 | |
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| 397 | mov 1, %g5 |
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| 398 | sllx %g5, THREAD_SHIFT, %g5 |
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| 399 | sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 |
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| 400 | add %g6, %g5, %sp |
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| 401 | |
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| 402 | rdpr %pstate, %o1 |
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| 403 | or %o1, PSTATE_IE, %o1 |
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| 404 | wrpr %o1, 0, %pstate |
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| 405 | |
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| 406 | call smp_callin |
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| 407 | nop |
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| 408 | |
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| 409 | call cpu_panic |
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| 410 | nop |
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| 411 | 1: b,a,pt %xcc, 1b |
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| 412 | |
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| 413 | .align 8 |
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| 414 | sparc64_cpu_startup_end: |
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| 415 | |
|---|
