1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * From PPR Vol 1 for AMD Family 19h Model 01h B1 |
4 | * 55898 Rev 0.35 - Feb 5, 2021 |
5 | */ |
6 | |
7 | #include <asm/msr-index.h> |
8 | |
9 | /* IBS_OP_DATA2 DataSrc */ |
10 | #define IBS_DATA_SRC_LOC_CACHE 2 |
11 | #define IBS_DATA_SRC_DRAM 3 |
12 | #define IBS_DATA_SRC_REM_CACHE 4 |
13 | #define IBS_DATA_SRC_IO 7 |
14 | |
15 | /* IBS_OP_DATA2 DataSrc Extension */ |
16 | #define IBS_DATA_SRC_EXT_LOC_CACHE 1 |
17 | #define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2 |
18 | #define IBS_DATA_SRC_EXT_DRAM 3 |
19 | #define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5 |
20 | #define IBS_DATA_SRC_EXT_PMEM 6 |
21 | #define IBS_DATA_SRC_EXT_IO 7 |
22 | #define IBS_DATA_SRC_EXT_EXT_MEM 8 |
23 | #define IBS_DATA_SRC_EXT_PEER_AGENT_MEM 12 |
24 | |
25 | /* |
26 | * IBS Hardware MSRs |
27 | */ |
28 | |
29 | /* MSR 0xc0011030: IBS Fetch Control */ |
30 | union ibs_fetch_ctl { |
31 | __u64 val; |
32 | struct { |
33 | __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */ |
34 | fetch_cnt:16, /* 16-31: instruction fetch count */ |
35 | fetch_lat:16, /* 32-47: instruction fetch latency */ |
36 | fetch_en:1, /* 48: instruction fetch enable */ |
37 | fetch_val:1, /* 49: instruction fetch valid */ |
38 | fetch_comp:1, /* 50: instruction fetch complete */ |
39 | ic_miss:1, /* 51: i-cache miss */ |
40 | phy_addr_valid:1,/* 52: physical address valid */ |
41 | l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size |
42 | * (needs IbsPhyAddrValid) */ |
43 | l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */ |
44 | l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */ |
45 | rand_en:1, /* 57: random tagging enable */ |
46 | fetch_l2_miss:1,/* 58: L2 miss for sampled fetch |
47 | * (needs IbsFetchComp) */ |
48 | l3_miss_only:1, /* 59: Collect L3 miss samples only */ |
49 | fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */ |
50 | fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */ |
51 | reserved:2; /* 62-63: reserved */ |
52 | }; |
53 | }; |
54 | |
55 | /* MSR 0xc0011033: IBS Execution Control */ |
56 | union ibs_op_ctl { |
57 | __u64 val; |
58 | struct { |
59 | __u64 opmaxcnt:16, /* 0-15: periodic op max. count */ |
60 | l3_miss_only:1, /* 16: Collect L3 miss samples only */ |
61 | op_en:1, /* 17: op sampling enable */ |
62 | op_val:1, /* 18: op sample valid */ |
63 | cnt_ctl:1, /* 19: periodic op counter control */ |
64 | opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */ |
65 | reserved0:5, /* 27-31: reserved */ |
66 | opcurcnt:27, /* 32-58: periodic op counter current count */ |
67 | reserved1:5; /* 59-63: reserved */ |
68 | }; |
69 | }; |
70 | |
71 | /* MSR 0xc0011035: IBS Op Data 1 */ |
72 | union ibs_op_data { |
73 | __u64 val; |
74 | struct { |
75 | __u64 comp_to_ret_ctr:16, /* 0-15: op completion to retire count */ |
76 | tag_to_ret_ctr:16, /* 15-31: op tag to retire count */ |
77 | reserved1:2, /* 32-33: reserved */ |
78 | op_return:1, /* 34: return op */ |
79 | op_brn_taken:1, /* 35: taken branch op */ |
80 | op_brn_misp:1, /* 36: mispredicted branch op */ |
81 | op_brn_ret:1, /* 37: branch op retired */ |
82 | op_rip_invalid:1, /* 38: RIP is invalid */ |
83 | op_brn_fuse:1, /* 39: fused branch op */ |
84 | op_microcode:1, /* 40: microcode op */ |
85 | reserved2:23; /* 41-63: reserved */ |
86 | }; |
87 | }; |
88 | |
89 | /* MSR 0xc0011036: IBS Op Data 2 */ |
90 | union ibs_op_data2 { |
91 | __u64 val; |
92 | struct { |
93 | __u64 data_src_lo:3, /* 0-2: data source low */ |
94 | reserved0:1, /* 3: reserved */ |
95 | rmt_node:1, /* 4: destination node */ |
96 | cache_hit_st:1, /* 5: cache hit state */ |
97 | data_src_hi:2, /* 6-7: data source high */ |
98 | reserved1:56; /* 8-63: reserved */ |
99 | }; |
100 | }; |
101 | |
102 | /* MSR 0xc0011037: IBS Op Data 3 */ |
103 | union ibs_op_data3 { |
104 | __u64 val; |
105 | struct { |
106 | __u64 ld_op:1, /* 0: load op */ |
107 | st_op:1, /* 1: store op */ |
108 | dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */ |
109 | dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */ |
110 | dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */ |
111 | dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */ |
112 | dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */ |
113 | dc_miss:1, /* 7: data cache miss */ |
114 | dc_mis_acc:1, /* 8: misaligned access */ |
115 | reserved:4, /* 9-12: reserved */ |
116 | dc_wc_mem_acc:1, /* 13: write combining memory access */ |
117 | dc_uc_mem_acc:1, /* 14: uncacheable memory access */ |
118 | dc_locked_op:1, /* 15: locked operation */ |
119 | dc_miss_no_mab_alloc:1, /* 16: DC miss with no MAB allocated */ |
120 | dc_lin_addr_valid:1, /* 17: data cache linear address valid */ |
121 | dc_phy_addr_valid:1, /* 18: data cache physical address valid */ |
122 | dc_l2_tlb_hit_1g:1, /* 19: data cache L2 hit in 1GB page */ |
123 | l2_miss:1, /* 20: L2 cache miss */ |
124 | sw_pf:1, /* 21: software prefetch */ |
125 | op_mem_width:4, /* 22-25: load/store size in bytes */ |
126 | op_dc_miss_open_mem_reqs:6, /* 26-31: outstanding mem reqs on DC fill */ |
127 | dc_miss_lat:16, /* 32-47: data cache miss latency */ |
128 | tlb_refill_lat:16; /* 48-63: L1 TLB refill latency */ |
129 | }; |
130 | }; |
131 | |
132 | /* MSR 0xc001103c: IBS Fetch Control Extended */ |
133 | union ic_ibs_extd_ctl { |
134 | __u64 val; |
135 | struct { |
136 | __u64 itlb_refill_lat:16, /* 0-15: ITLB Refill latency for sampled fetch */ |
137 | reserved:48; /* 16-63: reserved */ |
138 | }; |
139 | }; |
140 | |
141 | /* |
142 | * IBS driver related |
143 | */ |
144 | |
145 | struct perf_ibs_data { |
146 | u32 size; |
147 | union { |
148 | u32 data[0]; /* data buffer starts here */ |
149 | u32 caps; |
150 | }; |
151 | u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX]; |
152 | }; |
153 | |