| 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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| 2 | #ifndef _UAPI_ASM_X86_DEBUGREG_H |
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| 3 | #define _UAPI_ASM_X86_DEBUGREG_H |
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| 4 | |
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| 5 | |
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| 6 | /* Indicate the register numbers for a number of the specific |
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| 7 | debug registers. Registers 0-3 contain the addresses we wish to trap on */ |
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| 8 | #define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */ |
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| 9 | #define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */ |
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| 10 | |
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| 11 | #define DR_STATUS 6 /* u_debugreg[DR_STATUS] */ |
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| 12 | #define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */ |
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| 13 | |
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| 14 | /* Define a few things for the status register. We can use this to determine |
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| 15 | which debugging register was responsible for the trap. The other bits |
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| 16 | are either reserved or not of interest to us. */ |
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| 17 | |
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| 18 | /* Define reserved bits in DR6 which are always set to 1 */ |
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| 19 | #define DR6_RESERVED (0xFFFF0FF0) |
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| 20 | |
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| 21 | #define DR_TRAP0 (0x1) /* db0 */ |
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| 22 | #define DR_TRAP1 (0x2) /* db1 */ |
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| 23 | #define DR_TRAP2 (0x4) /* db2 */ |
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| 24 | #define DR_TRAP3 (0x8) /* db3 */ |
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| 25 | #define DR_TRAP_BITS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3) |
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| 26 | |
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| 27 | #define DR_BUS_LOCK (0x800) /* bus_lock */ |
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| 28 | #define DR_STEP (0x4000) /* single-step */ |
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| 29 | #define DR_SWITCH (0x8000) /* task switch */ |
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| 30 | |
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| 31 | /* Now define a bunch of things for manipulating the control register. |
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| 32 | The top two bytes of the control register consist of 4 fields of 4 |
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| 33 | bits - each field corresponds to one of the four debug registers, |
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| 34 | and indicates what types of access we trap on, and how large the data |
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| 35 | field is that we are looking at */ |
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| 36 | |
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| 37 | #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */ |
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| 38 | #define DR_CONTROL_SIZE 4 /* 4 control bits per register */ |
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| 39 | |
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| 40 | #define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */ |
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| 41 | #define DR_RW_WRITE (0x1) |
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| 42 | #define DR_RW_READ (0x3) |
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| 43 | |
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| 44 | #define DR_LEN_1 (0x0) /* Settings for data length to trap on */ |
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| 45 | #define DR_LEN_2 (0x4) |
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| 46 | #define DR_LEN_4 (0xC) |
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| 47 | #define DR_LEN_8 (0x8) |
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| 48 | |
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| 49 | /* The low byte to the control register determine which registers are |
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| 50 | enabled. There are 4 fields of two bits. One bit is "local", meaning |
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| 51 | that the processor will reset the bit after a task switch and the other |
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| 52 | is global meaning that we have to explicitly reset the bit. With linux, |
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| 53 | you can use either one, since we explicitly zero the register when we enter |
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| 54 | kernel mode. */ |
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| 55 | |
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| 56 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */ |
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| 57 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */ |
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| 58 | #define DR_LOCAL_ENABLE (0x1) /* Local enable for reg 0 */ |
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| 59 | #define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */ |
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| 60 | #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */ |
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| 61 | |
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| 62 | #define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */ |
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| 63 | #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */ |
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| 64 | |
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| 65 | /* The second byte to the control register has a few special things. |
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| 66 | We can slow the instruction pipeline for instructions coming via the |
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| 67 | gdt or the ldt if we want to. I am not sure why this is an advantage */ |
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| 68 | |
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| 69 | #ifdef __i386__ |
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| 70 | #define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */ |
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| 71 | #else |
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| 72 | #define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */ |
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| 73 | #endif |
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| 74 | |
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| 75 | #define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */ |
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| 76 | #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */ |
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| 77 | |
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| 78 | /* |
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| 79 | * HW breakpoint additions |
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| 80 | */ |
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| 81 | |
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| 82 | #endif /* _UAPI_ASM_X86_DEBUGREG_H */ |
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| 83 | |
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