1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2020-2023 Intel Corporation |
4 | */ |
5 | |
6 | #ifndef __IVPU_HW_H__ |
7 | #define __IVPU_HW_H__ |
8 | |
9 | #include "ivpu_drv.h" |
10 | |
11 | struct ivpu_hw_ops { |
12 | int (*info_init)(struct ivpu_device *vdev); |
13 | int (*power_up)(struct ivpu_device *vdev); |
14 | int (*boot_fw)(struct ivpu_device *vdev); |
15 | int (*power_down)(struct ivpu_device *vdev); |
16 | int (*reset)(struct ivpu_device *vdev); |
17 | bool (*is_idle)(struct ivpu_device *vdev); |
18 | void (*wdt_disable)(struct ivpu_device *vdev); |
19 | void (*diagnose_failure)(struct ivpu_device *vdev); |
20 | u32 (*reg_pll_freq_get)(struct ivpu_device *vdev); |
21 | u32 (*reg_telemetry_offset_get)(struct ivpu_device *vdev); |
22 | u32 (*reg_telemetry_size_get)(struct ivpu_device *vdev); |
23 | u32 (*reg_telemetry_enable_get)(struct ivpu_device *vdev); |
24 | void (*reg_db_set)(struct ivpu_device *vdev, u32 db_id); |
25 | u32 (*reg_ipc_rx_addr_get)(struct ivpu_device *vdev); |
26 | u32 (*reg_ipc_rx_count_get)(struct ivpu_device *vdev); |
27 | void (*reg_ipc_tx_set)(struct ivpu_device *vdev, u32 vpu_addr); |
28 | void (*irq_clear)(struct ivpu_device *vdev); |
29 | void (*irq_enable)(struct ivpu_device *vdev); |
30 | void (*irq_disable)(struct ivpu_device *vdev); |
31 | irqreturn_t (*irq_handler)(int irq, void *ptr); |
32 | }; |
33 | |
34 | struct ivpu_addr_range { |
35 | resource_size_t start; |
36 | resource_size_t end; |
37 | }; |
38 | |
39 | struct ivpu_hw_info { |
40 | const struct ivpu_hw_ops *ops; |
41 | struct { |
42 | struct ivpu_addr_range global; |
43 | struct ivpu_addr_range user; |
44 | struct ivpu_addr_range shave; |
45 | struct ivpu_addr_range dma; |
46 | } ranges; |
47 | struct { |
48 | u8 min_ratio; |
49 | u8 max_ratio; |
50 | /* |
51 | * Pll ratio for the efficiency frequency. The VPU has optimum |
52 | * performance to power ratio at this frequency. |
53 | */ |
54 | u8 pn_ratio; |
55 | u32 profiling_freq; |
56 | } pll; |
57 | u32 tile_fuse; |
58 | u32 sku; |
59 | u16 config; |
60 | int dma_bits; |
61 | }; |
62 | |
63 | extern const struct ivpu_hw_ops ivpu_hw_37xx_ops; |
64 | extern const struct ivpu_hw_ops ivpu_hw_40xx_ops; |
65 | |
66 | static inline int ivpu_hw_info_init(struct ivpu_device *vdev) |
67 | { |
68 | return vdev->hw->ops->info_init(vdev); |
69 | }; |
70 | |
71 | static inline int ivpu_hw_power_up(struct ivpu_device *vdev) |
72 | { |
73 | ivpu_dbg(vdev, PM, "HW power up\n" ); |
74 | |
75 | return vdev->hw->ops->power_up(vdev); |
76 | }; |
77 | |
78 | static inline int ivpu_hw_boot_fw(struct ivpu_device *vdev) |
79 | { |
80 | return vdev->hw->ops->boot_fw(vdev); |
81 | }; |
82 | |
83 | static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev) |
84 | { |
85 | return vdev->hw->ops->is_idle(vdev); |
86 | }; |
87 | |
88 | static inline int ivpu_hw_power_down(struct ivpu_device *vdev) |
89 | { |
90 | ivpu_dbg(vdev, PM, "HW power down\n" ); |
91 | |
92 | return vdev->hw->ops->power_down(vdev); |
93 | }; |
94 | |
95 | static inline int ivpu_hw_reset(struct ivpu_device *vdev) |
96 | { |
97 | ivpu_dbg(vdev, PM, "HW reset\n" ); |
98 | |
99 | return vdev->hw->ops->reset(vdev); |
100 | }; |
101 | |
102 | static inline void ivpu_hw_wdt_disable(struct ivpu_device *vdev) |
103 | { |
104 | vdev->hw->ops->wdt_disable(vdev); |
105 | }; |
106 | |
107 | /* Register indirect accesses */ |
108 | static inline u32 ivpu_hw_reg_pll_freq_get(struct ivpu_device *vdev) |
109 | { |
110 | return vdev->hw->ops->reg_pll_freq_get(vdev); |
111 | }; |
112 | |
113 | static inline u32 ivpu_hw_reg_telemetry_offset_get(struct ivpu_device *vdev) |
114 | { |
115 | return vdev->hw->ops->reg_telemetry_offset_get(vdev); |
116 | }; |
117 | |
118 | static inline u32 ivpu_hw_reg_telemetry_size_get(struct ivpu_device *vdev) |
119 | { |
120 | return vdev->hw->ops->reg_telemetry_size_get(vdev); |
121 | }; |
122 | |
123 | static inline u32 ivpu_hw_reg_telemetry_enable_get(struct ivpu_device *vdev) |
124 | { |
125 | return vdev->hw->ops->reg_telemetry_enable_get(vdev); |
126 | }; |
127 | |
128 | static inline void ivpu_hw_reg_db_set(struct ivpu_device *vdev, u32 db_id) |
129 | { |
130 | vdev->hw->ops->reg_db_set(vdev, db_id); |
131 | }; |
132 | |
133 | static inline u32 ivpu_hw_reg_ipc_rx_addr_get(struct ivpu_device *vdev) |
134 | { |
135 | return vdev->hw->ops->reg_ipc_rx_addr_get(vdev); |
136 | }; |
137 | |
138 | static inline u32 ivpu_hw_reg_ipc_rx_count_get(struct ivpu_device *vdev) |
139 | { |
140 | return vdev->hw->ops->reg_ipc_rx_count_get(vdev); |
141 | }; |
142 | |
143 | static inline void ivpu_hw_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) |
144 | { |
145 | vdev->hw->ops->reg_ipc_tx_set(vdev, vpu_addr); |
146 | }; |
147 | |
148 | static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev) |
149 | { |
150 | vdev->hw->ops->irq_clear(vdev); |
151 | }; |
152 | |
153 | static inline void ivpu_hw_irq_enable(struct ivpu_device *vdev) |
154 | { |
155 | vdev->hw->ops->irq_enable(vdev); |
156 | }; |
157 | |
158 | static inline void ivpu_hw_irq_disable(struct ivpu_device *vdev) |
159 | { |
160 | vdev->hw->ops->irq_disable(vdev); |
161 | }; |
162 | |
163 | static inline void ivpu_hw_init_range(struct ivpu_addr_range *range, u64 start, u64 size) |
164 | { |
165 | range->start = start; |
166 | range->end = start + size; |
167 | } |
168 | |
169 | static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range) |
170 | { |
171 | return range->end - range->start; |
172 | } |
173 | |
174 | static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev) |
175 | { |
176 | vdev->hw->ops->diagnose_failure(vdev); |
177 | } |
178 | |
179 | #endif /* __IVPU_HW_H__ */ |
180 | |