| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Structures used by ASPEED clock drivers |
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| 4 | * |
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| 5 | * Copyright 2019 IBM Corp. |
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| 6 | */ |
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| 7 | |
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| 8 | #include <linux/clk-provider.h> |
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| 9 | #include <linux/kernel.h> |
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| 10 | #include <linux/reset-controller.h> |
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| 11 | #include <linux/spinlock.h> |
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| 12 | |
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| 13 | struct clk_div_table; |
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| 14 | struct regmap; |
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| 15 | |
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| 16 | /** |
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| 17 | * struct aspeed_gate_data - Aspeed gated clocks |
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| 18 | * @clock_idx: bit used to gate this clock in the clock register |
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| 19 | * @reset_idx: bit used to reset this IP in the reset register. -1 if no |
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| 20 | * reset is required when enabling the clock |
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| 21 | * @name: the clock name |
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| 22 | * @parent_name: the name of the parent clock |
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| 23 | * @flags: standard clock framework flags |
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| 24 | */ |
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| 25 | struct aspeed_gate_data { |
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| 26 | u8 clock_idx; |
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| 27 | s8 reset_idx; |
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| 28 | const char *name; |
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| 29 | const char *parent_name; |
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| 30 | unsigned long flags; |
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| 31 | }; |
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| 32 | |
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| 33 | /** |
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| 34 | * struct aspeed_clk_gate - Aspeed specific clk_gate structure |
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| 35 | * @hw: handle between common and hardware-specific interfaces |
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| 36 | * @reg: register controlling gate |
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| 37 | * @clock_idx: bit used to gate this clock in the clock register |
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| 38 | * @reset_idx: bit used to reset this IP in the reset register. -1 if no |
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| 39 | * reset is required when enabling the clock |
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| 40 | * @flags: hardware-specific flags |
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| 41 | * @lock: register lock |
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| 42 | * |
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| 43 | * Some of the clocks in the Aspeed SoC must be put in reset before enabling. |
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| 44 | * This modified version of clk_gate allows an optional reset bit to be |
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| 45 | * specified. |
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| 46 | */ |
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| 47 | struct aspeed_clk_gate { |
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| 48 | struct clk_hw hw; |
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| 49 | struct regmap *map; |
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| 50 | u8 clock_idx; |
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| 51 | s8 reset_idx; |
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| 52 | u8 flags; |
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| 53 | spinlock_t *lock; |
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| 54 | }; |
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| 55 | |
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| 56 | #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) |
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| 57 | |
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| 58 | /** |
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| 59 | * struct aspeed_reset - Aspeed reset controller |
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| 60 | * @map: regmap to access the containing system controller |
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| 61 | * @rcdev: reset controller device |
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| 62 | */ |
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| 63 | struct aspeed_reset { |
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| 64 | struct regmap *map; |
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| 65 | struct reset_controller_dev rcdev; |
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| 66 | }; |
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| 67 | |
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| 68 | #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) |
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| 69 | |
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| 70 | /** |
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| 71 | * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information |
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| 72 | * @div_table: Common divider lookup table |
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| 73 | * @eclk_div_table: Divider lookup table for ECLK |
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| 74 | * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks |
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| 75 | * @calc_pll: Callback to maculate common PLL settings |
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| 76 | */ |
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| 77 | struct aspeed_clk_soc_data { |
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| 78 | const struct clk_div_table *div_table; |
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| 79 | const struct clk_div_table *eclk_div_table; |
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| 80 | const struct clk_div_table *mac_div_table; |
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| 81 | struct clk_hw *(*calc_pll)(const char *name, u32 val); |
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| 82 | }; |
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| 83 | |
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