1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. |
5 | */ |
6 | |
7 | #include <linux/kernel.h> |
8 | #include <linux/bitops.h> |
9 | #include <linux/err.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/export.h> |
12 | #include <linux/clk-provider.h> |
13 | #include <linux/regmap.h> |
14 | |
15 | #include "clk-branch.h" |
16 | |
17 | static bool clk_branch_in_hwcg_mode(const struct clk_branch *br) |
18 | { |
19 | u32 val; |
20 | |
21 | if (!br->hwcg_reg) |
22 | return false; |
23 | |
24 | regmap_read(map: br->clkr.regmap, reg: br->hwcg_reg, val: &val); |
25 | |
26 | return !!(val & BIT(br->hwcg_bit)); |
27 | } |
28 | |
29 | static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling) |
30 | { |
31 | bool invert = (br->halt_check == BRANCH_HALT_ENABLE); |
32 | u32 val; |
33 | |
34 | regmap_read(map: br->clkr.regmap, reg: br->halt_reg, val: &val); |
35 | |
36 | val &= BIT(br->halt_bit); |
37 | if (invert) |
38 | val = !val; |
39 | |
40 | return !!val == !enabling; |
41 | } |
42 | |
43 | static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling) |
44 | { |
45 | u32 val; |
46 | u32 mask; |
47 | bool invert = (br->halt_check == BRANCH_HALT_ENABLE); |
48 | |
49 | mask = CBCR_NOC_FSM_STATUS; |
50 | mask |= CBCR_CLK_OFF; |
51 | |
52 | regmap_read(map: br->clkr.regmap, reg: br->halt_reg, val: &val); |
53 | |
54 | if (enabling) { |
55 | val &= mask; |
56 | return (val & CBCR_CLK_OFF) == (invert ? CBCR_CLK_OFF : 0) || |
57 | FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON; |
58 | } |
59 | return (val & CBCR_CLK_OFF) == (invert ? 0 : CBCR_CLK_OFF); |
60 | } |
61 | |
62 | static int clk_branch_wait(const struct clk_branch *br, bool enabling, |
63 | bool (check_halt)(const struct clk_branch *, bool)) |
64 | { |
65 | bool voted = br->halt_check & BRANCH_VOTED; |
66 | const char *name = clk_hw_get_name(hw: &br->clkr.hw); |
67 | |
68 | /* |
69 | * Skip checking halt bit if we're explicitly ignoring the bit or the |
70 | * clock is in hardware gated mode |
71 | */ |
72 | if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br)) |
73 | return 0; |
74 | |
75 | if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) { |
76 | udelay(10); |
77 | } else if (br->halt_check == BRANCH_HALT_ENABLE || |
78 | br->halt_check == BRANCH_HALT || |
79 | (enabling && voted)) { |
80 | int count = 200; |
81 | |
82 | while (count-- > 0) { |
83 | if (check_halt(br, enabling)) |
84 | return 0; |
85 | udelay(1); |
86 | } |
87 | WARN(1, "%s status stuck at 'o%s'" , name, |
88 | enabling ? "ff" : "n" ); |
89 | return -EBUSY; |
90 | } |
91 | return 0; |
92 | } |
93 | |
94 | static int clk_branch_toggle(struct clk_hw *hw, bool en, |
95 | bool (check_halt)(const struct clk_branch *, bool)) |
96 | { |
97 | struct clk_branch *br = to_clk_branch(hw); |
98 | int ret; |
99 | |
100 | if (en) { |
101 | ret = clk_enable_regmap(hw); |
102 | if (ret) |
103 | return ret; |
104 | } else { |
105 | clk_disable_regmap(hw); |
106 | } |
107 | |
108 | return clk_branch_wait(br, enabling: en, check_halt); |
109 | } |
110 | |
111 | static int clk_branch_enable(struct clk_hw *hw) |
112 | { |
113 | return clk_branch_toggle(hw, en: true, check_halt: clk_branch_check_halt); |
114 | } |
115 | |
116 | static void clk_branch_disable(struct clk_hw *hw) |
117 | { |
118 | clk_branch_toggle(hw, en: false, check_halt: clk_branch_check_halt); |
119 | } |
120 | |
121 | const struct clk_ops clk_branch_ops = { |
122 | .enable = clk_branch_enable, |
123 | .disable = clk_branch_disable, |
124 | .is_enabled = clk_is_enabled_regmap, |
125 | }; |
126 | EXPORT_SYMBOL_GPL(clk_branch_ops); |
127 | |
128 | static int clk_branch2_enable(struct clk_hw *hw) |
129 | { |
130 | return clk_branch_toggle(hw, en: true, check_halt: clk_branch2_check_halt); |
131 | } |
132 | |
133 | static void clk_branch2_disable(struct clk_hw *hw) |
134 | { |
135 | clk_branch_toggle(hw, en: false, check_halt: clk_branch2_check_halt); |
136 | } |
137 | |
138 | static int clk_branch2_mem_enable(struct clk_hw *hw) |
139 | { |
140 | struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); |
141 | struct clk_branch branch = mem_br->branch; |
142 | u32 val; |
143 | int ret; |
144 | |
145 | regmap_update_bits(map: branch.clkr.regmap, reg: mem_br->mem_enable_reg, |
146 | mask: mem_br->mem_enable_ack_mask, val: mem_br->mem_enable_ack_mask); |
147 | |
148 | ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg, |
149 | val, val & mem_br->mem_enable_ack_mask, 0, 200); |
150 | if (ret) { |
151 | WARN(1, "%s mem enable failed\n" , clk_hw_get_name(&branch.clkr.hw)); |
152 | return ret; |
153 | } |
154 | |
155 | return clk_branch2_enable(hw); |
156 | } |
157 | |
158 | static void clk_branch2_mem_disable(struct clk_hw *hw) |
159 | { |
160 | struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); |
161 | |
162 | regmap_update_bits(map: mem_br->branch.clkr.regmap, reg: mem_br->mem_enable_reg, |
163 | mask: mem_br->mem_enable_ack_mask, val: 0); |
164 | |
165 | return clk_branch2_disable(hw); |
166 | } |
167 | |
168 | const struct clk_ops clk_branch2_mem_ops = { |
169 | .enable = clk_branch2_mem_enable, |
170 | .disable = clk_branch2_mem_disable, |
171 | .is_enabled = clk_is_enabled_regmap, |
172 | }; |
173 | EXPORT_SYMBOL_GPL(clk_branch2_mem_ops); |
174 | |
175 | const struct clk_ops clk_branch2_ops = { |
176 | .enable = clk_branch2_enable, |
177 | .disable = clk_branch2_disable, |
178 | .is_enabled = clk_is_enabled_regmap, |
179 | }; |
180 | EXPORT_SYMBOL_GPL(clk_branch2_ops); |
181 | |
182 | const struct clk_ops clk_branch2_aon_ops = { |
183 | .enable = clk_branch2_enable, |
184 | .is_enabled = clk_is_enabled_regmap, |
185 | }; |
186 | EXPORT_SYMBOL_GPL(clk_branch2_aon_ops); |
187 | |
188 | const struct clk_ops clk_branch_simple_ops = { |
189 | .enable = clk_enable_regmap, |
190 | .disable = clk_disable_regmap, |
191 | .is_enabled = clk_is_enabled_regmap, |
192 | }; |
193 | EXPORT_SYMBOL_GPL(clk_branch_simple_ops); |
194 | |