1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RZ/V2N CPG driver
4 *
5 * Copyright (C) 2025 Renesas Electronics Corp.
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/clk/renesas.h>
10#include <linux/device.h>
11#include <linux/init.h>
12#include <linux/kernel.h>
13
14#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15
16#include "rzv2h-cpg.h"
17
18enum clk_ids {
19 /* Core Clock Outputs exported to DT */
20 LAST_DT_CORE_CLK = R9A09G056_USB3_0_CLKCORE,
21
22 /* External Input Clocks */
23 CLK_AUDIO_EXTAL,
24 CLK_RTXIN,
25 CLK_QEXTAL,
26
27 /* PLL Clocks */
28 CLK_PLLCM33,
29 CLK_PLLCLN,
30 CLK_PLLDTY,
31 CLK_PLLCA55,
32 CLK_PLLVDO,
33 CLK_PLLETH,
34 CLK_PLLDSI,
35 CLK_PLLGPU,
36
37 /* Internal Core Clocks */
38 CLK_PLLCM33_DIV3,
39 CLK_PLLCM33_DIV4,
40 CLK_PLLCM33_DIV5,
41 CLK_PLLCM33_DIV16,
42 CLK_PLLCM33_GEAR,
43 CLK_SMUX2_XSPI_CLK0,
44 CLK_SMUX2_XSPI_CLK1,
45 CLK_PLLCM33_XSPI,
46 CLK_PLLCLN_DIV2,
47 CLK_PLLCLN_DIV8,
48 CLK_PLLCLN_DIV16,
49 CLK_PLLDTY_ACPU,
50 CLK_PLLDTY_ACPU_DIV2,
51 CLK_PLLDTY_ACPU_DIV4,
52 CLK_PLLDTY_DIV8,
53 CLK_PLLDTY_DIV16,
54 CLK_PLLVDO_CRU0,
55 CLK_PLLVDO_CRU1,
56 CLK_PLLVDO_ISP,
57 CLK_PLLETH_DIV_250_FIX,
58 CLK_PLLETH_DIV_125_FIX,
59 CLK_CSDIV_PLLETH_GBE0,
60 CLK_CSDIV_PLLETH_GBE1,
61 CLK_SMUX2_GBE0_TXCLK,
62 CLK_SMUX2_GBE0_RXCLK,
63 CLK_SMUX2_GBE1_TXCLK,
64 CLK_SMUX2_GBE1_RXCLK,
65 CLK_CDIV4_PLLETH_LPCLK,
66 CLK_PLLETH_LPCLK_GEAR,
67 CLK_PLLDSI_GEAR,
68 CLK_PLLGPU_GEAR,
69
70 /* Module Clocks */
71 MOD_CLK_BASE,
72};
73
74static const struct clk_div_table dtable_1_8[] = {
75 {0, 1},
76 {1, 2},
77 {2, 4},
78 {3, 8},
79 {0, 0},
80};
81
82static const struct clk_div_table dtable_2_4[] = {
83 {0, 2},
84 {1, 4},
85 {0, 0},
86};
87
88static const struct clk_div_table dtable_2_16[] = {
89 {0, 2},
90 {1, 4},
91 {2, 8},
92 {3, 16},
93 {0, 0},
94};
95
96static const struct clk_div_table dtable_2_32[] = {
97 {0, 2},
98 {1, 4},
99 {2, 6},
100 {3, 8},
101 {4, 10},
102 {5, 12},
103 {6, 14},
104 {7, 16},
105 {8, 18},
106 {9, 20},
107 {10, 22},
108 {11, 24},
109 {12, 26},
110 {13, 28},
111 {14, 30},
112 {15, 32},
113 {0, 0},
114};
115
116static const struct clk_div_table dtable_2_64[] = {
117 {0, 2},
118 {1, 4},
119 {2, 8},
120 {3, 16},
121 {4, 64},
122 {0, 0},
123};
124
125static const struct clk_div_table dtable_2_100[] = {
126 {0, 2},
127 {1, 10},
128 {2, 100},
129 {0, 0},
130};
131
132static const struct clk_div_table dtable_16_128[] = {
133 {0, 16},
134 {1, 32},
135 {2, 64},
136 {3, 128},
137 {0, 0},
138};
139
140RZV2H_CPG_PLL_DSI_LIMITS(rzv2n_cpg_pll_dsi_limits);
141#define PLLDSI PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2n_cpg_pll_dsi_limits)
142
143/* Mux clock tables */
144static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
145static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
146static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
147static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
148static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
149static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
150
151static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
152 /* External Clock Inputs */
153 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
154 DEF_INPUT("rtxin", CLK_RTXIN),
155 DEF_INPUT("qextal", CLK_QEXTAL),
156
157 /* PLL Clocks */
158 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
159 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
160 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
161 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
162 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
163 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
164 DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
165 DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
166
167 /* Internal Core Clocks */
168 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
169 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
170 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
171 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
172 DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
173 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
174 DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
175 DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
176 dtable_2_16),
177
178 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
179 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
180 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
181
182 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
183 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
184 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
185 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
186 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
187
188 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
189 DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
190 DEF_DDIV(".pllvdo_isp", CLK_PLLVDO_ISP, CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
191
192 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
193 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
194 DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
195 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
196 DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
197 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
198 DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
199 DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
200 DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
201 DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
202 DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
203 DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
204 CSDIV0_DIVCTL2, dtable_16_128),
205
206 DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
207 CSDIV1_DIVCTL2, dtable_2_32),
208
209 DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
210
211 /* Core Clocks */
212 DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
213 DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
214 CDDIV1_DIVCTL0, dtable_1_8),
215 DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55,
216 CDDIV1_DIVCTL1, dtable_1_8),
217 DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55,
218 CDDIV1_DIVCTL2, dtable_1_8),
219 DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
220 CDDIV1_DIVCTL3, dtable_1_8),
221 DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
222 DEF_FIXED("usb2_0_clk_core0", R9A09G056_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
223 DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G056_GBETH_0_CLK_PTP_REF_I,
224 CLK_PLLETH_DIV_125_FIX, 1, 1),
225 DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I,
226 CLK_PLLETH_DIV_125_FIX, 1, 1),
227 DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
228 FIXED_MOD_CONF_XSPI),
229 DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G056_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
230 DEF_FIXED("usb3_0_core_clk", R9A09G056_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
231};
232
233static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
234 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
235 BUS_MSTOP(3, BIT(5))),
236 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
237 BUS_MSTOP(5, BIT(10))),
238 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
239 BUS_MSTOP(5, BIT(11))),
240 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
241 BUS_MSTOP(2, BIT(13))),
242 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
243 BUS_MSTOP(2, BIT(14))),
244 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
245 BUS_MSTOP(11, BIT(13))),
246 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
247 BUS_MSTOP(11, BIT(14))),
248 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
249 BUS_MSTOP(11, BIT(15))),
250 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
251 BUS_MSTOP(12, BIT(0))),
252 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
253 BUS_MSTOP(3, BIT(10))),
254 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
255 BUS_MSTOP(3, BIT(10))),
256 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
257 BUS_MSTOP(1, BIT(0))),
258 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
259 BUS_MSTOP(1, BIT(0))),
260 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
261 BUS_MSTOP(5, BIT(12))),
262 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
263 BUS_MSTOP(5, BIT(12))),
264 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
265 BUS_MSTOP(5, BIT(13))),
266 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
267 BUS_MSTOP(5, BIT(13))),
268 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
269 BUS_MSTOP(3, BIT(14))),
270 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
271 BUS_MSTOP(10, BIT(15))),
272 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
273 BUS_MSTOP(10, BIT(15))),
274 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
275 BUS_MSTOP(10, BIT(15))),
276 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
277 BUS_MSTOP(3, BIT(13))),
278 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
279 BUS_MSTOP(1, BIT(1))),
280 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
281 BUS_MSTOP(1, BIT(2))),
282 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
283 BUS_MSTOP(1, BIT(3))),
284 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
285 BUS_MSTOP(1, BIT(4))),
286 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
287 BUS_MSTOP(1, BIT(5))),
288 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
289 BUS_MSTOP(1, BIT(6))),
290 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
291 BUS_MSTOP(1, BIT(7))),
292 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
293 BUS_MSTOP(1, BIT(8))),
294 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
295 BUS_MSTOP(4, BIT(5))),
296 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
297 BUS_MSTOP(4, BIT(5))),
298 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
299 BUS_MSTOP(4, BIT(5))),
300 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
301 BUS_MSTOP(8, BIT(2))),
302 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
303 BUS_MSTOP(8, BIT(2))),
304 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
305 BUS_MSTOP(8, BIT(2))),
306 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
307 BUS_MSTOP(8, BIT(2))),
308 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
309 BUS_MSTOP(8, BIT(3))),
310 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
311 BUS_MSTOP(8, BIT(3))),
312 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
313 BUS_MSTOP(8, BIT(3))),
314 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
315 BUS_MSTOP(8, BIT(3))),
316 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
317 BUS_MSTOP(8, BIT(4))),
318 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
319 BUS_MSTOP(8, BIT(4))),
320 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
321 BUS_MSTOP(8, BIT(4))),
322 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
323 BUS_MSTOP(8, BIT(4))),
324 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
325 BUS_MSTOP(7, BIT(12))),
326 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
327 BUS_MSTOP(7, BIT(14))),
328 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
329 BUS_MSTOP(7, BIT(7))),
330 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
331 BUS_MSTOP(7, BIT(9))),
332 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
333 BUS_MSTOP(7, BIT(10))),
334 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
335 BUS_MSTOP(8, BIT(5)), 1),
336 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
337 BUS_MSTOP(8, BIT(5)), 1),
338 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
339 BUS_MSTOP(8, BIT(5)), 1),
340 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
341 BUS_MSTOP(8, BIT(5)), 1),
342 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
343 BUS_MSTOP(8, BIT(5))),
344 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
345 BUS_MSTOP(8, BIT(5))),
346 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
347 BUS_MSTOP(8, BIT(6)), 1),
348 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
349 BUS_MSTOP(8, BIT(6)), 1),
350 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
351 BUS_MSTOP(8, BIT(6)), 1),
352 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
353 BUS_MSTOP(8, BIT(6)), 1),
354 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
355 BUS_MSTOP(8, BIT(6))),
356 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
357 BUS_MSTOP(8, BIT(6))),
358 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
359 BUS_MSTOP(9, BIT(4))),
360 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
361 BUS_MSTOP(9, BIT(4))),
362 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
363 BUS_MSTOP(9, BIT(4))),
364 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
365 BUS_MSTOP(9, BIT(5))),
366 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
367 BUS_MSTOP(9, BIT(5))),
368 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
369 BUS_MSTOP(9, BIT(5))),
370 DEF_MOD("isp_0_reg_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
371 BUS_MSTOP(9, BIT(8))),
372 DEF_MOD("isp_0_pclk", CLK_PLLDTY_DIV16, 14, 3, 7, 3,
373 BUS_MSTOP(9, BIT(8))),
374 DEF_MOD("isp_0_vin_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
375 BUS_MSTOP(9, BIT(9))),
376 DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP, 14, 5, 7, 5,
377 BUS_MSTOP(9, BIT(9))),
378 DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
379 BUS_MSTOP(9, BIT(14) | BIT(15))),
380 DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
381 BUS_MSTOP(9, BIT(14) | BIT(15))),
382 DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_GEAR, 14, 10, 7, 10,
383 BUS_MSTOP(9, BIT(14) | BIT(15))),
384 DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
385 BUS_MSTOP(9, BIT(14) | BIT(15))),
386 DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
387 BUS_MSTOP(9, BIT(14) | BIT(15))),
388 DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
389 BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
390 DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
391 BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
392 DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_GEAR, 14, 15, 7, 15,
393 BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
394 DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
395 BUS_MSTOP(3, BIT(4))),
396 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
397 BUS_MSTOP(3, BIT(4))),
398 DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
399 BUS_MSTOP(3, BIT(4))),
400};
401
402static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
403 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
404 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
405 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
406 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
407 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
408 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
409 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
410 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
411 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
412 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
413 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
414 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
415 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
416 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
417 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
418 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
419 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
420 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
421 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
422 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
423 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
424 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
425 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
426 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
427 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
428 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
429 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
430 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
431 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
432 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
433 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
434 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
435 DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
436 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
437 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
438 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
439 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
440 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
441 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
442 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
443 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
444 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
445 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
446 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
447 DEF_RST(13, 1, 6, 2), /* ISP_0_VIN_ARESETN */
448 DEF_RST(13, 2, 6, 3), /* ISP_0_REG_ARESETN */
449 DEF_RST(13, 3, 6, 4), /* ISP_0_ISP_SRESETN */
450 DEF_RST(13, 4, 6, 5), /* ISP_0_PRESETN */
451 DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
452 DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
453 DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
454 DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
455 DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
456 DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
457};
458
459const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
460 /* Core Clocks */
461 .core_clks = r9a09g056_core_clks,
462 .num_core_clks = ARRAY_SIZE(r9a09g056_core_clks),
463 .last_dt_core_clk = LAST_DT_CORE_CLK,
464 .num_total_core_clks = MOD_CLK_BASE,
465
466 /* Module Clocks */
467 .mod_clks = r9a09g056_mod_clks,
468 .num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks),
469 .num_hw_mod_clks = 25 * 16,
470
471 /* Resets */
472 .resets = r9a09g056_resets,
473 .num_resets = ARRAY_SIZE(r9a09g056_resets),
474
475 .num_mstop_bits = 192,
476};
477

source code of linux/drivers/clk/renesas/r9a09g056-cpg.c