1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright 2016 Chen-Yu Tsai |
4 | * |
5 | * Chen-Yu Tsai <wens@csie.org> |
6 | */ |
7 | |
8 | #ifndef _CCU_SUN6I_A31_H_ |
9 | #define _CCU_SUN6I_A31_H_ |
10 | |
11 | #include <dt-bindings/clock/sun6i-a31-ccu.h> |
12 | #include <dt-bindings/reset/sun6i-a31-ccu.h> |
13 | |
14 | #define CLK_PLL_CPU 0 |
15 | #define CLK_PLL_AUDIO_BASE 1 |
16 | #define CLK_PLL_AUDIO 2 |
17 | #define CLK_PLL_AUDIO_2X 3 |
18 | #define CLK_PLL_AUDIO_4X 4 |
19 | #define CLK_PLL_AUDIO_8X 5 |
20 | #define CLK_PLL_VIDEO0 6 |
21 | |
22 | /* The PLL_VIDEO0_2X clock is exported */ |
23 | |
24 | #define CLK_PLL_VE 8 |
25 | #define CLK_PLL_DDR 9 |
26 | |
27 | /* The PLL_PERIPH clock is exported */ |
28 | |
29 | #define CLK_PLL_PERIPH_2X 11 |
30 | #define CLK_PLL_VIDEO1 12 |
31 | |
32 | /* The PLL_VIDEO1_2X clock is exported */ |
33 | |
34 | #define CLK_PLL_GPU 14 |
35 | |
36 | /* The PLL_VIDEO1_2X clock is exported */ |
37 | |
38 | #define CLK_PLL9 16 |
39 | #define CLK_PLL10 17 |
40 | |
41 | /* The CPUX clock is exported */ |
42 | |
43 | #define CLK_AXI 19 |
44 | #define CLK_AHB1 20 |
45 | #define CLK_APB1 21 |
46 | #define CLK_APB2 22 |
47 | |
48 | /* All the bus gates are exported */ |
49 | |
50 | /* The first bunch of module clocks are exported */ |
51 | |
52 | /* EMAC clock is not implemented */ |
53 | |
54 | #define CLK_MDFS 107 |
55 | #define CLK_SDRAM0 108 |
56 | #define CLK_SDRAM1 109 |
57 | |
58 | /* All the DRAM gates are exported */ |
59 | |
60 | /* Some more module clocks are exported */ |
61 | |
62 | #define CLK_MBUS0 141 |
63 | #define CLK_MBUS1 142 |
64 | |
65 | /* Some more module clocks and external clock outputs are exported */ |
66 | |
67 | #define CLK_NUMBER (CLK_OUT_C + 1) |
68 | |
69 | #endif /* _CCU_SUN6I_A31_H_ */ |
70 | |