| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
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| 4 | * |
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| 5 | * Based on ccu-sun8i-h3.h, which is: |
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| 6 | * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef _CCU_SUN8I_V3S_H_ |
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| 10 | #define _CCU_SUN8I_V3S_H_ |
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| 11 | |
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| 12 | #include <dt-bindings/clock/sun8i-v3s-ccu.h> |
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| 13 | #include <dt-bindings/reset/sun8i-v3s-ccu.h> |
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| 14 | |
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| 15 | #define CLK_PLL_CPU 0 |
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| 16 | #define CLK_PLL_AUDIO_BASE 1 |
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| 17 | #define CLK_PLL_AUDIO 2 |
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| 18 | #define CLK_PLL_AUDIO_2X 3 |
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| 19 | #define CLK_PLL_AUDIO_4X 4 |
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| 20 | #define CLK_PLL_AUDIO_8X 5 |
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| 21 | #define CLK_PLL_VIDEO 6 |
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| 22 | #define CLK_PLL_VE 7 |
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| 23 | #define CLK_PLL_DDR0 8 |
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| 24 | #define CLK_PLL_PERIPH0 9 |
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| 25 | #define CLK_PLL_PERIPH0_2X 10 |
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| 26 | #define CLK_PLL_ISP 11 |
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| 27 | #define CLK_PLL_PERIPH1 12 |
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| 28 | /* Reserve one number for not implemented and not used PLL_DDR1 */ |
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| 29 | |
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| 30 | /* The CPU clock is exported */ |
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| 31 | |
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| 32 | #define CLK_AXI 15 |
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| 33 | #define CLK_AHB1 16 |
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| 34 | #define CLK_APB1 17 |
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| 35 | #define CLK_APB2 18 |
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| 36 | #define CLK_AHB2 19 |
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| 37 | |
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| 38 | /* All the bus gates are exported */ |
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| 39 | |
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| 40 | /* The first bunch of module clocks are exported */ |
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| 41 | |
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| 42 | #define CLK_DRAM 58 |
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| 43 | |
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| 44 | /* All the DRAM gates are exported */ |
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| 45 | |
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| 46 | /* Some more module clocks are exported */ |
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| 47 | |
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| 48 | #define CLK_MBUS 72 |
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| 49 | |
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| 50 | /* And the GPU module clock is exported */ |
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| 51 | |
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| 52 | #define CLK_PLL_DDR1 74 |
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| 53 | |
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| 54 | #endif /* _CCU_SUN8I_V3S_H_ */ |
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| 55 | |
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