| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright (c) 2016 Maxime Ripard. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef _CCU_GATE_H_ |
| 7 | #define _CCU_GATE_H_ |
| 8 | |
| 9 | #include <linux/clk-provider.h> |
| 10 | |
| 11 | #include "ccu_common.h" |
| 12 | |
| 13 | struct ccu_gate { |
| 14 | u32 enable; |
| 15 | |
| 16 | struct ccu_common common; |
| 17 | }; |
| 18 | |
| 19 | #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ |
| 20 | struct ccu_gate _struct = { \ |
| 21 | .enable = _gate, \ |
| 22 | .common = { \ |
| 23 | .reg = _reg, \ |
| 24 | .hw.init = CLK_HW_INIT(_name, \ |
| 25 | _parent, \ |
| 26 | &ccu_gate_ops, \ |
| 27 | _flags), \ |
| 28 | } \ |
| 29 | } |
| 30 | |
| 31 | #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ |
| 32 | struct ccu_gate _struct = { \ |
| 33 | .enable = _gate, \ |
| 34 | .common = { \ |
| 35 | .reg = _reg, \ |
| 36 | .hw.init = CLK_HW_INIT_HW(_name, \ |
| 37 | _parent, \ |
| 38 | &ccu_gate_ops, \ |
| 39 | _flags), \ |
| 40 | } \ |
| 41 | } |
| 42 | |
| 43 | #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ |
| 44 | struct ccu_gate _struct = { \ |
| 45 | .enable = _gate, \ |
| 46 | .common = { \ |
| 47 | .reg = _reg, \ |
| 48 | .hw.init = CLK_HW_INIT_FW_NAME(_name, \ |
| 49 | _parent, \ |
| 50 | &ccu_gate_ops, \ |
| 51 | _flags), \ |
| 52 | } \ |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * The following macros allow the re-use of the data structure |
| 57 | * holding the parent info. |
| 58 | */ |
| 59 | #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ |
| 60 | struct ccu_gate _struct = { \ |
| 61 | .enable = _gate, \ |
| 62 | .common = { \ |
| 63 | .reg = _reg, \ |
| 64 | .hw.init = CLK_HW_INIT_HWS(_name, \ |
| 65 | _parent, \ |
| 66 | &ccu_gate_ops, \ |
| 67 | _flags), \ |
| 68 | } \ |
| 69 | } |
| 70 | |
| 71 | #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ |
| 72 | _gate, _prediv, _flags) \ |
| 73 | struct ccu_gate _struct = { \ |
| 74 | .enable = _gate, \ |
| 75 | .common = { \ |
| 76 | .reg = _reg, \ |
| 77 | .prediv = _prediv, \ |
| 78 | .features = CCU_FEATURE_ALL_PREDIV, \ |
| 79 | .hw.init = CLK_HW_INIT_HWS(_name, \ |
| 80 | _parent, \ |
| 81 | &ccu_gate_ops, \ |
| 82 | _flags), \ |
| 83 | } \ |
| 84 | } |
| 85 | |
| 86 | #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ |
| 87 | struct ccu_gate _struct = { \ |
| 88 | .enable = _gate, \ |
| 89 | .common = { \ |
| 90 | .reg = _reg, \ |
| 91 | .hw.init = \ |
| 92 | CLK_HW_INIT_PARENTS_DATA(_name, \ |
| 93 | _data, \ |
| 94 | &ccu_gate_ops, \ |
| 95 | _flags), \ |
| 96 | } \ |
| 97 | } |
| 98 | |
| 99 | #define SUNXI_CCU_GATE_DATA_WITH_PREDIV(_struct, _name, _parent, _reg, \ |
| 100 | _gate, _prediv, _flags) \ |
| 101 | struct ccu_gate _struct = { \ |
| 102 | .enable = _gate, \ |
| 103 | .common = { \ |
| 104 | .reg = _reg, \ |
| 105 | .prediv = _prediv, \ |
| 106 | .features = CCU_FEATURE_ALL_PREDIV, \ |
| 107 | .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \ |
| 108 | _parent, \ |
| 109 | &ccu_gate_ops, \ |
| 110 | _flags), \ |
| 111 | } \ |
| 112 | } |
| 113 | |
| 114 | static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw) |
| 115 | { |
| 116 | struct ccu_common *common = hw_to_ccu_common(hw); |
| 117 | |
| 118 | return container_of(common, struct ccu_gate, common); |
| 119 | } |
| 120 | |
| 121 | void ccu_gate_helper_disable(struct ccu_common *common, u32 gate); |
| 122 | int ccu_gate_helper_enable(struct ccu_common *common, u32 gate); |
| 123 | int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate); |
| 124 | |
| 125 | extern const struct clk_ops ccu_gate_ops; |
| 126 | |
| 127 | #endif /* _CCU_GATE_H_ */ |
| 128 | |