1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * COMEDI driver for the ADLINK PCI-723x/743x series boards.
4 * Copyright (C) 2012 H Hartley Sweeten <hsweeten@visionengravers.com>
5 *
6 * Based on the adl_pci7230 driver written by:
7 * David Fernandez <dfcastelao@gmail.com>
8 * and the adl_pci7432 driver written by:
9 * Michel Lachaine <mike@mikelachaine.ca>
10 *
11 * COMEDI - Linux Control and Measurement Device Interface
12 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
13 */
14
15/*
16 * Driver: adl_pci7x3x
17 * Description: 32/64-Channel Isolated Digital I/O Boards
18 * Devices: [ADLink] PCI-7230 (adl_pci7230), PCI-7233 (adl_pci7233),
19 * PCI-7234 (adl_pci7234), PCI-7432 (adl_pci7432), PCI-7433 (adl_pci7433),
20 * PCI-7434 (adl_pci7434)
21 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
22 * Updated: Fri, 20 Nov 2020 14:49:36 +0000
23 * Status: works (tested on PCI-7230)
24 *
25 * One or two subdevices are setup by this driver depending on
26 * the number of digital inputs and/or outputs provided by the
27 * board. Each subdevice has a maximum of 32 channels.
28 *
29 * PCI-7230 - 4 subdevices: 0 - 16 input, 1 - 16 output,
30 * 2 - IRQ_IDI0, 3 - IRQ_IDI1
31 * PCI-7233 - 1 subdevice: 0 - 32 input
32 * PCI-7234 - 1 subdevice: 0 - 32 output
33 * PCI-7432 - 2 subdevices: 0 - 32 input, 1 - 32 output
34 * PCI-7433 - 2 subdevices: 0 - 32 input, 1 - 32 input
35 * PCI-7434 - 2 subdevices: 0 - 32 output, 1 - 32 output
36 *
37 * The PCI-7230, PCI-7432 and PCI-7433 boards also support external
38 * interrupt signals on digital input channels 0 and 1. The PCI-7233
39 * has dual-interrupt sources for change-of-state (COS) on any 16
40 * digital input channels of LSB and for COS on any 16 digital input
41 * lines of MSB.
42 *
43 * Currently, this driver only supports interrupts for PCI-7230.
44 *
45 * Configuration Options: not applicable, uses comedi PCI auto config
46 */
47
48#include <linux/module.h>
49#include <linux/comedi/comedi_pci.h>
50
51#include "plx9052.h"
52
53/*
54 * Register I/O map (32-bit access only)
55 */
56#define PCI7X3X_DIO_REG 0x0000 /* in the DigIO Port area */
57#define PCI743X_DIO_REG 0x0004
58
59#define ADL_PT_CLRIRQ 0x0040 /* in the DigIO Port area */
60
61#define LINTI1_EN_ACT_IDI0 (PLX9052_INTCSR_LI1ENAB | PLX9052_INTCSR_LI1STAT)
62#define LINTI2_EN_ACT_IDI1 (PLX9052_INTCSR_LI2ENAB | PLX9052_INTCSR_LI2STAT)
63#define EN_PCI_LINT2H_LINT1H \
64 (PLX9052_INTCSR_PCIENAB | PLX9052_INTCSR_LI2POL | PLX9052_INTCSR_LI1POL)
65
66enum adl_pci7x3x_boardid {
67 BOARD_PCI7230,
68 BOARD_PCI7233,
69 BOARD_PCI7234,
70 BOARD_PCI7432,
71 BOARD_PCI7433,
72 BOARD_PCI7434,
73};
74
75struct adl_pci7x3x_boardinfo {
76 const char *name;
77 int nsubdevs;
78 int di_nchan;
79 int do_nchan;
80 int irq_nchan;
81};
82
83static const struct adl_pci7x3x_boardinfo adl_pci7x3x_boards[] = {
84 [BOARD_PCI7230] = {
85 .name = "adl_pci7230",
86 .nsubdevs = 4, /* IDI, IDO, IRQ_IDI0, IRQ_IDI1 */
87 .di_nchan = 16,
88 .do_nchan = 16,
89 .irq_nchan = 2,
90 },
91 [BOARD_PCI7233] = {
92 .name = "adl_pci7233",
93 .nsubdevs = 1,
94 .di_nchan = 32,
95 },
96 [BOARD_PCI7234] = {
97 .name = "adl_pci7234",
98 .nsubdevs = 1,
99 .do_nchan = 32,
100 },
101 [BOARD_PCI7432] = {
102 .name = "adl_pci7432",
103 .nsubdevs = 2,
104 .di_nchan = 32,
105 .do_nchan = 32,
106 },
107 [BOARD_PCI7433] = {
108 .name = "adl_pci7433",
109 .nsubdevs = 2,
110 .di_nchan = 64,
111 },
112 [BOARD_PCI7434] = {
113 .name = "adl_pci7434",
114 .nsubdevs = 2,
115 .do_nchan = 64,
116 }
117};
118
119struct adl_pci7x3x_dev_private_data {
120 unsigned long lcr_io_base;
121 unsigned int int_ctrl;
122};
123
124struct adl_pci7x3x_sd_private_data {
125 spinlock_t subd_slock; /* spin-lock for cmd_running */
126 unsigned long port_offset;
127 short int cmd_running;
128};
129
130static void process_irq(struct comedi_device *dev, unsigned int subdev,
131 unsigned short intcsr)
132{
133 struct comedi_subdevice *s = &dev->subdevices[subdev];
134 struct adl_pci7x3x_sd_private_data *sd_priv = s->private;
135 unsigned long reg = sd_priv->port_offset;
136 struct comedi_async *async_p = s->async;
137
138 if (async_p) {
139 unsigned short val = inw(port: dev->iobase + reg);
140
141 spin_lock(lock: &sd_priv->subd_slock);
142 if (sd_priv->cmd_running)
143 comedi_buf_write_samples(s, data: &val, nsamples: 1);
144 spin_unlock(lock: &sd_priv->subd_slock);
145 comedi_handle_events(dev, s);
146 }
147}
148
149static irqreturn_t adl_pci7x3x_interrupt(int irq, void *p_device)
150{
151 struct comedi_device *dev = p_device;
152 struct adl_pci7x3x_dev_private_data *dev_private = dev->private;
153 unsigned long cpu_flags;
154 unsigned int intcsr;
155 bool li1stat, li2stat;
156
157 if (!dev->attached) {
158 /* Ignore interrupt before device fully attached. */
159 /* Might not even have allocated subdevices yet! */
160 return IRQ_NONE;
161 }
162
163 /* Check if we are source of interrupt */
164 spin_lock_irqsave(&dev->spinlock, cpu_flags);
165 intcsr = inl(port: dev_private->lcr_io_base + PLX9052_INTCSR);
166 li1stat = (intcsr & LINTI1_EN_ACT_IDI0) == LINTI1_EN_ACT_IDI0;
167 li2stat = (intcsr & LINTI2_EN_ACT_IDI1) == LINTI2_EN_ACT_IDI1;
168 if (li1stat || li2stat) {
169 /* clear all current interrupt flags */
170 /* Fixme: Reset all 2 Int Flags */
171 outb(value: 0x00, port: dev->iobase + ADL_PT_CLRIRQ);
172 }
173 spin_unlock_irqrestore(lock: &dev->spinlock, flags: cpu_flags);
174
175 /* SubDev 2, 3 = Isolated DigIn , on "SCSI2" jack!*/
176
177 if (li1stat) /* 0x0005 LINTi1 is Enabled && IDI0 is 1 */
178 process_irq(dev, subdev: 2, intcsr);
179
180 if (li2stat) /* 0x0028 LINTi2 is Enabled && IDI1 is 1 */
181 process_irq(dev, subdev: 3, intcsr);
182
183 return IRQ_RETVAL(li1stat || li2stat);
184}
185
186static int adl_pci7x3x_asy_cmdtest(struct comedi_device *dev,
187 struct comedi_subdevice *s,
188 struct comedi_cmd *cmd)
189{
190 int err = 0;
191
192 /* Step 1 : check if triggers are trivially valid */
193
194 err |= comedi_check_trigger_src(src: &cmd->start_src, TRIG_NOW);
195 err |= comedi_check_trigger_src(src: &cmd->scan_begin_src, TRIG_EXT);
196 err |= comedi_check_trigger_src(src: &cmd->convert_src, TRIG_FOLLOW);
197 err |= comedi_check_trigger_src(src: &cmd->scan_end_src, TRIG_COUNT);
198 err |= comedi_check_trigger_src(src: &cmd->stop_src, TRIG_NONE);
199
200 if (err)
201 return 1;
202
203 /* Step 2a : make sure trigger sources are unique */
204 /* Step 2b : and mutually compatible */
205
206 /* Step 3: check if arguments are trivially valid */
207
208 err |= comedi_check_trigger_arg_is(arg: &cmd->start_arg, val: 0);
209 err |= comedi_check_trigger_arg_is(arg: &cmd->scan_begin_arg, val: 0);
210 err |= comedi_check_trigger_arg_is(arg: &cmd->convert_arg, val: 0);
211 err |= comedi_check_trigger_arg_is(arg: &cmd->scan_end_arg,
212 val: cmd->chanlist_len);
213 err |= comedi_check_trigger_arg_is(arg: &cmd->stop_arg, val: 0);
214
215 if (err)
216 return 3;
217
218 /* Step 4: fix up any arguments */
219
220 /* Step 5: check channel list if it exists */
221
222 return 0;
223}
224
225static int adl_pci7x3x_asy_cmd(struct comedi_device *dev,
226 struct comedi_subdevice *s)
227{
228 struct adl_pci7x3x_dev_private_data *dev_private = dev->private;
229 struct adl_pci7x3x_sd_private_data *sd_priv = s->private;
230 unsigned long cpu_flags;
231 unsigned int int_enab;
232
233 if (s->index == 2) {
234 /* enable LINTi1 == IDI sdi[0] Ch 0 IRQ ActHigh */
235 int_enab = PLX9052_INTCSR_LI1ENAB;
236 } else {
237 /* enable LINTi2 == IDI sdi[0] Ch 1 IRQ ActHigh */
238 int_enab = PLX9052_INTCSR_LI2ENAB;
239 }
240
241 spin_lock_irqsave(&dev->spinlock, cpu_flags);
242 dev_private->int_ctrl |= int_enab;
243 outl(value: dev_private->int_ctrl, port: dev_private->lcr_io_base + PLX9052_INTCSR);
244 spin_unlock_irqrestore(lock: &dev->spinlock, flags: cpu_flags);
245
246 spin_lock_irqsave(&sd_priv->subd_slock, cpu_flags);
247 sd_priv->cmd_running = 1;
248 spin_unlock_irqrestore(lock: &sd_priv->subd_slock, flags: cpu_flags);
249
250 return 0;
251}
252
253static int adl_pci7x3x_asy_cancel(struct comedi_device *dev,
254 struct comedi_subdevice *s)
255{
256 struct adl_pci7x3x_dev_private_data *dev_private = dev->private;
257 struct adl_pci7x3x_sd_private_data *sd_priv = s->private;
258 unsigned long cpu_flags;
259 unsigned int int_enab;
260
261 spin_lock_irqsave(&sd_priv->subd_slock, cpu_flags);
262 sd_priv->cmd_running = 0;
263 spin_unlock_irqrestore(lock: &sd_priv->subd_slock, flags: cpu_flags);
264 /* disable Interrupts */
265 if (s->index == 2)
266 int_enab = PLX9052_INTCSR_LI1ENAB;
267 else
268 int_enab = PLX9052_INTCSR_LI2ENAB;
269 spin_lock_irqsave(&dev->spinlock, cpu_flags);
270 dev_private->int_ctrl &= ~int_enab;
271 outl(value: dev_private->int_ctrl, port: dev_private->lcr_io_base + PLX9052_INTCSR);
272 spin_unlock_irqrestore(lock: &dev->spinlock, flags: cpu_flags);
273
274 return 0;
275}
276
277/* same as _di_insn_bits because the IRQ-pins are the DI-ports */
278static int adl_pci7x3x_dirq_insn_bits(struct comedi_device *dev,
279 struct comedi_subdevice *s,
280 struct comedi_insn *insn,
281 unsigned int *data)
282{
283 struct adl_pci7x3x_sd_private_data *sd_priv = s->private;
284 unsigned long reg = (unsigned long)sd_priv->port_offset;
285
286 data[1] = inl(port: dev->iobase + reg);
287
288 return insn->n;
289}
290
291static int adl_pci7x3x_do_insn_bits(struct comedi_device *dev,
292 struct comedi_subdevice *s,
293 struct comedi_insn *insn,
294 unsigned int *data)
295{
296 unsigned long reg = (unsigned long)s->private;
297
298 if (comedi_dio_update_state(s, data)) {
299 unsigned int val = s->state;
300
301 if (s->n_chan == 16) {
302 /*
303 * It seems the PCI-7230 needs the 16-bit DO state
304 * to be shifted left by 16 bits before being written
305 * to the 32-bit register. Set the value in both
306 * halves of the register to be sure.
307 */
308 val |= val << 16;
309 }
310 outl(value: val, port: dev->iobase + reg);
311 }
312
313 data[1] = s->state;
314
315 return insn->n;
316}
317
318static int adl_pci7x3x_di_insn_bits(struct comedi_device *dev,
319 struct comedi_subdevice *s,
320 struct comedi_insn *insn,
321 unsigned int *data)
322{
323 unsigned long reg = (unsigned long)s->private;
324
325 data[1] = inl(port: dev->iobase + reg);
326
327 return insn->n;
328}
329
330static int adl_pci7x3x_reset(struct comedi_device *dev)
331{
332 struct adl_pci7x3x_dev_private_data *dev_private = dev->private;
333
334 /* disable Interrupts */
335 dev_private->int_ctrl = 0x00; /* Disable PCI + LINTi2 + LINTi1 */
336 outl(value: dev_private->int_ctrl, port: dev_private->lcr_io_base + PLX9052_INTCSR);
337
338 return 0;
339}
340
341static int adl_pci7x3x_auto_attach(struct comedi_device *dev,
342 unsigned long context)
343{
344 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
345 const struct adl_pci7x3x_boardinfo *board = NULL;
346 struct comedi_subdevice *s;
347 struct adl_pci7x3x_dev_private_data *dev_private;
348 int subdev;
349 int nchan;
350 int ret;
351 int ic;
352
353 if (context < ARRAY_SIZE(adl_pci7x3x_boards))
354 board = &adl_pci7x3x_boards[context];
355 if (!board)
356 return -ENODEV;
357 dev->board_ptr = board;
358 dev->board_name = board->name;
359
360 dev_private = comedi_alloc_devpriv(dev, size: sizeof(*dev_private));
361 if (!dev_private)
362 return -ENOMEM;
363
364 ret = comedi_pci_enable(dev);
365 if (ret)
366 return ret;
367 dev->iobase = pci_resource_start(pcidev, 2);
368 dev_private->lcr_io_base = pci_resource_start(pcidev, 1);
369
370 adl_pci7x3x_reset(dev);
371
372 if (board->irq_nchan) {
373 /* discard all evtl. old IRQs */
374 outb(value: 0x00, port: dev->iobase + ADL_PT_CLRIRQ);
375
376 if (pcidev->irq) {
377 ret = request_irq(irq: pcidev->irq, handler: adl_pci7x3x_interrupt,
378 IRQF_SHARED, name: dev->board_name, dev);
379 if (ret == 0) {
380 dev->irq = pcidev->irq;
381 /* 0x52 PCI + IDI Ch 1 Ch 0 IRQ Off ActHigh */
382 dev_private->int_ctrl = EN_PCI_LINT2H_LINT1H;
383 outl(value: dev_private->int_ctrl,
384 port: dev_private->lcr_io_base + PLX9052_INTCSR);
385 }
386 }
387 }
388
389 ret = comedi_alloc_subdevices(dev, num_subdevices: board->nsubdevs);
390 if (ret)
391 return ret;
392
393 subdev = 0;
394
395 if (board->di_nchan) {
396 nchan = min(board->di_nchan, 32);
397
398 s = &dev->subdevices[subdev];
399 /* Isolated digital inputs 0 to 15/31 */
400 s->type = COMEDI_SUBD_DI;
401 s->subdev_flags = SDF_READABLE;
402 s->n_chan = nchan;
403 s->maxdata = 1;
404 s->insn_bits = adl_pci7x3x_di_insn_bits;
405 s->range_table = &range_digital;
406
407 s->private = (void *)PCI7X3X_DIO_REG;
408
409 subdev++;
410
411 nchan = board->di_nchan - nchan;
412 if (nchan) {
413 s = &dev->subdevices[subdev];
414 /* Isolated digital inputs 32 to 63 */
415 s->type = COMEDI_SUBD_DI;
416 s->subdev_flags = SDF_READABLE;
417 s->n_chan = nchan;
418 s->maxdata = 1;
419 s->insn_bits = adl_pci7x3x_di_insn_bits;
420 s->range_table = &range_digital;
421
422 s->private = (void *)PCI743X_DIO_REG;
423
424 subdev++;
425 }
426 }
427
428 if (board->do_nchan) {
429 nchan = min(board->do_nchan, 32);
430
431 s = &dev->subdevices[subdev];
432 /* Isolated digital outputs 0 to 15/31 */
433 s->type = COMEDI_SUBD_DO;
434 s->subdev_flags = SDF_WRITABLE;
435 s->n_chan = nchan;
436 s->maxdata = 1;
437 s->insn_bits = adl_pci7x3x_do_insn_bits;
438 s->range_table = &range_digital;
439
440 s->private = (void *)PCI7X3X_DIO_REG;
441
442 subdev++;
443
444 nchan = board->do_nchan - nchan;
445 if (nchan) {
446 s = &dev->subdevices[subdev];
447 /* Isolated digital outputs 32 to 63 */
448 s->type = COMEDI_SUBD_DO;
449 s->subdev_flags = SDF_WRITABLE;
450 s->n_chan = nchan;
451 s->maxdata = 1;
452 s->insn_bits = adl_pci7x3x_do_insn_bits;
453 s->range_table = &range_digital;
454
455 s->private = (void *)PCI743X_DIO_REG;
456
457 subdev++;
458 }
459 }
460
461 for (ic = 0; ic < board->irq_nchan; ++ic) {
462 struct adl_pci7x3x_sd_private_data *sd_priv;
463
464 nchan = 1;
465
466 s = &dev->subdevices[subdev];
467 /* Isolated digital inputs 0 or 1 */
468 s->type = COMEDI_SUBD_DI;
469 s->subdev_flags = SDF_READABLE;
470 s->n_chan = nchan;
471 s->maxdata = 1;
472 s->insn_bits = adl_pci7x3x_dirq_insn_bits;
473 s->range_table = &range_digital;
474
475 sd_priv = comedi_alloc_spriv(s, size: sizeof(*sd_priv));
476 if (!sd_priv)
477 return -ENOMEM;
478
479 spin_lock_init(&sd_priv->subd_slock);
480 sd_priv->port_offset = PCI7X3X_DIO_REG;
481 sd_priv->cmd_running = 0;
482
483 if (dev->irq) {
484 dev->read_subdev = s;
485 s->type = COMEDI_SUBD_DI;
486 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
487 s->len_chanlist = 1;
488 s->do_cmdtest = adl_pci7x3x_asy_cmdtest;
489 s->do_cmd = adl_pci7x3x_asy_cmd;
490 s->cancel = adl_pci7x3x_asy_cancel;
491 }
492
493 subdev++;
494 }
495
496 return 0;
497}
498
499static void adl_pci7x3x_detach(struct comedi_device *dev)
500{
501 if (dev->iobase)
502 adl_pci7x3x_reset(dev);
503 comedi_pci_detach(dev);
504}
505
506static struct comedi_driver adl_pci7x3x_driver = {
507 .driver_name = "adl_pci7x3x",
508 .module = THIS_MODULE,
509 .auto_attach = adl_pci7x3x_auto_attach,
510 .detach = adl_pci7x3x_detach,
511};
512
513static int adl_pci7x3x_pci_probe(struct pci_dev *dev,
514 const struct pci_device_id *id)
515{
516 return comedi_pci_auto_config(pcidev: dev, driver: &adl_pci7x3x_driver,
517 context: id->driver_data);
518}
519
520static const struct pci_device_id adl_pci7x3x_pci_table[] = {
521 { PCI_VDEVICE(ADLINK, 0x7230), BOARD_PCI7230 },
522 { PCI_VDEVICE(ADLINK, 0x7233), BOARD_PCI7233 },
523 { PCI_VDEVICE(ADLINK, 0x7234), BOARD_PCI7234 },
524 { PCI_VDEVICE(ADLINK, 0x7432), BOARD_PCI7432 },
525 { PCI_VDEVICE(ADLINK, 0x7433), BOARD_PCI7433 },
526 { PCI_VDEVICE(ADLINK, 0x7434), BOARD_PCI7434 },
527 { 0 }
528};
529MODULE_DEVICE_TABLE(pci, adl_pci7x3x_pci_table);
530
531static struct pci_driver adl_pci7x3x_pci_driver = {
532 .name = "adl_pci7x3x",
533 .id_table = adl_pci7x3x_pci_table,
534 .probe = adl_pci7x3x_pci_probe,
535 .remove = comedi_pci_auto_unconfig,
536};
537module_comedi_pci_driver(adl_pci7x3x_driver, adl_pci7x3x_pci_driver);
538
539MODULE_DESCRIPTION("ADLINK PCI-723x/743x Isolated Digital I/O boards");
540MODULE_AUTHOR("H Hartley Sweeten <hsweeten@visionengravers.com>");
541MODULE_LICENSE("GPL");
542

source code of linux/drivers/comedi/drivers/adl_pci7x3x.c