1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Definitions for the PLX-9052 PCI interface chip
4 *
5 * Copyright (C) 2002 MEV Ltd. <https://www.mev.co.uk/>
6 *
7 * COMEDI - Linux Control and Measurement Device Interface
8 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
9 */
10
11#ifndef _PLX9052_H_
12#define _PLX9052_H_
13
14/*
15 * INTCSR - Interrupt Control/Status register
16 */
17#define PLX9052_INTCSR 0x4c
18#define PLX9052_INTCSR_LI1ENAB BIT(0) /* LI1 enabled */
19#define PLX9052_INTCSR_LI1POL BIT(1) /* LI1 active high */
20#define PLX9052_INTCSR_LI1STAT BIT(2) /* LI1 active */
21#define PLX9052_INTCSR_LI2ENAB BIT(3) /* LI2 enabled */
22#define PLX9052_INTCSR_LI2POL BIT(4) /* LI2 active high */
23#define PLX9052_INTCSR_LI2STAT BIT(5) /* LI2 active */
24#define PLX9052_INTCSR_PCIENAB BIT(6) /* PCIINT enabled */
25#define PLX9052_INTCSR_SOFTINT BIT(7) /* generate soft int */
26#define PLX9052_INTCSR_LI1SEL BIT(8) /* LI1 edge */
27#define PLX9052_INTCSR_LI2SEL BIT(9) /* LI2 edge */
28#define PLX9052_INTCSR_LI1CLRINT BIT(10) /* LI1 clear int */
29#define PLX9052_INTCSR_LI2CLRINT BIT(11) /* LI2 clear int */
30#define PLX9052_INTCSR_ISAMODE BIT(12) /* ISA interface mode */
31
32/*
33 * CNTRL - User I/O, Direct Slave Response, Serial EEPROM, and
34 * Initialization Control register
35 */
36#define PLX9052_CNTRL 0x50
37#define PLX9052_CNTRL_WAITO BIT(0) /* UIO0 or WAITO# select */
38#define PLX9052_CNTRL_UIO0_DIR BIT(1) /* UIO0 direction */
39#define PLX9052_CNTRL_UIO0_DATA BIT(2) /* UIO0 data */
40#define PLX9052_CNTRL_LLOCKO BIT(3) /* UIO1 or LLOCKo# select */
41#define PLX9052_CNTRL_UIO1_DIR BIT(4) /* UIO1 direction */
42#define PLX9052_CNTRL_UIO1_DATA BIT(5) /* UIO1 data */
43#define PLX9052_CNTRL_CS2 BIT(6) /* UIO2 or CS2# select */
44#define PLX9052_CNTRL_UIO2_DIR BIT(7) /* UIO2 direction */
45#define PLX9052_CNTRL_UIO2_DATA BIT(8) /* UIO2 data */
46#define PLX9052_CNTRL_CS3 BIT(9) /* UIO3 or CS3# select */
47#define PLX9052_CNTRL_UIO3_DIR BIT(10) /* UIO3 direction */
48#define PLX9052_CNTRL_UIO3_DATA BIT(11) /* UIO3 data */
49#define PLX9052_CNTRL_PCIBAR(x) (((x) & 0x3) << 12)
50#define PLX9052_CNTRL_PCIBAR01 PLX9052_CNTRL_PCIBAR(0) /* mem and IO */
51#define PLX9052_CNTRL_PCIBAR0 PLX9052_CNTRL_PCIBAR(1) /* mem only */
52#define PLX9052_CNTRL_PCIBAR1 PLX9052_CNTRL_PCIBAR(2) /* IO only */
53#define PLX9052_CNTRL_PCI2_1_FEATURES BIT(14) /* PCI v2.1 features enabled */
54#define PLX9052_CNTRL_PCI_R_W_FLUSH BIT(15) /* read w/write flush mode */
55#define PLX9052_CNTRL_PCI_R_NO_FLUSH BIT(16) /* read no flush mode */
56#define PLX9052_CNTRL_PCI_R_NO_WRITE BIT(17) /* read no write mode */
57#define PLX9052_CNTRL_PCI_W_RELEASE BIT(18) /* write release bus mode */
58#define PLX9052_CNTRL_RETRY_CLKS(x) (((x) & 0xf) << 19) /* retry clks */
59#define PLX9052_CNTRL_LOCK_ENAB BIT(23) /* slave LOCK# enable */
60#define PLX9052_CNTRL_EEPROM_MASK (0x1f << 24) /* EEPROM bits */
61#define PLX9052_CNTRL_EEPROM_CLK BIT(24) /* EEPROM clock */
62#define PLX9052_CNTRL_EEPROM_CS BIT(25) /* EEPROM chip select */
63#define PLX9052_CNTRL_EEPROM_DOUT BIT(26) /* EEPROM write bit */
64#define PLX9052_CNTRL_EEPROM_DIN BIT(27) /* EEPROM read bit */
65#define PLX9052_CNTRL_EEPROM_PRESENT BIT(28) /* EEPROM present */
66#define PLX9052_CNTRL_RELOAD_CFG BIT(29) /* reload configuration */
67#define PLX9052_CNTRL_PCI_RESET BIT(30) /* PCI adapter reset */
68#define PLX9052_CNTRL_MASK_REV BIT(31) /* mask revision */
69
70#endif /* _PLX9052_H_ */
71

source code of linux/drivers/comedi/drivers/plx9052.h