1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * comedi/drivers/s626.h |
4 | * Sensoray s626 Comedi driver, header file |
5 | * |
6 | * COMEDI - Linux Control and Measurement Device Interface |
7 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> |
8 | * |
9 | * Based on Sensoray Model 626 Linux driver Version 0.2 |
10 | * Copyright (C) 2002-2004 Sensoray Co., Inc. |
11 | */ |
12 | |
13 | #ifndef S626_H_INCLUDED |
14 | #define S626_H_INCLUDED |
15 | |
16 | #define S626_DMABUF_SIZE 4096 /* 4k pages */ |
17 | |
18 | #define S626_ADC_CHANNELS 16 |
19 | #define S626_DAC_CHANNELS 4 |
20 | #define S626_ENCODER_CHANNELS 6 |
21 | #define S626_DIO_CHANNELS 48 |
22 | #define S626_DIO_BANKS 3 /* Number of DIO groups. */ |
23 | #define S626_DIO_EXTCHANS 40 /* |
24 | * Number of extended-capability |
25 | * DIO channels. |
26 | */ |
27 | |
28 | #define S626_NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ |
29 | |
30 | /* PCI bus interface types. */ |
31 | #define S626_INTEL 1 /* Intel bus type. */ |
32 | #define S626_MOTOROLA 2 /* Motorola bus type. */ |
33 | |
34 | #define S626_PLATFORM S626_INTEL /* *** SELECT PLATFORM TYPE *** */ |
35 | |
36 | #define S626_RANGE_5V 0x10 /* +/-5V range */ |
37 | #define S626_RANGE_10V 0x00 /* +/-10V range */ |
38 | |
39 | #define S626_EOPL 0x80 /* End of ADC poll list marker. */ |
40 | #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */ |
41 | #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */ |
42 | |
43 | /* Error codes that must be visible to this base class. */ |
44 | #define S626_ERR_ILLEGAL_PARM 0x00010000 /* |
45 | * Illegal function parameter |
46 | * value was specified. |
47 | */ |
48 | #define S626_ERR_I2C 0x00020000 /* I2C error. */ |
49 | #define S626_ERR_COUNTERSETUP 0x00200000 /* |
50 | * Illegal setup specified for |
51 | * counter channel. |
52 | */ |
53 | #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ |
54 | |
55 | /* |
56 | * Organization (physical order) and size (in DWORDs) of logical DMA buffers |
57 | * contained by ANA_DMABUF. |
58 | */ |
59 | #define S626_ADC_DMABUF_DWORDS 40 /* |
60 | * ADC DMA buffer must hold 16 samples, |
61 | * plus pre/post garbage samples. |
62 | */ |
63 | #define S626_DAC_WDMABUF_DWORDS 1 /* |
64 | * DAC output DMA buffer holds a single |
65 | * sample. |
66 | */ |
67 | |
68 | /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ |
69 | |
70 | /* Address offsets, in DWORDS, from base of DMA buffer. */ |
71 | #define S626_DAC_WDMABUF_OS S626_ADC_DMABUF_DWORDS |
72 | |
73 | /* Interrupt enable bit in ISR and IER. */ |
74 | #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */ |
75 | #define S626_IRQ_RPS1 0x10000000 |
76 | #define S626_ISR_AFOU 0x00000800 |
77 | /* Audio fifo under/overflow detected. */ |
78 | |
79 | #define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */ |
80 | #define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */ |
81 | #define S626_IRQ_COINT2A 0x1000 /* counter 2A overflow interrupt mask */ |
82 | #define S626_IRQ_COINT2B 0x2000 /* counter 2B overflow interrupt mask */ |
83 | #define S626_IRQ_COINT3A 0x4000 /* counter 3A overflow interrupt mask */ |
84 | #define S626_IRQ_COINT3B 0x8000 /* counter 3B overflow interrupt mask */ |
85 | |
86 | /* RPS command codes. */ |
87 | #define S626_RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */ |
88 | #define S626_RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */ |
89 | #define S626_RPS_NOP 0x00000000 /* NOP */ |
90 | #define S626_RPS_PAUSE 0x20000000 /* PAUSE */ |
91 | #define S626_RPS_UPLOAD 0x40000000 /* UPLOAD */ |
92 | #define S626_RPS_JUMP 0x80000000 /* JUMP */ |
93 | #define S626_RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */ |
94 | #define S626_RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */ |
95 | #define S626_RPS_STOP 0x50000000 /* STOP */ |
96 | #define S626_RPS_IRQ 0x60000000 /* IRQ */ |
97 | |
98 | #define S626_RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ |
99 | #define S626_RPS_INVERT 0x04000000 /* |
100 | * Test for negated |
101 | * semaphores. |
102 | */ |
103 | #define S626_RPS_DEBI 0x00000002 /* DEBI done */ |
104 | |
105 | #define S626_RPS_SIG0 0x00200000 /* |
106 | * RPS semaphore 0 |
107 | * (used by ADC). |
108 | */ |
109 | #define S626_RPS_SIG1 0x00400000 /* |
110 | * RPS semaphore 1 |
111 | * (used by DAC). |
112 | */ |
113 | #define S626_RPS_SIG2 0x00800000 /* |
114 | * RPS semaphore 2 |
115 | * (not used). |
116 | */ |
117 | #define S626_RPS_GPIO2 0x00080000 /* RPS GPIO2 */ |
118 | #define S626_RPS_GPIO3 0x00100000 /* RPS GPIO3 */ |
119 | |
120 | #define S626_RPS_SIGADC S626_RPS_SIG0 /* |
121 | * Trigger/status for |
122 | * ADC's RPS program. |
123 | */ |
124 | #define S626_RPS_SIGDAC S626_RPS_SIG1 /* |
125 | * Trigger/status for |
126 | * DAC's RPS program. |
127 | */ |
128 | |
129 | /* RPS clock parameters. */ |
130 | #define S626_RPSCLK_SCALAR 8 /* |
131 | * This is apparent ratio of |
132 | * PCI/RPS clks (undocumented!!). |
133 | */ |
134 | #define S626_RPSCLK_PER_US (33 / S626_RPSCLK_SCALAR) |
135 | /* |
136 | * Number of RPS clocks in one |
137 | * microsecond. |
138 | */ |
139 | |
140 | /* Event counter source addresses. */ |
141 | #define S626_SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ |
142 | |
143 | /* GPIO constants. */ |
144 | #define S626_GPIO_BASE 0x10004000 /* |
145 | * GPIO 0,2,3 = inputs, |
146 | * GPIO3 = IRQ; GPIO1 = out. |
147 | */ |
148 | #define S626_GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ |
149 | #define S626_GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ |
150 | |
151 | /* Primary Status Register (PSR) constants. */ |
152 | #define S626_PSR_DEBI_E 0x00040000 /* DEBI event flag. */ |
153 | #define S626_PSR_DEBI_S 0x00080000 /* DEBI status flag. */ |
154 | #define S626_PSR_A2_IN 0x00008000 /* |
155 | * Audio output DMA2 protection |
156 | * address reached. |
157 | */ |
158 | #define S626_PSR_AFOU 0x00000800 /* |
159 | * Audio FIFO under/overflow |
160 | * detected. |
161 | */ |
162 | #define S626_PSR_GPIO2 0x00000020 /* |
163 | * GPIO2 input pin: 0=AdcBusy, |
164 | * 1=AdcIdle. |
165 | */ |
166 | #define S626_PSR_EC0S 0x00000001 /* |
167 | * Event counter 0 threshold |
168 | * reached. |
169 | */ |
170 | |
171 | /* Secondary Status Register (SSR) constants. */ |
172 | #define S626_SSR_AF2_OUT 0x00000200 /* |
173 | * Audio 2 output FIFO |
174 | * under/overflow detected. |
175 | */ |
176 | |
177 | /* Master Control Register 1 (MC1) constants. */ |
178 | #define S626_MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ |
179 | #define S626_MC1_SHUTDOWN 0x3FFF0000 /* |
180 | * Shut down all MC1-controlled |
181 | * enables. |
182 | */ |
183 | |
184 | #define S626_MC1_ERPS1 0x2000 /* Enab/disable RPS task 1. */ |
185 | #define S626_MC1_ERPS0 0x1000 /* Enab/disable RPS task 0. */ |
186 | #define S626_MC1_DEBI 0x0800 /* Enab/disable DEBI pins. */ |
187 | #define S626_MC1_AUDIO 0x0200 /* Enab/disable audio port pins. */ |
188 | #define S626_MC1_I2C 0x0100 /* Enab/disable I2C interface. */ |
189 | #define S626_MC1_A2OUT 0x0008 /* Enab/disable transfer on A2 out. */ |
190 | #define S626_MC1_A2IN 0x0004 /* Enab/disable transfer on A2 in. */ |
191 | #define S626_MC1_A1IN 0x0001 /* Enab/disable transfer on A1 in. */ |
192 | |
193 | /* Master Control Register 2 (MC2) constants. */ |
194 | #define S626_MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */ |
195 | #define S626_MC2_UPLD_IIC 0x0001 /* Upload I2C. */ |
196 | #define S626_MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */ |
197 | #define S626_MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */ |
198 | #define S626_MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */ |
199 | |
200 | #define S626_MC2_ADC_RPS S626_MC2_RPSSIG0 /* ADC RPS busy. */ |
201 | #define S626_MC2_DAC_RPS S626_MC2_RPSSIG1 /* DAC RPS busy. */ |
202 | |
203 | /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */ |
204 | #define S626_P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */ |
205 | #define S626_P_DEBICFG 0x007C /* DEBI configuration. */ |
206 | #define S626_P_DEBICMD 0x0080 /* DEBI command. */ |
207 | #define S626_P_DEBIPAGE 0x0084 /* DEBI page. */ |
208 | #define S626_P_DEBIAD 0x0088 /* DEBI target address. */ |
209 | #define S626_P_I2CCTRL 0x008C /* I2C control. */ |
210 | #define S626_P_I2CSTAT 0x0090 /* I2C status. */ |
211 | #define S626_P_BASEA2_IN 0x00AC /* |
212 | * Audio input 2 base physical DMAbuf |
213 | * address. |
214 | */ |
215 | #define S626_P_PROTA2_IN 0x00B0 /* |
216 | * Audio input 2 physical DMAbuf |
217 | * protection address. |
218 | */ |
219 | #define S626_P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ |
220 | #define S626_P_BASEA2_OUT 0x00B8 /* |
221 | * Audio output 2 base physical DMAbuf |
222 | * address. |
223 | */ |
224 | #define S626_P_PROTA2_OUT 0x00BC /* |
225 | * Audio output 2 physical DMAbuf |
226 | * protection address. |
227 | */ |
228 | #define S626_P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ |
229 | #define S626_P_RPSPAGE0 0x00C4 /* RPS0 page. */ |
230 | #define S626_P_RPSPAGE1 0x00C8 /* RPS1 page. */ |
231 | #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */ |
232 | #define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */ |
233 | #define S626_P_IER 0x00DC /* Interrupt enable. */ |
234 | #define S626_P_GPIO 0x00E0 /* General-purpose I/O. */ |
235 | #define S626_P_EC1SSR 0x00E4 /* Event counter set 1 source select. */ |
236 | #define S626_P_ECT1R 0x00EC /* Event counter threshold set 1. */ |
237 | #define S626_P_ACON1 0x00F4 /* Audio control 1. */ |
238 | #define S626_P_ACON2 0x00F8 /* Audio control 2. */ |
239 | #define S626_P_MC1 0x00FC /* Master control 1. */ |
240 | #define S626_P_MC2 0x0100 /* Master control 2. */ |
241 | #define S626_P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */ |
242 | #define S626_P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */ |
243 | #define S626_P_ISR 0x010C /* Interrupt status. */ |
244 | #define S626_P_PSR 0x0110 /* Primary status. */ |
245 | #define S626_P_SSR 0x0114 /* Secondary status. */ |
246 | #define S626_P_EC1R 0x0118 /* Event counter set 1. */ |
247 | #define S626_P_ADP4 0x0138 /* |
248 | * Logical audio DMA pointer of audio |
249 | * input FIFO A2_IN. |
250 | */ |
251 | #define S626_P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ |
252 | #define S626_P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ |
253 | #define S626_P_TSL1 0x0180 /* Audio time slot list 1. */ |
254 | #define S626_P_TSL2 0x01C0 /* Audio time slot list 2. */ |
255 | |
256 | /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */ |
257 | /* Analog I/O registers: */ |
258 | #define S626_LP_DACPOL 0x0082 /* Write DAC polarity. */ |
259 | #define S626_LP_GSEL 0x0084 /* Write ADC gain. */ |
260 | #define S626_LP_ISEL 0x0086 /* Write ADC channel select. */ |
261 | |
262 | /* Digital I/O registers */ |
263 | #define S626_LP_RDDIN(x) (0x0040 + (x) * 0x10) /* R: digital input */ |
264 | #define S626_LP_WRINTSEL(x) (0x0042 + (x) * 0x10) /* W: int enable */ |
265 | #define S626_LP_WREDGSEL(x) (0x0044 + (x) * 0x10) /* W: edge selection */ |
266 | #define S626_LP_WRCAPSEL(x) (0x0046 + (x) * 0x10) /* W: capture enable */ |
267 | #define S626_LP_RDCAPFLG(x) (0x0048 + (x) * 0x10) /* R: edges captured */ |
268 | #define S626_LP_WRDOUT(x) (0x0048 + (x) * 0x10) /* W: digital output */ |
269 | #define S626_LP_RDINTSEL(x) (0x004a + (x) * 0x10) /* R: int enable */ |
270 | #define S626_LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */ |
271 | #define S626_LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */ |
272 | |
273 | /* Counter registers (read/write): 0A 1A 2A 0B 1B 2B */ |
274 | #define S626_LP_CRA(x) (0x0000 + (((x) % 3) * 0x4)) |
275 | #define S626_LP_CRB(x) (0x0002 + (((x) % 3) * 0x4)) |
276 | |
277 | /* Counter PreLoad (write) and Latch (read) Registers: 0A 1A 2A 0B 1B 2B */ |
278 | #define S626_LP_CNTR(x) (0x000c + (((x) < 3) ? 0x0 : 0x4) + \ |
279 | (((x) % 3) * 0x8)) |
280 | |
281 | /* Miscellaneous Registers (read/write): */ |
282 | #define S626_LP_MISC1 0x0088 /* Read/write Misc1. */ |
283 | #define S626_LP_WRMISC2 0x0090 /* Write Misc2. */ |
284 | #define S626_LP_RDMISC2 0x0082 /* Read Misc2. */ |
285 | |
286 | /* Bit masks for MISC1 register that are the same for reads and writes. */ |
287 | #define S626_MISC1_WENABLE 0x8000 /* |
288 | * enab writes to MISC2 (except Clear |
289 | * Watchdog bit). |
290 | */ |
291 | #define S626_MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ |
292 | #define S626_MISC1_EDCAP 0x1000 /* |
293 | * Enable edge capture on DIO chans |
294 | * specified by S626_LP_WRCAPSELx. |
295 | */ |
296 | #define S626_MISC1_NOEDCAP 0x0000 /* |
297 | * Disable edge capture on specified |
298 | * DIO chans. |
299 | */ |
300 | |
301 | /* Bit masks for MISC1 register reads. */ |
302 | #define S626_RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ |
303 | |
304 | /* Bit masks for MISC2 register writes. */ |
305 | #define S626_WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */ |
306 | #define S626_WRMISC2_CHARGE_ENABLE 0x4000 /* Enable battery trickle charging. */ |
307 | |
308 | /* Bit masks for MISC2 register that are the same for reads and writes. */ |
309 | #define S626_MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */ |
310 | #define S626_MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */ |
311 | #define S626_MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval select mask. */ |
312 | |
313 | /* Bit masks for ACON1 register. */ |
314 | #define S626_A2_RUN 0x40000000 /* Run A2 based on TSL2. */ |
315 | #define S626_A1_RUN 0x20000000 /* Run A1 based on TSL1. */ |
316 | #define S626_A1_SWAP 0x00200000 /* Use big-endian for A1. */ |
317 | #define S626_A2_SWAP 0x00100000 /* Use big-endian for A2. */ |
318 | #define S626_WS_MODES 0x00019999 /* |
319 | * WS0 = TSL1 trigger input, |
320 | * WS1-WS4 = CS* outputs. |
321 | */ |
322 | |
323 | #if (S626_PLATFORM == S626_INTEL) /* |
324 | * Base ACON1 config: always run |
325 | * A1 based on TSL1. |
326 | */ |
327 | #define S626_ACON1_BASE (S626_WS_MODES | S626_A1_RUN) |
328 | #elif S626_PLATFORM == S626_MOTOROLA |
329 | #define S626_ACON1_BASE \ |
330 | (S626_WS_MODES | S626_A1_RUN | S626_A1_SWAP | S626_A2_SWAP) |
331 | #endif |
332 | |
333 | #define S626_ACON1_ADCSTART S626_ACON1_BASE /* |
334 | * Start ADC: run A1 |
335 | * based on TSL1. |
336 | */ |
337 | #define S626_ACON1_DACSTART (S626_ACON1_BASE | S626_A2_RUN) |
338 | /* Start transmit to DAC: run A2 based on TSL2. */ |
339 | #define S626_ACON1_DACSTOP S626_ACON1_BASE /* Halt A2. */ |
340 | |
341 | /* Bit masks for ACON2 register. */ |
342 | #define S626_A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ |
343 | #define S626_A2_CLKSRC_X1 0x00800000 /* |
344 | * A2 bit rate = ACLK/1 |
345 | * (DACs). |
346 | */ |
347 | #define S626_A2_CLKSRC_X2 0x00C00000 /* |
348 | * A2 bit rate = ACLK/2 |
349 | * (DACs). |
350 | */ |
351 | #define S626_A2_CLKSRC_X4 0x01400000 /* |
352 | * A2 bit rate = ACLK/4 |
353 | * (DACs). |
354 | */ |
355 | #define S626_INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ |
356 | #define S626_BCLK2_OE 0x00040000 /* Enable BCLK2 (DACs). */ |
357 | #define S626_ACON2_XORMASK 0x000C0000 /* |
358 | * XOR mask for ACON2 |
359 | * active-low bits. |
360 | */ |
361 | |
362 | #define S626_ACON2_INIT (S626_ACON2_XORMASK ^ \ |
363 | (S626_A1_CLKSRC_BCLK1 | S626_A2_CLKSRC_X2 | \ |
364 | S626_INVERT_BCLK2 | S626_BCLK2_OE)) |
365 | |
366 | /* Bit masks for timeslot records. */ |
367 | #define S626_WS1 0x40000000 /* WS output to assert. */ |
368 | #define S626_WS2 0x20000000 |
369 | #define S626_WS3 0x10000000 |
370 | #define S626_WS4 0x08000000 |
371 | #define S626_RSD1 0x01000000 /* Shift A1 data in on SD1. */ |
372 | #define S626_SDW_A1 0x00800000 /* |
373 | * Store rcv'd char at next char |
374 | * slot of DWORD1 buffer. |
375 | */ |
376 | #define S626_SIB_A1 0x00400000 /* |
377 | * Store rcv'd char at next |
378 | * char slot of FB1 buffer. |
379 | */ |
380 | #define S626_SF_A1 0x00200000 /* |
381 | * Write unsigned long |
382 | * buffer to input FIFO. |
383 | */ |
384 | |
385 | /* Select parallel-to-serial converter's data source: */ |
386 | #define S626_XFIFO_0 0x00000000 /* Data fifo byte 0. */ |
387 | #define S626_XFIFO_1 0x00000010 /* Data fifo byte 1. */ |
388 | #define S626_XFIFO_2 0x00000020 /* Data fifo byte 2. */ |
389 | #define S626_XFIFO_3 0x00000030 /* Data fifo byte 3. */ |
390 | #define S626_XFB0 0x00000040 /* FB_BUFFER byte 0. */ |
391 | #define S626_XFB1 0x00000050 /* FB_BUFFER byte 1. */ |
392 | #define S626_XFB2 0x00000060 /* FB_BUFFER byte 2. */ |
393 | #define S626_XFB3 0x00000070 /* FB_BUFFER byte 3. */ |
394 | #define S626_SIB_A2 0x00000200 /* |
395 | * Store next dword from A2's |
396 | * input shifter to FB2 |
397 | * buffer. |
398 | */ |
399 | #define S626_SF_A2 0x00000100 /* |
400 | * Store next dword from A2's |
401 | * input shifter to its input |
402 | * fifo. |
403 | */ |
404 | #define S626_LF_A2 0x00000080 /* |
405 | * Load next dword from A2's |
406 | * output fifo into its |
407 | * output dword buffer. |
408 | */ |
409 | #define S626_XSD2 0x00000008 /* Shift data out on SD2. */ |
410 | #define S626_RSD3 0x00001800 /* Shift data in on SD3. */ |
411 | #define S626_RSD2 0x00001000 /* Shift data in on SD2. */ |
412 | #define S626_LOW_A2 0x00000002 /* |
413 | * Drive last SD low for 7 clks, |
414 | * then tri-state. |
415 | */ |
416 | #define S626_EOS 0x00000001 /* End of superframe. */ |
417 | |
418 | /* I2C configuration constants. */ |
419 | #define S626_I2C_CLKSEL 0x0400 /* |
420 | * I2C bit rate = |
421 | * PCIclk/480 = 68.75 KHz. |
422 | */ |
423 | #define S626_I2C_BITRATE 68.75 /* |
424 | * I2C bus data bit rate |
425 | * (determined by |
426 | * S626_I2C_CLKSEL) in KHz. |
427 | */ |
428 | #define S626_I2C_WRTIME 15.0 /* |
429 | * Worst case time, in msec, |
430 | * for EEPROM internal write |
431 | * op. |
432 | */ |
433 | |
434 | /* I2C manifest constants. */ |
435 | |
436 | /* Max retries to wait for EEPROM write. */ |
437 | #define S626_I2C_RETRIES (S626_I2C_WRTIME * S626_I2C_BITRATE / 9.0) |
438 | #define S626_I2C_ERR 0x0002 /* I2C control/status flag ERROR. */ |
439 | #define S626_I2C_BUSY 0x0001 /* I2C control/status flag BUSY. */ |
440 | #define S626_I2C_ABORT 0x0080 /* I2C status flag ABORT. */ |
441 | #define S626_I2C_ATTRSTART 0x3 /* I2C attribute START. */ |
442 | #define S626_I2C_ATTRCONT 0x2 /* I2C attribute CONT. */ |
443 | #define S626_I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */ |
444 | #define S626_I2C_ATTRNOP 0x0 /* I2C attribute NOP. */ |
445 | |
446 | /* Code macros used for constructing I2C command bytes. */ |
447 | #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) |
448 | #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) |
449 | #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) |
450 | |
451 | /* DEBI command constants. */ |
452 | #define S626_DEBI_CMD_SIZE16 (2 << 17) /* |
453 | * Transfer size is always |
454 | * 2 bytes. |
455 | */ |
456 | #define S626_DEBI_CMD_READ 0x00010000 /* Read operation. */ |
457 | #define S626_DEBI_CMD_WRITE 0x00000000 /* Write operation. */ |
458 | |
459 | /* Read immediate 2 bytes. */ |
460 | #define S626_DEBI_CMD_RDWORD (S626_DEBI_CMD_READ | S626_DEBI_CMD_SIZE16) |
461 | |
462 | /* Write immediate 2 bytes. */ |
463 | #define S626_DEBI_CMD_WRWORD (S626_DEBI_CMD_WRITE | S626_DEBI_CMD_SIZE16) |
464 | |
465 | /* DEBI configuration constants. */ |
466 | #define S626_DEBI_CFG_XIRQ_EN 0x80000000 /* |
467 | * Enable external interrupt |
468 | * on GPIO3. |
469 | */ |
470 | #define S626_DEBI_CFG_XRESUME 0x40000000 /* Resume block */ |
471 | /* |
472 | * Transfer when XIRQ |
473 | * deasserted. |
474 | */ |
475 | #define S626_DEBI_CFG_TOQ 0x03C00000 /* Timeout (15 PCI cycles). */ |
476 | #define S626_DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ |
477 | |
478 | /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ |
479 | #define S626_DEBI_CFG_TOUT_BIT 22 /* |
480 | * Finish DEBI cycle after this many |
481 | * clocks. |
482 | */ |
483 | |
484 | /* 2-bit field that specifies Endian byte lane steering: */ |
485 | #define S626_DEBI_CFG_SWAP_NONE 0x00000000 /* |
486 | * Straight - don't swap any |
487 | * bytes (Intel). |
488 | */ |
489 | #define S626_DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ |
490 | #define S626_DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ |
491 | #define S626_DEBI_CFG_SLAVE16 0x00080000 /* |
492 | * Slave is able to serve |
493 | * 16-bit cycles. |
494 | */ |
495 | #define S626_DEBI_CFG_INC 0x00040000 /* |
496 | * Enable address increment |
497 | * for block transfers. |
498 | */ |
499 | #define S626_DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ |
500 | #define S626_DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ |
501 | |
502 | #if S626_PLATFORM == S626_INTEL |
503 | |
504 | #define S626_DEBI_TOUT 7 /* |
505 | * Wait 7 PCI clocks (212 ns) before |
506 | * polling RDY. |
507 | */ |
508 | |
509 | /* Intel byte lane steering (pass through all byte lanes). */ |
510 | #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_NONE |
511 | |
512 | #elif S626_PLATFORM == S626_MOTOROLA |
513 | |
514 | #define S626_DEBI_TOUT 15 /* |
515 | * Wait 15 PCI clocks (454 ns) maximum |
516 | * before timing out. |
517 | */ |
518 | |
519 | /* Motorola byte lane steering. */ |
520 | #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_2 |
521 | |
522 | #endif |
523 | |
524 | /* DEBI page table constants. */ |
525 | #define S626_DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */ |
526 | |
527 | /* ******* EXTRA FROM OTHER SENSORAY * .h ******* */ |
528 | |
529 | /* LoadSrc values: */ |
530 | #define S626_LOADSRC_INDX 0 /* Preload core in response to Index. */ |
531 | #define S626_LOADSRC_OVER 1 /* |
532 | * Preload core in response to |
533 | * Overflow. |
534 | */ |
535 | #define S626_LOADSRCB_OVERA 2 /* |
536 | * Preload B core in response to |
537 | * A Overflow. |
538 | */ |
539 | #define S626_LOADSRC_NONE 3 /* Never preload core. */ |
540 | |
541 | /* IntSrc values: */ |
542 | #define S626_INTSRC_NONE 0 /* Interrupts disabled. */ |
543 | #define S626_INTSRC_OVER 1 /* Interrupt on Overflow. */ |
544 | #define S626_INTSRC_INDX 2 /* Interrupt on Index. */ |
545 | #define S626_INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */ |
546 | |
547 | /* LatchSrc values: */ |
548 | #define S626_LATCHSRC_AB_READ 0 /* Latch on read. */ |
549 | #define S626_LATCHSRC_A_INDXA 1 /* Latch A on A Index. */ |
550 | #define S626_LATCHSRC_B_INDXB 2 /* Latch B on B Index. */ |
551 | #define S626_LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */ |
552 | |
553 | /* IndxSrc values: */ |
554 | #define S626_INDXSRC_ENCODER 0 /* Encoder. */ |
555 | #define S626_INDXSRC_DIGIN 1 /* Digital inputs. */ |
556 | #define S626_INDXSRC_SOFT 2 /* S/w controlled by IndxPol bit. */ |
557 | #define S626_INDXSRC_DISABLED 3 /* Index disabled. */ |
558 | |
559 | /* IndxPol values: */ |
560 | #define S626_INDXPOL_POS 0 /* Index input is active high. */ |
561 | #define S626_INDXPOL_NEG 1 /* Index input is active low. */ |
562 | |
563 | /* Logical encoder mode values: */ |
564 | #define S626_ENCMODE_COUNTER 0 /* Counter mode. */ |
565 | #define S626_ENCMODE_TIMER 2 /* Timer mode. */ |
566 | #define S626_ENCMODE_EXTENDER 3 /* Extender mode. */ |
567 | |
568 | /* Physical CntSrc values (for Counter A source and Counter B source): */ |
569 | #define S626_CNTSRC_ENCODER 0 /* Encoder */ |
570 | #define S626_CNTSRC_DIGIN 1 /* Digital inputs */ |
571 | #define S626_CNTSRC_SYSCLK 2 /* System clock up */ |
572 | #define S626_CNTSRC_SYSCLK_DOWN 3 /* System clock down */ |
573 | |
574 | /* ClkPol values: */ |
575 | #define S626_CLKPOL_POS 0 /* |
576 | * Counter/Extender clock is |
577 | * active high. |
578 | */ |
579 | #define S626_CLKPOL_NEG 1 /* |
580 | * Counter/Extender clock is |
581 | * active low. |
582 | */ |
583 | #define S626_CNTDIR_UP 0 /* Timer counts up. */ |
584 | #define S626_CNTDIR_DOWN 1 /* Timer counts down. */ |
585 | |
586 | /* ClkEnab values: */ |
587 | #define S626_CLKENAB_ALWAYS 0 /* Clock always enabled. */ |
588 | #define S626_CLKENAB_INDEX 1 /* Clock is enabled by index. */ |
589 | |
590 | /* ClkMult values: */ |
591 | #define S626_CLKMULT_4X 0 /* 4x clock multiplier. */ |
592 | #define S626_CLKMULT_2X 1 /* 2x clock multiplier. */ |
593 | #define S626_CLKMULT_1X 2 /* 1x clock multiplier. */ |
594 | #define S626_CLKMULT_SPECIAL 3 /* Special clock multiplier value. */ |
595 | |
596 | /* Sanity-check limits for parameters. */ |
597 | |
598 | #define S626_NUM_COUNTERS 6 /* |
599 | * Maximum valid counter |
600 | * logical channel number. |
601 | */ |
602 | #define S626_NUM_INTSOURCES 4 |
603 | #define S626_NUM_LATCHSOURCES 4 |
604 | #define S626_NUM_CLKMULTS 4 |
605 | #define S626_NUM_CLKSOURCES 4 |
606 | #define S626_NUM_CLKPOLS 2 |
607 | #define S626_NUM_INDEXPOLS 2 |
608 | #define S626_NUM_INDEXSOURCES 2 |
609 | #define S626_NUM_LOADTRIGS 4 |
610 | |
611 | /* General macros for manipulating bitfields: */ |
612 | #define S626_MAKE(x, w, p) (((x) & ((1 << (w)) - 1)) << (p)) |
613 | #define S626_UNMAKE(v, w, p) (((v) >> (p)) & ((1 << (w)) - 1)) |
614 | |
615 | /* Bit field positions in CRA: */ |
616 | #define S626_CRABIT_INDXSRC_B 14 /* B index source. */ |
617 | #define S626_CRABIT_CNTSRC_B 12 /* B counter source. */ |
618 | #define S626_CRABIT_INDXPOL_A 11 /* A index polarity. */ |
619 | #define S626_CRABIT_LOADSRC_A 9 /* A preload trigger. */ |
620 | #define S626_CRABIT_CLKMULT_A 7 /* A clock multiplier. */ |
621 | #define S626_CRABIT_INTSRC_A 5 /* A interrupt source. */ |
622 | #define S626_CRABIT_CLKPOL_A 4 /* A clock polarity. */ |
623 | #define S626_CRABIT_INDXSRC_A 2 /* A index source. */ |
624 | #define S626_CRABIT_CNTSRC_A 0 /* A counter source. */ |
625 | |
626 | /* Bit field widths in CRA: */ |
627 | #define S626_CRAWID_INDXSRC_B 2 |
628 | #define S626_CRAWID_CNTSRC_B 2 |
629 | #define S626_CRAWID_INDXPOL_A 1 |
630 | #define S626_CRAWID_LOADSRC_A 2 |
631 | #define S626_CRAWID_CLKMULT_A 2 |
632 | #define S626_CRAWID_INTSRC_A 2 |
633 | #define S626_CRAWID_CLKPOL_A 1 |
634 | #define S626_CRAWID_INDXSRC_A 2 |
635 | #define S626_CRAWID_CNTSRC_A 2 |
636 | |
637 | /* Bit field masks for CRA: */ |
638 | #define S626_CRAMSK_INDXSRC_B S626_SET_CRA_INDXSRC_B(~0) |
639 | #define S626_CRAMSK_CNTSRC_B S626_SET_CRA_CNTSRC_B(~0) |
640 | #define S626_CRAMSK_INDXPOL_A S626_SET_CRA_INDXPOL_A(~0) |
641 | #define S626_CRAMSK_LOADSRC_A S626_SET_CRA_LOADSRC_A(~0) |
642 | #define S626_CRAMSK_CLKMULT_A S626_SET_CRA_CLKMULT_A(~0) |
643 | #define S626_CRAMSK_INTSRC_A S626_SET_CRA_INTSRC_A(~0) |
644 | #define S626_CRAMSK_CLKPOL_A S626_SET_CRA_CLKPOL_A(~0) |
645 | #define S626_CRAMSK_INDXSRC_A S626_SET_CRA_INDXSRC_A(~0) |
646 | #define S626_CRAMSK_CNTSRC_A S626_SET_CRA_CNTSRC_A(~0) |
647 | |
648 | /* Construct parts of the CRA value: */ |
649 | #define S626_SET_CRA_INDXSRC_B(x) \ |
650 | S626_MAKE((x), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B) |
651 | #define S626_SET_CRA_CNTSRC_B(x) \ |
652 | S626_MAKE((x), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B) |
653 | #define S626_SET_CRA_INDXPOL_A(x) \ |
654 | S626_MAKE((x), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A) |
655 | #define S626_SET_CRA_LOADSRC_A(x) \ |
656 | S626_MAKE((x), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A) |
657 | #define S626_SET_CRA_CLKMULT_A(x) \ |
658 | S626_MAKE((x), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A) |
659 | #define S626_SET_CRA_INTSRC_A(x) \ |
660 | S626_MAKE((x), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A) |
661 | #define S626_SET_CRA_CLKPOL_A(x) \ |
662 | S626_MAKE((x), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A) |
663 | #define S626_SET_CRA_INDXSRC_A(x) \ |
664 | S626_MAKE((x), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A) |
665 | #define S626_SET_CRA_CNTSRC_A(x) \ |
666 | S626_MAKE((x), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A) |
667 | |
668 | /* Extract parts of the CRA value: */ |
669 | #define S626_GET_CRA_INDXSRC_B(v) \ |
670 | S626_UNMAKE((v), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B) |
671 | #define S626_GET_CRA_CNTSRC_B(v) \ |
672 | S626_UNMAKE((v), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B) |
673 | #define S626_GET_CRA_INDXPOL_A(v) \ |
674 | S626_UNMAKE((v), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A) |
675 | #define S626_GET_CRA_LOADSRC_A(v) \ |
676 | S626_UNMAKE((v), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A) |
677 | #define S626_GET_CRA_CLKMULT_A(v) \ |
678 | S626_UNMAKE((v), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A) |
679 | #define S626_GET_CRA_INTSRC_A(v) \ |
680 | S626_UNMAKE((v), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A) |
681 | #define S626_GET_CRA_CLKPOL_A(v) \ |
682 | S626_UNMAKE((v), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A) |
683 | #define S626_GET_CRA_INDXSRC_A(v) \ |
684 | S626_UNMAKE((v), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A) |
685 | #define S626_GET_CRA_CNTSRC_A(v) \ |
686 | S626_UNMAKE((v), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A) |
687 | |
688 | /* Bit field positions in CRB: */ |
689 | #define S626_CRBBIT_INTRESETCMD 15 /* (w) Interrupt reset command. */ |
690 | #define S626_CRBBIT_CNTDIR_B 15 /* (r) B counter direction. */ |
691 | #define S626_CRBBIT_INTRESET_B 14 /* (w) B interrupt reset enable. */ |
692 | #define S626_CRBBIT_OVERDO_A 14 /* (r) A overflow routed to dig. out. */ |
693 | #define S626_CRBBIT_INTRESET_A 13 /* (w) A interrupt reset enable. */ |
694 | #define S626_CRBBIT_OVERDO_B 13 /* (r) B overflow routed to dig. out. */ |
695 | #define S626_CRBBIT_CLKENAB_A 12 /* A clock enable. */ |
696 | #define S626_CRBBIT_INTSRC_B 10 /* B interrupt source. */ |
697 | #define S626_CRBBIT_LATCHSRC 8 /* A/B latch source. */ |
698 | #define S626_CRBBIT_LOADSRC_B 6 /* B preload trigger. */ |
699 | #define S626_CRBBIT_CLEAR_B 7 /* B cleared when A overflows. */ |
700 | #define S626_CRBBIT_CLKMULT_B 3 /* B clock multiplier. */ |
701 | #define S626_CRBBIT_CLKENAB_B 2 /* B clock enable. */ |
702 | #define S626_CRBBIT_INDXPOL_B 1 /* B index polarity. */ |
703 | #define S626_CRBBIT_CLKPOL_B 0 /* B clock polarity. */ |
704 | |
705 | /* Bit field widths in CRB: */ |
706 | #define S626_CRBWID_INTRESETCMD 1 |
707 | #define S626_CRBWID_CNTDIR_B 1 |
708 | #define S626_CRBWID_INTRESET_B 1 |
709 | #define S626_CRBWID_OVERDO_A 1 |
710 | #define S626_CRBWID_INTRESET_A 1 |
711 | #define S626_CRBWID_OVERDO_B 1 |
712 | #define S626_CRBWID_CLKENAB_A 1 |
713 | #define S626_CRBWID_INTSRC_B 2 |
714 | #define S626_CRBWID_LATCHSRC 2 |
715 | #define S626_CRBWID_LOADSRC_B 2 |
716 | #define S626_CRBWID_CLEAR_B 1 |
717 | #define S626_CRBWID_CLKMULT_B 2 |
718 | #define S626_CRBWID_CLKENAB_B 1 |
719 | #define S626_CRBWID_INDXPOL_B 1 |
720 | #define S626_CRBWID_CLKPOL_B 1 |
721 | |
722 | /* Bit field masks for CRB: */ |
723 | #define S626_CRBMSK_INTRESETCMD S626_SET_CRB_INTRESETCMD(~0) /* (w) */ |
724 | #define S626_CRBMSK_CNTDIR_B S626_CRBMSK_INTRESETCMD /* (r) */ |
725 | #define S626_CRBMSK_INTRESET_B S626_SET_CRB_INTRESET_B(~0) /* (w) */ |
726 | #define S626_CRBMSK_OVERDO_A S626_CRBMSK_INTRESET_B /* (r) */ |
727 | #define S626_CRBMSK_INTRESET_A S626_SET_CRB_INTRESET_A(~0) /* (w) */ |
728 | #define S626_CRBMSK_OVERDO_B S626_CRBMSK_INTRESET_A /* (r) */ |
729 | #define S626_CRBMSK_CLKENAB_A S626_SET_CRB_CLKENAB_A(~0) |
730 | #define S626_CRBMSK_INTSRC_B S626_SET_CRB_INTSRC_B(~0) |
731 | #define S626_CRBMSK_LATCHSRC S626_SET_CRB_LATCHSRC(~0) |
732 | #define S626_CRBMSK_LOADSRC_B S626_SET_CRB_LOADSRC_B(~0) |
733 | #define S626_CRBMSK_CLEAR_B S626_SET_CRB_CLEAR_B(~0) |
734 | #define S626_CRBMSK_CLKMULT_B S626_SET_CRB_CLKMULT_B(~0) |
735 | #define S626_CRBMSK_CLKENAB_B S626_SET_CRB_CLKENAB_B(~0) |
736 | #define S626_CRBMSK_INDXPOL_B S626_SET_CRB_INDXPOL_B(~0) |
737 | #define S626_CRBMSK_CLKPOL_B S626_SET_CRB_CLKPOL_B(~0) |
738 | |
739 | /* Interrupt reset control bits. */ |
740 | #define S626_CRBMSK_INTCTRL (S626_CRBMSK_INTRESETCMD | \ |
741 | S626_CRBMSK_INTRESET_A | \ |
742 | S626_CRBMSK_INTRESET_B) |
743 | |
744 | /* Construct parts of the CRB value: */ |
745 | #define S626_SET_CRB_INTRESETCMD(x) \ |
746 | S626_MAKE((x), S626_CRBWID_INTRESETCMD, S626_CRBBIT_INTRESETCMD) |
747 | #define S626_SET_CRB_INTRESET_B(x) \ |
748 | S626_MAKE((x), S626_CRBWID_INTRESET_B, S626_CRBBIT_INTRESET_B) |
749 | #define S626_SET_CRB_INTRESET_A(x) \ |
750 | S626_MAKE((x), S626_CRBWID_INTRESET_A, S626_CRBBIT_INTRESET_A) |
751 | #define S626_SET_CRB_CLKENAB_A(x) \ |
752 | S626_MAKE((x), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A) |
753 | #define S626_SET_CRB_INTSRC_B(x) \ |
754 | S626_MAKE((x), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B) |
755 | #define S626_SET_CRB_LATCHSRC(x) \ |
756 | S626_MAKE((x), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC) |
757 | #define S626_SET_CRB_LOADSRC_B(x) \ |
758 | S626_MAKE((x), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B) |
759 | #define S626_SET_CRB_CLEAR_B(x) \ |
760 | S626_MAKE((x), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B) |
761 | #define S626_SET_CRB_CLKMULT_B(x) \ |
762 | S626_MAKE((x), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B) |
763 | #define S626_SET_CRB_CLKENAB_B(x) \ |
764 | S626_MAKE((x), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B) |
765 | #define S626_SET_CRB_INDXPOL_B(x) \ |
766 | S626_MAKE((x), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B) |
767 | #define S626_SET_CRB_CLKPOL_B(x) \ |
768 | S626_MAKE((x), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B) |
769 | |
770 | /* Extract parts of the CRB value: */ |
771 | #define S626_GET_CRB_CNTDIR_B(v) \ |
772 | S626_UNMAKE((v), S626_CRBWID_CNTDIR_B, S626_CRBBIT_CNTDIR_B) |
773 | #define S626_GET_CRB_OVERDO_A(v) \ |
774 | S626_UNMAKE((v), S626_CRBWID_OVERDO_A, S626_CRBBIT_OVERDO_A) |
775 | #define S626_GET_CRB_OVERDO_B(v) \ |
776 | S626_UNMAKE((v), S626_CRBWID_OVERDO_B, S626_CRBBIT_OVERDO_B) |
777 | #define S626_GET_CRB_CLKENAB_A(v) \ |
778 | S626_UNMAKE((v), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A) |
779 | #define S626_GET_CRB_INTSRC_B(v) \ |
780 | S626_UNMAKE((v), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B) |
781 | #define S626_GET_CRB_LATCHSRC(v) \ |
782 | S626_UNMAKE((v), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC) |
783 | #define S626_GET_CRB_LOADSRC_B(v) \ |
784 | S626_UNMAKE((v), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B) |
785 | #define S626_GET_CRB_CLEAR_B(v) \ |
786 | S626_UNMAKE((v), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B) |
787 | #define S626_GET_CRB_CLKMULT_B(v) \ |
788 | S626_UNMAKE((v), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B) |
789 | #define S626_GET_CRB_CLKENAB_B(v) \ |
790 | S626_UNMAKE((v), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B) |
791 | #define S626_GET_CRB_INDXPOL_B(v) \ |
792 | S626_UNMAKE((v), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B) |
793 | #define S626_GET_CRB_CLKPOL_B(v) \ |
794 | S626_UNMAKE((v), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B) |
795 | |
796 | /* Bit field positions for standardized SETUP structure: */ |
797 | #define S626_STDBIT_INTSRC 13 |
798 | #define S626_STDBIT_LATCHSRC 11 |
799 | #define S626_STDBIT_LOADSRC 9 |
800 | #define S626_STDBIT_INDXSRC 7 |
801 | #define S626_STDBIT_INDXPOL 6 |
802 | #define S626_STDBIT_ENCMODE 4 |
803 | #define S626_STDBIT_CLKPOL 3 |
804 | #define S626_STDBIT_CLKMULT 1 |
805 | #define S626_STDBIT_CLKENAB 0 |
806 | |
807 | /* Bit field widths for standardized SETUP structure: */ |
808 | #define S626_STDWID_INTSRC 2 |
809 | #define S626_STDWID_LATCHSRC 2 |
810 | #define S626_STDWID_LOADSRC 2 |
811 | #define S626_STDWID_INDXSRC 2 |
812 | #define S626_STDWID_INDXPOL 1 |
813 | #define S626_STDWID_ENCMODE 2 |
814 | #define S626_STDWID_CLKPOL 1 |
815 | #define S626_STDWID_CLKMULT 2 |
816 | #define S626_STDWID_CLKENAB 1 |
817 | |
818 | /* Bit field masks for standardized SETUP structure: */ |
819 | #define S626_STDMSK_INTSRC S626_SET_STD_INTSRC(~0) |
820 | #define S626_STDMSK_LATCHSRC S626_SET_STD_LATCHSRC(~0) |
821 | #define S626_STDMSK_LOADSRC S626_SET_STD_LOADSRC(~0) |
822 | #define S626_STDMSK_INDXSRC S626_SET_STD_INDXSRC(~0) |
823 | #define S626_STDMSK_INDXPOL S626_SET_STD_INDXPOL(~0) |
824 | #define S626_STDMSK_ENCMODE S626_SET_STD_ENCMODE(~0) |
825 | #define S626_STDMSK_CLKPOL S626_SET_STD_CLKPOL(~0) |
826 | #define S626_STDMSK_CLKMULT S626_SET_STD_CLKMULT(~0) |
827 | #define S626_STDMSK_CLKENAB S626_SET_STD_CLKENAB(~0) |
828 | |
829 | /* Construct parts of standardized SETUP structure: */ |
830 | #define S626_SET_STD_INTSRC(x) \ |
831 | S626_MAKE((x), S626_STDWID_INTSRC, S626_STDBIT_INTSRC) |
832 | #define S626_SET_STD_LATCHSRC(x) \ |
833 | S626_MAKE((x), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC) |
834 | #define S626_SET_STD_LOADSRC(x) \ |
835 | S626_MAKE((x), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC) |
836 | #define S626_SET_STD_INDXSRC(x) \ |
837 | S626_MAKE((x), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC) |
838 | #define S626_SET_STD_INDXPOL(x) \ |
839 | S626_MAKE((x), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL) |
840 | #define S626_SET_STD_ENCMODE(x) \ |
841 | S626_MAKE((x), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE) |
842 | #define S626_SET_STD_CLKPOL(x) \ |
843 | S626_MAKE((x), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL) |
844 | #define S626_SET_STD_CLKMULT(x) \ |
845 | S626_MAKE((x), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT) |
846 | #define S626_SET_STD_CLKENAB(x) \ |
847 | S626_MAKE((x), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB) |
848 | |
849 | /* Extract parts of standardized SETUP structure: */ |
850 | #define S626_GET_STD_INTSRC(v) \ |
851 | S626_UNMAKE((v), S626_STDWID_INTSRC, S626_STDBIT_INTSRC) |
852 | #define S626_GET_STD_LATCHSRC(v) \ |
853 | S626_UNMAKE((v), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC) |
854 | #define S626_GET_STD_LOADSRC(v) \ |
855 | S626_UNMAKE((v), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC) |
856 | #define S626_GET_STD_INDXSRC(v) \ |
857 | S626_UNMAKE((v), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC) |
858 | #define S626_GET_STD_INDXPOL(v) \ |
859 | S626_UNMAKE((v), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL) |
860 | #define S626_GET_STD_ENCMODE(v) \ |
861 | S626_UNMAKE((v), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE) |
862 | #define S626_GET_STD_CLKPOL(v) \ |
863 | S626_UNMAKE((v), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL) |
864 | #define S626_GET_STD_CLKMULT(v) \ |
865 | S626_UNMAKE((v), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT) |
866 | #define S626_GET_STD_CLKENAB(v) \ |
867 | S626_UNMAKE((v), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB) |
868 | |
869 | #endif |
870 | |