1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * comedi/drivers/s626.c |
4 | * Sensoray s626 Comedi driver |
5 | * |
6 | * COMEDI - Linux Control and Measurement Device Interface |
7 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> |
8 | * |
9 | * Based on Sensoray Model 626 Linux driver Version 0.2 |
10 | * Copyright (C) 2002-2004 Sensoray Co., Inc. |
11 | */ |
12 | |
13 | /* |
14 | * Driver: s626 |
15 | * Description: Sensoray 626 driver |
16 | * Devices: [Sensoray] 626 (s626) |
17 | * Authors: Gianluca Palli <gpalli@deis.unibo.it>, |
18 | * Updated: Fri, 15 Feb 2008 10:28:42 +0000 |
19 | * Status: experimental |
20 | |
21 | * Configuration options: not applicable, uses PCI auto config |
22 | |
23 | * INSN_CONFIG instructions: |
24 | * analog input: |
25 | * none |
26 | * |
27 | * analog output: |
28 | * none |
29 | * |
30 | * digital channel: |
31 | * s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels |
32 | * supported configuration options: |
33 | * INSN_CONFIG_DIO_QUERY |
34 | * COMEDI_INPUT |
35 | * COMEDI_OUTPUT |
36 | * |
37 | * encoder: |
38 | * Every channel must be configured before reading. |
39 | * |
40 | * Example code |
41 | * |
42 | * insn.insn=INSN_CONFIG; //configuration instruction |
43 | * insn.n=1; //number of operation (must be 1) |
44 | * insn.data=&initialvalue; //initial value loaded into encoder |
45 | * //during configuration |
46 | * insn.subdev=5; //encoder subdevice |
47 | * insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel |
48 | * //to configure |
49 | * |
50 | * comedi_do_insn(cf,&insn); //executing configuration |
51 | */ |
52 | |
53 | #include <linux/module.h> |
54 | #include <linux/delay.h> |
55 | #include <linux/interrupt.h> |
56 | #include <linux/kernel.h> |
57 | #include <linux/types.h> |
58 | #include <linux/comedi/comedi_pci.h> |
59 | |
60 | #include "s626.h" |
61 | |
62 | struct s626_buffer_dma { |
63 | dma_addr_t physical_base; |
64 | void *logical_base; |
65 | }; |
66 | |
67 | /** |
68 | * struct s626_private - Working data for s626 driver. |
69 | * @ai_cmd_running: non-zero if ai_cmd is running. |
70 | * @ai_sample_timer: time between samples in units of the timer. |
71 | * @ai_convert_count: conversion counter. |
72 | * @ai_convert_timer: time between conversion in units of the timer. |
73 | * @counter_int_enabs: counter interrupt enable mask for MISC2 register. |
74 | * @adc_items: number of items in ADC poll list. |
75 | * @rps_buf: DMA buffer used to hold ADC (RPS1) program. |
76 | * @ana_buf: DMA buffer used to receive ADC data and hold DAC data. |
77 | * @dac_wbuf: pointer to logical adrs of DMA buffer used to hold DAC data. |
78 | * @dacpol: image of DAC polarity register. |
79 | * @trim_setpoint: images of TrimDAC setpoints. |
80 | * @i2c_adrs: I2C device address for onboard EEPROM (board rev dependent) |
81 | */ |
82 | struct s626_private { |
83 | u8 ai_cmd_running; |
84 | unsigned int ai_sample_timer; |
85 | int ai_convert_count; |
86 | unsigned int ai_convert_timer; |
87 | u16 counter_int_enabs; |
88 | u8 adc_items; |
89 | struct s626_buffer_dma rps_buf; |
90 | struct s626_buffer_dma ana_buf; |
91 | u32 *dac_wbuf; |
92 | u16 dacpol; |
93 | u8 trim_setpoint[12]; |
94 | u32 i2c_adrs; |
95 | }; |
96 | |
97 | /* Counter overflow/index event flag masks for RDMISC2. */ |
98 | #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4))) |
99 | #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10))) |
100 | |
101 | /* |
102 | * Enable/disable a function or test status bit(s) that are accessed |
103 | * through Main Control Registers 1 or 2. |
104 | */ |
105 | static void s626_mc_enable(struct comedi_device *dev, |
106 | unsigned int cmd, unsigned int reg) |
107 | { |
108 | unsigned int val = (cmd << 16) | cmd; |
109 | |
110 | writel(val, addr: dev->mmio + reg); |
111 | } |
112 | |
113 | static void s626_mc_disable(struct comedi_device *dev, |
114 | unsigned int cmd, unsigned int reg) |
115 | { |
116 | writel(val: cmd << 16, addr: dev->mmio + reg); |
117 | } |
118 | |
119 | static bool s626_mc_test(struct comedi_device *dev, |
120 | unsigned int cmd, unsigned int reg) |
121 | { |
122 | unsigned int val; |
123 | |
124 | val = readl(addr: dev->mmio + reg); |
125 | |
126 | return (val & cmd) ? true : false; |
127 | } |
128 | |
129 | #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4) |
130 | |
131 | /* Write a time slot control record to TSL2. */ |
132 | #define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2)) |
133 | |
134 | static const struct comedi_lrange s626_range_table = { |
135 | 2, { |
136 | BIP_RANGE(5), |
137 | BIP_RANGE(10) |
138 | } |
139 | }; |
140 | |
141 | /* |
142 | * Execute a DEBI transfer. This must be called from within a critical section. |
143 | */ |
144 | static void s626_debi_transfer(struct comedi_device *dev) |
145 | { |
146 | static const int timeout = 10000; |
147 | int i; |
148 | |
149 | /* Initiate upload of shadow RAM to DEBI control register */ |
150 | s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2); |
151 | |
152 | /* |
153 | * Wait for completion of upload from shadow RAM to |
154 | * DEBI control register. |
155 | */ |
156 | for (i = 0; i < timeout; i++) { |
157 | if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2)) |
158 | break; |
159 | udelay(1); |
160 | } |
161 | if (i == timeout) |
162 | dev_err(dev->class_dev, |
163 | "Timeout while uploading to DEBI control register\n" ); |
164 | |
165 | /* Wait until DEBI transfer is done */ |
166 | for (i = 0; i < timeout; i++) { |
167 | if (!(readl(addr: dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S)) |
168 | break; |
169 | udelay(1); |
170 | } |
171 | if (i == timeout) |
172 | dev_err(dev->class_dev, "DEBI transfer timeout\n" ); |
173 | } |
174 | |
175 | /* |
176 | * Read a value from a gate array register. |
177 | */ |
178 | static u16 s626_debi_read(struct comedi_device *dev, u16 addr) |
179 | { |
180 | /* Set up DEBI control register value in shadow RAM */ |
181 | writel(S626_DEBI_CMD_RDWORD | addr, addr: dev->mmio + S626_P_DEBICMD); |
182 | |
183 | /* Execute the DEBI transfer. */ |
184 | s626_debi_transfer(dev); |
185 | |
186 | return readl(addr: dev->mmio + S626_P_DEBIAD); |
187 | } |
188 | |
189 | /* |
190 | * Write a value to a gate array register. |
191 | */ |
192 | static void s626_debi_write(struct comedi_device *dev, u16 addr, |
193 | u16 wdata) |
194 | { |
195 | /* Set up DEBI control register value in shadow RAM */ |
196 | writel(S626_DEBI_CMD_WRWORD | addr, addr: dev->mmio + S626_P_DEBICMD); |
197 | writel(val: wdata, addr: dev->mmio + S626_P_DEBIAD); |
198 | |
199 | /* Execute the DEBI transfer. */ |
200 | s626_debi_transfer(dev); |
201 | } |
202 | |
203 | /* |
204 | * Replace the specified bits in a gate array register. Imports: mask |
205 | * specifies bits that are to be preserved, wdata is new value to be |
206 | * or'd with the masked original. |
207 | */ |
208 | static void s626_debi_replace(struct comedi_device *dev, unsigned int addr, |
209 | unsigned int mask, unsigned int wdata) |
210 | { |
211 | unsigned int val; |
212 | |
213 | addr &= 0xffff; |
214 | writel(S626_DEBI_CMD_RDWORD | addr, addr: dev->mmio + S626_P_DEBICMD); |
215 | s626_debi_transfer(dev); |
216 | |
217 | writel(S626_DEBI_CMD_WRWORD | addr, addr: dev->mmio + S626_P_DEBICMD); |
218 | val = readl(addr: dev->mmio + S626_P_DEBIAD); |
219 | val &= mask; |
220 | val |= wdata; |
221 | writel(val: val & 0xffff, addr: dev->mmio + S626_P_DEBIAD); |
222 | s626_debi_transfer(dev); |
223 | } |
224 | |
225 | /* ************** EEPROM ACCESS FUNCTIONS ************** */ |
226 | |
227 | static int s626_i2c_handshake_eoc(struct comedi_device *dev, |
228 | struct comedi_subdevice *s, |
229 | struct comedi_insn *insn, |
230 | unsigned long context) |
231 | { |
232 | bool status; |
233 | |
234 | status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
235 | if (status) |
236 | return 0; |
237 | return -EBUSY; |
238 | } |
239 | |
240 | static int s626_i2c_handshake(struct comedi_device *dev, u32 val) |
241 | { |
242 | unsigned int ctrl; |
243 | int ret; |
244 | |
245 | /* Write I2C command to I2C Transfer Control shadow register */ |
246 | writel(val, addr: dev->mmio + S626_P_I2CCTRL); |
247 | |
248 | /* |
249 | * Upload I2C shadow registers into working registers and |
250 | * wait for upload confirmation. |
251 | */ |
252 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
253 | ret = comedi_timeout(dev, NULL, NULL, cb: s626_i2c_handshake_eoc, context: 0); |
254 | if (ret) |
255 | return ret; |
256 | |
257 | /* Wait until I2C bus transfer is finished or an error occurs */ |
258 | do { |
259 | ctrl = readl(addr: dev->mmio + S626_P_I2CCTRL); |
260 | } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY); |
261 | |
262 | /* Return non-zero if I2C error occurred */ |
263 | return ctrl & S626_I2C_ERR; |
264 | } |
265 | |
266 | /* Read u8 from EEPROM. */ |
267 | static u8 s626_i2c_read(struct comedi_device *dev, u8 addr) |
268 | { |
269 | struct s626_private *devpriv = dev->private; |
270 | |
271 | /* |
272 | * Send EEPROM target address: |
273 | * Byte2 = I2C command: write to I2C EEPROM device. |
274 | * Byte1 = EEPROM internal target address. |
275 | * Byte0 = Not sent. |
276 | */ |
277 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
278 | devpriv->i2c_adrs) | |
279 | S626_I2C_B1(S626_I2C_ATTRSTOP, addr) | |
280 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) |
281 | /* Abort function and declare error if handshake failed. */ |
282 | return 0; |
283 | |
284 | /* |
285 | * Execute EEPROM read: |
286 | * Byte2 = I2C command: read from I2C EEPROM device. |
287 | * Byte1 receives uint8_t from EEPROM. |
288 | * Byte0 = Not sent. |
289 | */ |
290 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
291 | (devpriv->i2c_adrs | 1)) | |
292 | S626_I2C_B1(S626_I2C_ATTRSTOP, 0) | |
293 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) |
294 | /* Abort function and declare error if handshake failed. */ |
295 | return 0; |
296 | |
297 | return (readl(addr: dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff; |
298 | } |
299 | |
300 | /* *********** DAC FUNCTIONS *********** */ |
301 | |
302 | /* TrimDac LogicalChan-to-PhysicalChan mapping table. */ |
303 | static const u8 s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 }; |
304 | |
305 | /* TrimDac LogicalChan-to-EepromAdrs mapping table. */ |
306 | static const u8 s626_trimadrs[] = { |
307 | 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 |
308 | }; |
309 | |
310 | enum { |
311 | s626_send_dac_wait_not_mc1_a2out, |
312 | s626_send_dac_wait_ssr_af2_out, |
313 | s626_send_dac_wait_fb_buffer2_msb_00, |
314 | s626_send_dac_wait_fb_buffer2_msb_ff |
315 | }; |
316 | |
317 | static int s626_send_dac_eoc(struct comedi_device *dev, |
318 | struct comedi_subdevice *s, |
319 | struct comedi_insn *insn, |
320 | unsigned long context) |
321 | { |
322 | unsigned int status; |
323 | |
324 | switch (context) { |
325 | case s626_send_dac_wait_not_mc1_a2out: |
326 | status = readl(addr: dev->mmio + S626_P_MC1); |
327 | if (!(status & S626_MC1_A2OUT)) |
328 | return 0; |
329 | break; |
330 | case s626_send_dac_wait_ssr_af2_out: |
331 | status = readl(addr: dev->mmio + S626_P_SSR); |
332 | if (status & S626_SSR_AF2_OUT) |
333 | return 0; |
334 | break; |
335 | case s626_send_dac_wait_fb_buffer2_msb_00: |
336 | status = readl(addr: dev->mmio + S626_P_FB_BUFFER2); |
337 | if (!(status & 0xff000000)) |
338 | return 0; |
339 | break; |
340 | case s626_send_dac_wait_fb_buffer2_msb_ff: |
341 | status = readl(addr: dev->mmio + S626_P_FB_BUFFER2); |
342 | if (status & 0xff000000) |
343 | return 0; |
344 | break; |
345 | default: |
346 | return -EINVAL; |
347 | } |
348 | return -EBUSY; |
349 | } |
350 | |
351 | /* |
352 | * Private helper function: Transmit serial data to DAC via Audio |
353 | * channel 2. Assumes: (1) TSL2 slot records initialized, and (2) |
354 | * dacpol contains valid target image. |
355 | */ |
356 | static int s626_send_dac(struct comedi_device *dev, u32 val) |
357 | { |
358 | struct s626_private *devpriv = dev->private; |
359 | int ret; |
360 | |
361 | /* START THE SERIAL CLOCK RUNNING ------------- */ |
362 | |
363 | /* |
364 | * Assert DAC polarity control and enable gating of DAC serial clock |
365 | * and audio bit stream signals. At this point in time we must be |
366 | * assured of being in time slot 0. If we are not in slot 0, the |
367 | * serial clock and audio stream signals will be disabled; this is |
368 | * because the following s626_debi_write statement (which enables |
369 | * signals to be passed through the gate array) would execute before |
370 | * the trailing edge of WS1/WS3 (which turns off the signals), thus |
371 | * causing the signals to be inactive during the DAC write. |
372 | */ |
373 | s626_debi_write(dev, S626_LP_DACPOL, wdata: devpriv->dacpol); |
374 | |
375 | /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */ |
376 | |
377 | /* Copy DAC setpoint value to DAC's output DMA buffer. */ |
378 | /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */ |
379 | *devpriv->dac_wbuf = val; |
380 | |
381 | /* |
382 | * Enable the output DMA transfer. This will cause the DMAC to copy |
383 | * the DAC's data value to A2's output FIFO. The DMA transfer will |
384 | * then immediately terminate because the protection address is |
385 | * reached upon transfer of the first DWORD value. |
386 | */ |
387 | s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1); |
388 | |
389 | /* While the DMA transfer is executing ... */ |
390 | |
391 | /* |
392 | * Reset Audio2 output FIFO's underflow flag (along with any |
393 | * other FIFO underflow/overflow flags). When set, this flag |
394 | * will indicate that we have emerged from slot 0. |
395 | */ |
396 | writel(S626_ISR_AFOU, addr: dev->mmio + S626_P_ISR); |
397 | |
398 | /* |
399 | * Wait for the DMA transfer to finish so that there will be data |
400 | * available in the FIFO when time slot 1 tries to transfer a DWORD |
401 | * from the FIFO to the output buffer register. We test for DMA |
402 | * Done by polling the DMAC enable flag; this flag is automatically |
403 | * cleared when the transfer has finished. |
404 | */ |
405 | ret = comedi_timeout(dev, NULL, NULL, cb: s626_send_dac_eoc, |
406 | context: s626_send_dac_wait_not_mc1_a2out); |
407 | if (ret) { |
408 | dev_err(dev->class_dev, "DMA transfer timeout\n" ); |
409 | return ret; |
410 | } |
411 | |
412 | /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */ |
413 | |
414 | /* |
415 | * FIFO data is now available, so we enable execution of time slots |
416 | * 1 and higher by clearing the EOS flag in slot 0. Note that SD3 |
417 | * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list |
418 | * detection. |
419 | */ |
420 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2, |
421 | addr: dev->mmio + S626_VECTPORT(0)); |
422 | |
423 | /* |
424 | * Wait for slot 1 to execute to ensure that the Packet will be |
425 | * transmitted. This is detected by polling the Audio2 output FIFO |
426 | * underflow flag, which will be set when slot 1 execution has |
427 | * finished transferring the DAC's data DWORD from the output FIFO |
428 | * to the output buffer register. |
429 | */ |
430 | ret = comedi_timeout(dev, NULL, NULL, cb: s626_send_dac_eoc, |
431 | context: s626_send_dac_wait_ssr_af2_out); |
432 | if (ret) { |
433 | dev_err(dev->class_dev, |
434 | "TSL timeout waiting for slot 1 to execute\n" ); |
435 | return ret; |
436 | } |
437 | |
438 | /* |
439 | * Set up to trap execution at slot 0 when the TSL sequencer cycles |
440 | * back to slot 0 after executing the EOS in slot 5. Also, |
441 | * simultaneously shift out and in the 0x00 that is ALWAYS the value |
442 | * stored in the last byte to be shifted out of the FIFO's DWORD |
443 | * buffer register. |
444 | */ |
445 | writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS, |
446 | addr: dev->mmio + S626_VECTPORT(0)); |
447 | |
448 | /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */ |
449 | |
450 | /* |
451 | * Wait for the TSL to finish executing all time slots before |
452 | * exiting this function. We must do this so that the next DAC |
453 | * write doesn't start, thereby enabling clock/chip select signals: |
454 | * |
455 | * 1. Before the TSL sequence cycles back to slot 0, which disables |
456 | * the clock/cs signal gating and traps slot // list execution. |
457 | * we have not yet finished slot 5 then the clock/cs signals are |
458 | * still gated and we have not finished transmitting the stream. |
459 | * |
460 | * 2. While slots 2-5 are executing due to a late slot 0 trap. In |
461 | * this case, the slot sequence is currently repeating, but with |
462 | * clock/cs signals disabled. We must wait for slot 0 to trap |
463 | * execution before setting up the next DAC setpoint DMA transfer |
464 | * and enabling the clock/cs signals. To detect the end of slot 5, |
465 | * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If |
466 | * the TSL has not yet finished executing slot 5 ... |
467 | */ |
468 | if (readl(addr: dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) { |
469 | /* |
470 | * The trap was set on time and we are still executing somewhere |
471 | * in slots 2-5, so we now wait for slot 0 to execute and trap |
472 | * TSL execution. This is detected when FB_BUFFER2 MSB changes |
473 | * from 0xFF to 0x00, which slot 0 causes to happen by shifting |
474 | * out/in on SD2 the 0x00 that is always referenced by slot 5. |
475 | */ |
476 | ret = comedi_timeout(dev, NULL, NULL, cb: s626_send_dac_eoc, |
477 | context: s626_send_dac_wait_fb_buffer2_msb_00); |
478 | if (ret) { |
479 | dev_err(dev->class_dev, |
480 | "TSL timeout waiting for slot 0 to execute\n" ); |
481 | return ret; |
482 | } |
483 | } |
484 | /* |
485 | * Either (1) we were too late setting the slot 0 trap; the TSL |
486 | * sequencer restarted slot 0 before we could set the EOS trap flag, |
487 | * or (2) we were not late and execution is now trapped at slot 0. |
488 | * In either case, we must now change slot 0 so that it will store |
489 | * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes. |
490 | * In order to do this, we reprogram slot 0 so that it will shift in |
491 | * SD3, which is driven only by a pull-up resistor. |
492 | */ |
493 | writel(S626_RSD3 | S626_SIB_A2 | S626_EOS, |
494 | addr: dev->mmio + S626_VECTPORT(0)); |
495 | |
496 | /* |
497 | * Wait for slot 0 to execute, at which time the TSL is setup for |
498 | * the next DAC write. This is detected when FB_BUFFER2 MSB changes |
499 | * from 0x00 to 0xFF. |
500 | */ |
501 | ret = comedi_timeout(dev, NULL, NULL, cb: s626_send_dac_eoc, |
502 | context: s626_send_dac_wait_fb_buffer2_msb_ff); |
503 | if (ret) { |
504 | dev_err(dev->class_dev, |
505 | "TSL timeout waiting for slot 0 to execute\n" ); |
506 | return ret; |
507 | } |
508 | return 0; |
509 | } |
510 | |
511 | /* |
512 | * Private helper function: Write setpoint to an application DAC channel. |
513 | */ |
514 | static int s626_set_dac(struct comedi_device *dev, |
515 | u16 chan, int16_t dacdata) |
516 | { |
517 | struct s626_private *devpriv = dev->private; |
518 | u16 signmask; |
519 | u32 ws_image; |
520 | u32 val; |
521 | |
522 | /* |
523 | * Adjust DAC data polarity and set up Polarity Control Register image. |
524 | */ |
525 | signmask = 1 << chan; |
526 | if (dacdata < 0) { |
527 | dacdata = -dacdata; |
528 | devpriv->dacpol |= signmask; |
529 | } else { |
530 | devpriv->dacpol &= ~signmask; |
531 | } |
532 | |
533 | /* Limit DAC setpoint value to valid range. */ |
534 | if ((u16)dacdata > 0x1FFF) |
535 | dacdata = 0x1FFF; |
536 | |
537 | /* |
538 | * Set up TSL2 records (aka "vectors") for DAC update. Vectors V2 |
539 | * and V3 transmit the setpoint to the target DAC. V4 and V5 send |
540 | * data to a non-existent TrimDac channel just to keep the clock |
541 | * running after sending data to the target DAC. This is necessary |
542 | * to eliminate the clock glitch that would otherwise occur at the |
543 | * end of the target DAC's serial data stream. When the sequence |
544 | * restarts at V0 (after executing V5), the gate array automatically |
545 | * disables gating for the DAC clock and all DAC chip selects. |
546 | */ |
547 | |
548 | /* Choose DAC chip select to be asserted */ |
549 | ws_image = (chan & 2) ? S626_WS1 : S626_WS2; |
550 | /* Slot 2: Transmit high data byte to target DAC */ |
551 | writel(S626_XSD2 | S626_XFIFO_1 | ws_image, |
552 | addr: dev->mmio + S626_VECTPORT(2)); |
553 | /* Slot 3: Transmit low data byte to target DAC */ |
554 | writel(S626_XSD2 | S626_XFIFO_0 | ws_image, |
555 | addr: dev->mmio + S626_VECTPORT(3)); |
556 | /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */ |
557 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3, |
558 | addr: dev->mmio + S626_VECTPORT(4)); |
559 | /* Slot 5: running after writing target DAC's low data byte */ |
560 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS, |
561 | addr: dev->mmio + S626_VECTPORT(5)); |
562 | |
563 | /* |
564 | * Construct and transmit target DAC's serial packet: |
565 | * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>, |
566 | * and D<12:0> is the DAC setpoint. Append a WORD value (that writes |
567 | * to a non-existent TrimDac channel) that serves to keep the clock |
568 | * running after the packet has been sent to the target DAC. |
569 | */ |
570 | val = 0x0F000000; /* Continue clock after target DAC data |
571 | * (write to non-existent trimdac). |
572 | */ |
573 | val |= 0x00004000; /* Address the two main dual-DAC devices |
574 | * (TSL's chip select enables target device). |
575 | */ |
576 | val |= ((u32)(chan & 1) << 15); /* Address the DAC channel |
577 | * within the device. |
578 | */ |
579 | val |= (u32)dacdata; /* Include DAC setpoint data. */ |
580 | return s626_send_dac(dev, val); |
581 | } |
582 | |
583 | static int s626_write_trim_dac(struct comedi_device *dev, |
584 | u8 logical_chan, u8 dac_data) |
585 | { |
586 | struct s626_private *devpriv = dev->private; |
587 | u32 chan; |
588 | |
589 | /* |
590 | * Save the new setpoint in case the application needs to read it back |
591 | * later. |
592 | */ |
593 | devpriv->trim_setpoint[logical_chan] = dac_data; |
594 | |
595 | /* Map logical channel number to physical channel number. */ |
596 | chan = s626_trimchan[logical_chan]; |
597 | |
598 | /* |
599 | * Set up TSL2 records for TrimDac write operation. All slots shift |
600 | * 0xFF in from pulled-up SD3 so that the end of the slot sequence |
601 | * can be detected. |
602 | */ |
603 | |
604 | /* Slot 2: Send high uint8_t to target TrimDac */ |
605 | writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3, |
606 | addr: dev->mmio + S626_VECTPORT(2)); |
607 | /* Slot 3: Send low uint8_t to target TrimDac */ |
608 | writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3, |
609 | addr: dev->mmio + S626_VECTPORT(3)); |
610 | /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */ |
611 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1, |
612 | addr: dev->mmio + S626_VECTPORT(4)); |
613 | /* Slot 5: Send NOP low uint8_t to DAC0 */ |
614 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS, |
615 | addr: dev->mmio + S626_VECTPORT(5)); |
616 | |
617 | /* |
618 | * Construct and transmit target DAC's serial packet: |
619 | * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the |
620 | * DAC channel's address, and D<7:0> is the DAC setpoint. Append a |
621 | * WORD value (that writes a channel 0 NOP command to a non-existent |
622 | * main DAC channel) that serves to keep the clock running after the |
623 | * packet has been sent to the target DAC. |
624 | */ |
625 | |
626 | /* |
627 | * Address the DAC channel within the trimdac device. |
628 | * Include DAC setpoint data. |
629 | */ |
630 | return s626_send_dac(dev, val: (chan << 8) | dac_data); |
631 | } |
632 | |
633 | static int s626_load_trim_dacs(struct comedi_device *dev) |
634 | { |
635 | u8 i; |
636 | int ret; |
637 | |
638 | /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */ |
639 | for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) { |
640 | ret = s626_write_trim_dac(dev, logical_chan: i, |
641 | dac_data: s626_i2c_read(dev, addr: s626_trimadrs[i])); |
642 | if (ret) |
643 | return ret; |
644 | } |
645 | return 0; |
646 | } |
647 | |
648 | /* ****** COUNTER FUNCTIONS ******* */ |
649 | |
650 | /* |
651 | * All counter functions address a specific counter by means of the |
652 | * "Counter" argument, which is a logical counter number. The Counter |
653 | * argument may have any of the following legal values: 0=0A, 1=1A, |
654 | * 2=2A, 3=0B, 4=1B, 5=2B. |
655 | */ |
656 | |
657 | /* |
658 | * Return/set a counter pair's latch trigger source. 0: On read |
659 | * access, 1: A index latches A, 2: B index latches B, 3: A overflow |
660 | * latches B. |
661 | */ |
662 | static void s626_set_latch_source(struct comedi_device *dev, |
663 | unsigned int chan, u16 value) |
664 | { |
665 | s626_debi_replace(dev, S626_LP_CRB(chan), |
666 | mask: ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC), |
667 | S626_SET_CRB_LATCHSRC(value)); |
668 | } |
669 | |
670 | /* |
671 | * Write value into counter preload register. |
672 | */ |
673 | static void s626_preload(struct comedi_device *dev, |
674 | unsigned int chan, u32 value) |
675 | { |
676 | s626_debi_write(dev, S626_LP_CNTR(chan), wdata: value); |
677 | s626_debi_write(dev, S626_LP_CNTR(chan) + 2, wdata: value >> 16); |
678 | } |
679 | |
680 | /* ****** PRIVATE COUNTER FUNCTIONS ****** */ |
681 | |
682 | /* |
683 | * Reset a counter's index and overflow event capture flags. |
684 | */ |
685 | static void s626_reset_cap_flags(struct comedi_device *dev, |
686 | unsigned int chan) |
687 | { |
688 | u16 set; |
689 | |
690 | set = S626_SET_CRB_INTRESETCMD(1); |
691 | if (chan < 3) |
692 | set |= S626_SET_CRB_INTRESET_A(1); |
693 | else |
694 | set |= S626_SET_CRB_INTRESET_B(1); |
695 | |
696 | s626_debi_replace(dev, S626_LP_CRB(chan), mask: ~S626_CRBMSK_INTCTRL, wdata: set); |
697 | } |
698 | |
699 | /* |
700 | * Set the operating mode for the specified counter. The setup |
701 | * parameter is treated as a COUNTER_SETUP data type. The following |
702 | * parameters are programmable (all other parms are ignored): ClkMult, |
703 | * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc. |
704 | */ |
705 | static void s626_set_mode_a(struct comedi_device *dev, |
706 | unsigned int chan, u16 setup, |
707 | u16 disable_int_src) |
708 | { |
709 | struct s626_private *devpriv = dev->private; |
710 | u16 cra; |
711 | u16 crb; |
712 | unsigned int cntsrc, clkmult, clkpol; |
713 | |
714 | /* Initialize CRA and CRB images. */ |
715 | /* Preload trigger is passed through. */ |
716 | cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup)); |
717 | /* IndexSrc is passed through. */ |
718 | cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup)); |
719 | |
720 | /* Reset any pending CounterA event captures. */ |
721 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1); |
722 | /* Clock enable is passed through. */ |
723 | crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup)); |
724 | |
725 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ |
726 | if (!disable_int_src) |
727 | cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup)); |
728 | |
729 | /* Populate all mode-dependent attributes of CRA & CRB images. */ |
730 | clkpol = S626_GET_STD_CLKPOL(setup); |
731 | switch (S626_GET_STD_ENCMODE(setup)) { |
732 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
733 | /* Force to Timer mode (Extender valid only for B counters). */ |
734 | /* Fall through to case S626_ENCMODE_TIMER: */ |
735 | case S626_ENCMODE_TIMER: /* Timer Mode: */ |
736 | /* CntSrcA<1> selects system clock */ |
737 | cntsrc = S626_CNTSRC_SYSCLK; |
738 | /* Count direction (CntSrcA<0>) obtained from ClkPol. */ |
739 | cntsrc |= clkpol; |
740 | /* ClkPolA behaves as always-on clock enable. */ |
741 | clkpol = 1; |
742 | /* ClkMult must be 1x. */ |
743 | clkmult = S626_CLKMULT_1X; |
744 | break; |
745 | default: /* Counter Mode: */ |
746 | /* Select ENC_C and ENC_D as clock/direction inputs. */ |
747 | cntsrc = S626_CNTSRC_ENCODER; |
748 | /* Clock polarity is passed through. */ |
749 | /* Force multiplier to x1 if not legal, else pass through. */ |
750 | clkmult = S626_GET_STD_CLKMULT(setup); |
751 | if (clkmult == S626_CLKMULT_SPECIAL) |
752 | clkmult = S626_CLKMULT_1X; |
753 | break; |
754 | } |
755 | cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) | |
756 | S626_SET_CRA_CLKMULT_A(clkmult); |
757 | |
758 | /* |
759 | * Force positive index polarity if IndxSrc is software-driven only, |
760 | * otherwise pass it through. |
761 | */ |
762 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
763 | cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup)); |
764 | |
765 | /* |
766 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt |
767 | * enable mask to indicate the counter interrupt is disabled. |
768 | */ |
769 | if (disable_int_src) |
770 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
771 | S626_INDXMASK(chan)); |
772 | |
773 | /* |
774 | * While retaining CounterB and LatchSrc configurations, program the |
775 | * new counter operating mode. |
776 | */ |
777 | s626_debi_replace(dev, S626_LP_CRA(chan), |
778 | S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, wdata: cra); |
779 | s626_debi_replace(dev, S626_LP_CRB(chan), |
780 | mask: ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), wdata: crb); |
781 | } |
782 | |
783 | static void s626_set_mode_b(struct comedi_device *dev, |
784 | unsigned int chan, u16 setup, |
785 | u16 disable_int_src) |
786 | { |
787 | struct s626_private *devpriv = dev->private; |
788 | u16 cra; |
789 | u16 crb; |
790 | unsigned int cntsrc, clkmult, clkpol; |
791 | |
792 | /* Initialize CRA and CRB images. */ |
793 | /* IndexSrc is passed through. */ |
794 | cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup)); |
795 | |
796 | /* Reset event captures and disable interrupts. */ |
797 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1); |
798 | /* Clock enable is passed through. */ |
799 | crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup)); |
800 | /* Preload trigger source is passed through. */ |
801 | crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup)); |
802 | |
803 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ |
804 | if (!disable_int_src) |
805 | crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup)); |
806 | |
807 | /* Populate all mode-dependent attributes of CRA & CRB images. */ |
808 | clkpol = S626_GET_STD_CLKPOL(setup); |
809 | switch (S626_GET_STD_ENCMODE(setup)) { |
810 | case S626_ENCMODE_TIMER: /* Timer Mode: */ |
811 | /* CntSrcB<1> selects system clock */ |
812 | cntsrc = S626_CNTSRC_SYSCLK; |
813 | /* with direction (CntSrcB<0>) obtained from ClkPol. */ |
814 | cntsrc |= clkpol; |
815 | /* ClkPolB behaves as always-on clock enable. */ |
816 | clkpol = 1; |
817 | /* ClkMultB must be 1x. */ |
818 | clkmult = S626_CLKMULT_1X; |
819 | break; |
820 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
821 | /* CntSrcB source is OverflowA (same as "timer") */ |
822 | cntsrc = S626_CNTSRC_SYSCLK; |
823 | /* with direction obtained from ClkPol. */ |
824 | cntsrc |= clkpol; |
825 | /* ClkPolB controls IndexB -- always set to active. */ |
826 | clkpol = 1; |
827 | /* ClkMultB selects OverflowA as the clock source. */ |
828 | clkmult = S626_CLKMULT_SPECIAL; |
829 | break; |
830 | default: /* Counter Mode: */ |
831 | /* Select ENC_C and ENC_D as clock/direction inputs. */ |
832 | cntsrc = S626_CNTSRC_ENCODER; |
833 | /* ClkPol is passed through. */ |
834 | /* Force ClkMult to x1 if not legal, otherwise pass through. */ |
835 | clkmult = S626_GET_STD_CLKMULT(setup); |
836 | if (clkmult == S626_CLKMULT_SPECIAL) |
837 | clkmult = S626_CLKMULT_1X; |
838 | break; |
839 | } |
840 | cra |= S626_SET_CRA_CNTSRC_B(cntsrc); |
841 | crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult); |
842 | |
843 | /* |
844 | * Force positive index polarity if IndxSrc is software-driven only, |
845 | * otherwise pass it through. |
846 | */ |
847 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
848 | crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup)); |
849 | |
850 | /* |
851 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt |
852 | * enable mask to indicate the counter interrupt is disabled. |
853 | */ |
854 | if (disable_int_src) |
855 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
856 | S626_INDXMASK(chan)); |
857 | |
858 | /* |
859 | * While retaining CounterA and LatchSrc configurations, program the |
860 | * new counter operating mode. |
861 | */ |
862 | s626_debi_replace(dev, S626_LP_CRA(chan), |
863 | mask: ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), wdata: cra); |
864 | s626_debi_replace(dev, S626_LP_CRB(chan), |
865 | S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, wdata: crb); |
866 | } |
867 | |
868 | static void s626_set_mode(struct comedi_device *dev, |
869 | unsigned int chan, |
870 | u16 setup, u16 disable_int_src) |
871 | { |
872 | if (chan < 3) |
873 | s626_set_mode_a(dev, chan, setup, disable_int_src); |
874 | else |
875 | s626_set_mode_b(dev, chan, setup, disable_int_src); |
876 | } |
877 | |
878 | /* |
879 | * Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. |
880 | */ |
881 | static void s626_set_enable(struct comedi_device *dev, |
882 | unsigned int chan, u16 enab) |
883 | { |
884 | unsigned int mask = S626_CRBMSK_INTCTRL; |
885 | unsigned int set; |
886 | |
887 | if (chan < 3) { |
888 | mask |= S626_CRBMSK_CLKENAB_A; |
889 | set = S626_SET_CRB_CLKENAB_A(enab); |
890 | } else { |
891 | mask |= S626_CRBMSK_CLKENAB_B; |
892 | set = S626_SET_CRB_CLKENAB_B(enab); |
893 | } |
894 | s626_debi_replace(dev, S626_LP_CRB(chan), mask: ~mask, wdata: set); |
895 | } |
896 | |
897 | /* |
898 | * Return/set the event that will trigger transfer of the preload |
899 | * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow, |
900 | * 2=OverflowA (B counters only), 3=disabled. |
901 | */ |
902 | static void s626_set_load_trig(struct comedi_device *dev, |
903 | unsigned int chan, u16 trig) |
904 | { |
905 | u16 reg; |
906 | u16 mask; |
907 | u16 set; |
908 | |
909 | if (chan < 3) { |
910 | reg = S626_LP_CRA(chan); |
911 | mask = S626_CRAMSK_LOADSRC_A; |
912 | set = S626_SET_CRA_LOADSRC_A(trig); |
913 | } else { |
914 | reg = S626_LP_CRB(chan); |
915 | mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL; |
916 | set = S626_SET_CRB_LOADSRC_B(trig); |
917 | } |
918 | s626_debi_replace(dev, addr: reg, mask: ~mask, wdata: set); |
919 | } |
920 | |
921 | /* |
922 | * Return/set counter interrupt source and clear any captured |
923 | * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly, |
924 | * 2=IndexOnly, 3=IndexAndOverflow. |
925 | */ |
926 | static void s626_set_int_src(struct comedi_device *dev, |
927 | unsigned int chan, u16 int_source) |
928 | { |
929 | struct s626_private *devpriv = dev->private; |
930 | u16 cra_reg = S626_LP_CRA(chan); |
931 | u16 crb_reg = S626_LP_CRB(chan); |
932 | |
933 | if (chan < 3) { |
934 | /* Reset any pending counter overflow or index captures */ |
935 | s626_debi_replace(dev, addr: crb_reg, mask: ~S626_CRBMSK_INTCTRL, |
936 | S626_SET_CRB_INTRESETCMD(1) | |
937 | S626_SET_CRB_INTRESET_A(1)); |
938 | |
939 | /* Program counter interrupt source */ |
940 | s626_debi_replace(dev, addr: cra_reg, mask: ~S626_CRAMSK_INTSRC_A, |
941 | S626_SET_CRA_INTSRC_A(int_source)); |
942 | } else { |
943 | u16 crb; |
944 | |
945 | /* Cache writeable CRB register image */ |
946 | crb = s626_debi_read(dev, addr: crb_reg); |
947 | crb &= ~S626_CRBMSK_INTCTRL; |
948 | |
949 | /* Reset any pending counter overflow or index captures */ |
950 | s626_debi_write(dev, addr: crb_reg, |
951 | wdata: crb | S626_SET_CRB_INTRESETCMD(1) | |
952 | S626_SET_CRB_INTRESET_B(1)); |
953 | |
954 | /* Program counter interrupt source */ |
955 | s626_debi_write(dev, addr: crb_reg, |
956 | wdata: (crb & ~S626_CRBMSK_INTSRC_B) | |
957 | S626_SET_CRB_INTSRC_B(int_source)); |
958 | } |
959 | |
960 | /* Update MISC2 interrupt enable mask. */ |
961 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
962 | S626_INDXMASK(chan)); |
963 | switch (int_source) { |
964 | case 0: |
965 | default: |
966 | break; |
967 | case 1: |
968 | devpriv->counter_int_enabs |= S626_OVERMASK(chan); |
969 | break; |
970 | case 2: |
971 | devpriv->counter_int_enabs |= S626_INDXMASK(chan); |
972 | break; |
973 | case 3: |
974 | devpriv->counter_int_enabs |= (S626_OVERMASK(chan) | |
975 | S626_INDXMASK(chan)); |
976 | break; |
977 | } |
978 | } |
979 | |
980 | /* |
981 | * Generate an index pulse. |
982 | */ |
983 | static void s626_pulse_index(struct comedi_device *dev, |
984 | unsigned int chan) |
985 | { |
986 | if (chan < 3) { |
987 | u16 cra; |
988 | |
989 | cra = s626_debi_read(dev, S626_LP_CRA(chan)); |
990 | |
991 | /* Pulse index */ |
992 | s626_debi_write(dev, S626_LP_CRA(chan), |
993 | wdata: (cra ^ S626_CRAMSK_INDXPOL_A)); |
994 | s626_debi_write(dev, S626_LP_CRA(chan), wdata: cra); |
995 | } else { |
996 | u16 crb; |
997 | |
998 | crb = s626_debi_read(dev, S626_LP_CRB(chan)); |
999 | crb &= ~S626_CRBMSK_INTCTRL; |
1000 | |
1001 | /* Pulse index */ |
1002 | s626_debi_write(dev, S626_LP_CRB(chan), |
1003 | wdata: (crb ^ S626_CRBMSK_INDXPOL_B)); |
1004 | s626_debi_write(dev, S626_LP_CRB(chan), wdata: crb); |
1005 | } |
1006 | } |
1007 | |
1008 | static unsigned int s626_ai_reg_to_uint(unsigned int data) |
1009 | { |
1010 | return ((data >> 18) & 0x3fff) ^ 0x2000; |
1011 | } |
1012 | |
1013 | static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan) |
1014 | { |
1015 | unsigned int group = chan / 16; |
1016 | unsigned int mask = 1 << (chan - (16 * group)); |
1017 | unsigned int status; |
1018 | |
1019 | /* set channel to capture positive edge */ |
1020 | status = s626_debi_read(dev, S626_LP_RDEDGSEL(group)); |
1021 | s626_debi_write(dev, S626_LP_WREDGSEL(group), wdata: mask | status); |
1022 | |
1023 | /* enable interrupt on selected channel */ |
1024 | status = s626_debi_read(dev, S626_LP_RDINTSEL(group)); |
1025 | s626_debi_write(dev, S626_LP_WRINTSEL(group), wdata: mask | status); |
1026 | |
1027 | /* enable edge capture write command */ |
1028 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP); |
1029 | |
1030 | /* enable edge capture on selected channel */ |
1031 | status = s626_debi_read(dev, S626_LP_RDCAPSEL(group)); |
1032 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), wdata: mask | status); |
1033 | |
1034 | return 0; |
1035 | } |
1036 | |
1037 | static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group, |
1038 | unsigned int mask) |
1039 | { |
1040 | /* disable edge capture write command */ |
1041 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
1042 | |
1043 | /* enable edge capture on selected channel */ |
1044 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), wdata: mask); |
1045 | |
1046 | return 0; |
1047 | } |
1048 | |
1049 | static int s626_dio_clear_irq(struct comedi_device *dev) |
1050 | { |
1051 | unsigned int group; |
1052 | |
1053 | /* disable edge capture write command */ |
1054 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
1055 | |
1056 | /* clear all dio pending events and interrupt */ |
1057 | for (group = 0; group < S626_DIO_BANKS; group++) |
1058 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), wdata: 0xffff); |
1059 | |
1060 | return 0; |
1061 | } |
1062 | |
1063 | static void s626_handle_dio_interrupt(struct comedi_device *dev, |
1064 | u16 irqbit, u8 group) |
1065 | { |
1066 | struct s626_private *devpriv = dev->private; |
1067 | struct comedi_subdevice *s = dev->read_subdev; |
1068 | struct comedi_cmd *cmd = &s->async->cmd; |
1069 | |
1070 | s626_dio_reset_irq(dev, group, mask: irqbit); |
1071 | |
1072 | if (devpriv->ai_cmd_running) { |
1073 | /* check if interrupt is an ai acquisition start trigger */ |
1074 | if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 && |
1075 | cmd->start_src == TRIG_EXT) { |
1076 | /* Start executing the RPS program */ |
1077 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
1078 | |
1079 | if (cmd->scan_begin_src == TRIG_EXT) |
1080 | s626_dio_set_irq(dev, chan: cmd->scan_begin_arg); |
1081 | } |
1082 | if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 && |
1083 | cmd->scan_begin_src == TRIG_EXT) { |
1084 | /* Trigger ADC scan loop start */ |
1085 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
1086 | |
1087 | if (cmd->convert_src == TRIG_EXT) { |
1088 | devpriv->ai_convert_count = cmd->chanlist_len; |
1089 | |
1090 | s626_dio_set_irq(dev, chan: cmd->convert_arg); |
1091 | } |
1092 | |
1093 | if (cmd->convert_src == TRIG_TIMER) { |
1094 | devpriv->ai_convert_count = cmd->chanlist_len; |
1095 | s626_set_enable(dev, chan: 5, S626_CLKENAB_ALWAYS); |
1096 | } |
1097 | } |
1098 | if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 && |
1099 | cmd->convert_src == TRIG_EXT) { |
1100 | /* Trigger ADC scan loop start */ |
1101 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
1102 | |
1103 | devpriv->ai_convert_count--; |
1104 | if (devpriv->ai_convert_count > 0) |
1105 | s626_dio_set_irq(dev, chan: cmd->convert_arg); |
1106 | } |
1107 | } |
1108 | } |
1109 | |
1110 | static void s626_check_dio_interrupts(struct comedi_device *dev) |
1111 | { |
1112 | u16 irqbit; |
1113 | u8 group; |
1114 | |
1115 | for (group = 0; group < S626_DIO_BANKS; group++) { |
1116 | /* read interrupt type */ |
1117 | irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group)); |
1118 | |
1119 | /* check if interrupt is generated from dio channels */ |
1120 | if (irqbit) { |
1121 | s626_handle_dio_interrupt(dev, irqbit, group); |
1122 | return; |
1123 | } |
1124 | } |
1125 | } |
1126 | |
1127 | static void s626_check_counter_interrupts(struct comedi_device *dev) |
1128 | { |
1129 | struct s626_private *devpriv = dev->private; |
1130 | struct comedi_subdevice *s = dev->read_subdev; |
1131 | struct comedi_async *async = s->async; |
1132 | struct comedi_cmd *cmd = &async->cmd; |
1133 | u16 irqbit; |
1134 | |
1135 | /* read interrupt type */ |
1136 | irqbit = s626_debi_read(dev, S626_LP_RDMISC2); |
1137 | |
1138 | /* check interrupt on counters */ |
1139 | if (irqbit & S626_IRQ_COINT1A) { |
1140 | /* clear interrupt capture flag */ |
1141 | s626_reset_cap_flags(dev, chan: 0); |
1142 | } |
1143 | if (irqbit & S626_IRQ_COINT2A) { |
1144 | /* clear interrupt capture flag */ |
1145 | s626_reset_cap_flags(dev, chan: 1); |
1146 | } |
1147 | if (irqbit & S626_IRQ_COINT3A) { |
1148 | /* clear interrupt capture flag */ |
1149 | s626_reset_cap_flags(dev, chan: 2); |
1150 | } |
1151 | if (irqbit & S626_IRQ_COINT1B) { |
1152 | /* clear interrupt capture flag */ |
1153 | s626_reset_cap_flags(dev, chan: 3); |
1154 | } |
1155 | if (irqbit & S626_IRQ_COINT2B) { |
1156 | /* clear interrupt capture flag */ |
1157 | s626_reset_cap_flags(dev, chan: 4); |
1158 | |
1159 | if (devpriv->ai_convert_count > 0) { |
1160 | devpriv->ai_convert_count--; |
1161 | if (devpriv->ai_convert_count == 0) |
1162 | s626_set_enable(dev, chan: 4, S626_CLKENAB_INDEX); |
1163 | |
1164 | if (cmd->convert_src == TRIG_TIMER) { |
1165 | /* Trigger ADC scan loop start */ |
1166 | s626_mc_enable(dev, S626_MC2_ADC_RPS, |
1167 | S626_P_MC2); |
1168 | } |
1169 | } |
1170 | } |
1171 | if (irqbit & S626_IRQ_COINT3B) { |
1172 | /* clear interrupt capture flag */ |
1173 | s626_reset_cap_flags(dev, chan: 5); |
1174 | |
1175 | if (cmd->scan_begin_src == TRIG_TIMER) { |
1176 | /* Trigger ADC scan loop start */ |
1177 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
1178 | } |
1179 | |
1180 | if (cmd->convert_src == TRIG_TIMER) { |
1181 | devpriv->ai_convert_count = cmd->chanlist_len; |
1182 | s626_set_enable(dev, chan: 4, S626_CLKENAB_ALWAYS); |
1183 | } |
1184 | } |
1185 | } |
1186 | |
1187 | static bool s626_handle_eos_interrupt(struct comedi_device *dev) |
1188 | { |
1189 | struct s626_private *devpriv = dev->private; |
1190 | struct comedi_subdevice *s = dev->read_subdev; |
1191 | struct comedi_async *async = s->async; |
1192 | struct comedi_cmd *cmd = &async->cmd; |
1193 | /* |
1194 | * Init ptr to DMA buffer that holds new ADC data. We skip the |
1195 | * first uint16_t in the buffer because it contains junk data |
1196 | * from the final ADC of the previous poll list scan. |
1197 | */ |
1198 | u32 *readaddr = (u32 *)devpriv->ana_buf.logical_base + 1; |
1199 | int i; |
1200 | |
1201 | /* get the data and hand it over to comedi */ |
1202 | for (i = 0; i < cmd->chanlist_len; i++) { |
1203 | unsigned short tempdata; |
1204 | |
1205 | /* |
1206 | * Convert ADC data to 16-bit integer values and copy |
1207 | * to application buffer. |
1208 | */ |
1209 | tempdata = s626_ai_reg_to_uint(data: *readaddr); |
1210 | readaddr++; |
1211 | |
1212 | comedi_buf_write_samples(s, data: &tempdata, nsamples: 1); |
1213 | } |
1214 | |
1215 | if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg) |
1216 | async->events |= COMEDI_CB_EOA; |
1217 | |
1218 | if (async->events & COMEDI_CB_CANCEL_MASK) |
1219 | devpriv->ai_cmd_running = 0; |
1220 | |
1221 | if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) |
1222 | s626_dio_set_irq(dev, chan: cmd->scan_begin_arg); |
1223 | |
1224 | comedi_handle_events(dev, s); |
1225 | |
1226 | return !devpriv->ai_cmd_running; |
1227 | } |
1228 | |
1229 | static irqreturn_t s626_irq_handler(int irq, void *d) |
1230 | { |
1231 | struct comedi_device *dev = d; |
1232 | unsigned long flags; |
1233 | u32 irqtype, irqstatus; |
1234 | |
1235 | if (!dev->attached) |
1236 | return IRQ_NONE; |
1237 | /* lock to avoid race with comedi_poll */ |
1238 | spin_lock_irqsave(&dev->spinlock, flags); |
1239 | |
1240 | /* save interrupt enable register state */ |
1241 | irqstatus = readl(addr: dev->mmio + S626_P_IER); |
1242 | |
1243 | /* read interrupt type */ |
1244 | irqtype = readl(addr: dev->mmio + S626_P_ISR); |
1245 | |
1246 | /* disable master interrupt */ |
1247 | writel(val: 0, addr: dev->mmio + S626_P_IER); |
1248 | |
1249 | /* clear interrupt */ |
1250 | writel(val: irqtype, addr: dev->mmio + S626_P_ISR); |
1251 | |
1252 | switch (irqtype) { |
1253 | case S626_IRQ_RPS1: /* end_of_scan occurs */ |
1254 | if (s626_handle_eos_interrupt(dev)) |
1255 | irqstatus = 0; |
1256 | break; |
1257 | case S626_IRQ_GPIO3: /* check dio and counter interrupt */ |
1258 | /* s626_dio_clear_irq(dev); */ |
1259 | s626_check_dio_interrupts(dev); |
1260 | s626_check_counter_interrupts(dev); |
1261 | break; |
1262 | } |
1263 | |
1264 | /* enable interrupt */ |
1265 | writel(val: irqstatus, addr: dev->mmio + S626_P_IER); |
1266 | |
1267 | spin_unlock_irqrestore(lock: &dev->spinlock, flags); |
1268 | return IRQ_HANDLED; |
1269 | } |
1270 | |
1271 | /* |
1272 | * This function builds the RPS program for hardware driven acquisition. |
1273 | */ |
1274 | static void s626_reset_adc(struct comedi_device *dev, u8 *ppl) |
1275 | { |
1276 | struct s626_private *devpriv = dev->private; |
1277 | struct comedi_subdevice *s = dev->read_subdev; |
1278 | struct comedi_cmd *cmd = &s->async->cmd; |
1279 | u32 *rps; |
1280 | u32 jmp_adrs; |
1281 | u16 i; |
1282 | u16 n; |
1283 | u32 local_ppl; |
1284 | |
1285 | /* Stop RPS program in case it is currently running */ |
1286 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
1287 | |
1288 | /* Set starting logical address to write RPS commands. */ |
1289 | rps = (u32 *)devpriv->rps_buf.logical_base; |
1290 | |
1291 | /* Initialize RPS instruction pointer */ |
1292 | writel(val: (u32)devpriv->rps_buf.physical_base, |
1293 | addr: dev->mmio + S626_P_RPSADDR1); |
1294 | |
1295 | /* Construct RPS program in rps_buf DMA buffer */ |
1296 | if (cmd->scan_begin_src != TRIG_FOLLOW) { |
1297 | /* Wait for Start trigger. */ |
1298 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1299 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; |
1300 | } |
1301 | |
1302 | /* |
1303 | * SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary |
1304 | * because the first RPS DEBI Write following a non-RPS DEBI write |
1305 | * seems to always fail. If we don't do this dummy write, the ADC |
1306 | * gain might not be set to the value required for the first slot in |
1307 | * the poll list; the ADC gain would instead remain unchanged from |
1308 | * the previously programmed value. |
1309 | */ |
1310 | /* Write DEBI Write command and address to shadow RAM. */ |
1311 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1312 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; |
1313 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); |
1314 | /* Write DEBI immediate data to shadow RAM: */ |
1315 | *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ |
1316 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
1317 | /* Reset "shadow RAM uploaded" flag. */ |
1318 | /* Invoke shadow RAM upload. */ |
1319 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
1320 | /* Wait for shadow upload to finish. */ |
1321 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
1322 | |
1323 | /* |
1324 | * Digitize all slots in the poll list. This is implemented as a |
1325 | * for loop to limit the slot count to 16 in case the application |
1326 | * forgot to set the S626_EOPL flag in the final slot. |
1327 | */ |
1328 | for (devpriv->adc_items = 0; devpriv->adc_items < 16; |
1329 | devpriv->adc_items++) { |
1330 | /* |
1331 | * Convert application's poll list item to private board class |
1332 | * format. Each app poll list item is an uint8_t with form |
1333 | * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 = |
1334 | * +-10V, 1 = +-5V, and EOPL = End of Poll List marker. |
1335 | */ |
1336 | local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V : |
1337 | S626_GSEL_BIPOLAR10V); |
1338 | |
1339 | /* Switch ADC analog gain. */ |
1340 | /* Write DEBI command and address to shadow RAM. */ |
1341 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1342 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; |
1343 | /* Write DEBI immediate data to shadow RAM. */ |
1344 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); |
1345 | *rps++ = local_ppl; |
1346 | /* Reset "shadow RAM uploaded" flag. */ |
1347 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
1348 | /* Invoke shadow RAM upload. */ |
1349 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
1350 | /* Wait for shadow upload to finish. */ |
1351 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
1352 | /* Select ADC analog input channel. */ |
1353 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1354 | /* Write DEBI command and address to shadow RAM. */ |
1355 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL; |
1356 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); |
1357 | /* Write DEBI immediate data to shadow RAM. */ |
1358 | *rps++ = local_ppl; |
1359 | /* Reset "shadow RAM uploaded" flag. */ |
1360 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
1361 | /* Invoke shadow RAM upload. */ |
1362 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
1363 | /* Wait for shadow upload to finish. */ |
1364 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
1365 | |
1366 | /* |
1367 | * Delay at least 10 microseconds for analog input settling. |
1368 | * Instead of padding with NOPs, we use S626_RPS_JUMP |
1369 | * instructions here; this allows us to produce a longer delay |
1370 | * than is possible with NOPs because each S626_RPS_JUMP |
1371 | * flushes the RPS' instruction prefetch pipeline. |
1372 | */ |
1373 | jmp_adrs = |
1374 | (u32)devpriv->rps_buf.physical_base + |
1375 | (u32)((unsigned long)rps - |
1376 | (unsigned long)devpriv->rps_buf.logical_base); |
1377 | for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) { |
1378 | jmp_adrs += 8; /* Repeat to implement time delay: */ |
1379 | /* Jump to next RPS instruction. */ |
1380 | *rps++ = S626_RPS_JUMP; |
1381 | *rps++ = jmp_adrs; |
1382 | } |
1383 | |
1384 | if (cmd->convert_src != TRIG_NOW) { |
1385 | /* Wait for Start trigger. */ |
1386 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1387 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; |
1388 | } |
1389 | /* Start ADC by pulsing GPIO1. */ |
1390 | /* Begin ADC Start pulse. */ |
1391 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1392 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; |
1393 | *rps++ = S626_RPS_NOP; |
1394 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
1395 | /* End ADC Start pulse. */ |
1396 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1397 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; |
1398 | /* |
1399 | * Wait for ADC to complete (GPIO2 is asserted high when ADC not |
1400 | * busy) and for data from previous conversion to shift into FB |
1401 | * BUFFER 1 register. |
1402 | */ |
1403 | /* Wait for ADC done. */ |
1404 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; |
1405 | |
1406 | /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */ |
1407 | *rps++ = S626_RPS_STREG | |
1408 | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); |
1409 | *rps++ = (u32)devpriv->ana_buf.physical_base + |
1410 | (devpriv->adc_items << 2); |
1411 | |
1412 | /* |
1413 | * If this slot's EndOfPollList flag is set, all channels have |
1414 | * now been processed. |
1415 | */ |
1416 | if (*ppl++ & S626_EOPL) { |
1417 | devpriv->adc_items++; /* Adjust poll list item count. */ |
1418 | break; /* Exit poll list processing loop. */ |
1419 | } |
1420 | } |
1421 | |
1422 | /* |
1423 | * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the |
1424 | * ADC to stabilize for 2 microseconds before starting the final |
1425 | * (dummy) conversion. This delay is necessary to allow sufficient |
1426 | * time between last conversion finished and the start of the dummy |
1427 | * conversion. Without this delay, the last conversion's data value |
1428 | * is sometimes set to the previous conversion's data value. |
1429 | */ |
1430 | for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++) |
1431 | *rps++ = S626_RPS_NOP; |
1432 | |
1433 | /* |
1434 | * Start a dummy conversion to cause the data from the last |
1435 | * conversion of interest to be shifted in. |
1436 | */ |
1437 | /* Begin ADC Start pulse. */ |
1438 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1439 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; |
1440 | *rps++ = S626_RPS_NOP; |
1441 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
1442 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */ |
1443 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; |
1444 | |
1445 | /* |
1446 | * Wait for the data from the last conversion of interest to arrive |
1447 | * in FB BUFFER 1 register. |
1448 | */ |
1449 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */ |
1450 | |
1451 | /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */ |
1452 | *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); |
1453 | *rps++ = (u32)devpriv->ana_buf.physical_base + |
1454 | (devpriv->adc_items << 2); |
1455 | |
1456 | /* Indicate ADC scan loop is finished. */ |
1457 | /* Signal ReadADC() that scan is done. */ |
1458 | /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */ |
1459 | |
1460 | /* invoke interrupt */ |
1461 | if (devpriv->ai_cmd_running == 1) |
1462 | *rps++ = S626_RPS_IRQ; |
1463 | |
1464 | /* Restart RPS program at its beginning. */ |
1465 | *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */ |
1466 | *rps++ = (u32)devpriv->rps_buf.physical_base; |
1467 | |
1468 | /* End of RPS program build */ |
1469 | } |
1470 | |
1471 | static int s626_ai_eoc(struct comedi_device *dev, |
1472 | struct comedi_subdevice *s, |
1473 | struct comedi_insn *insn, |
1474 | unsigned long context) |
1475 | { |
1476 | unsigned int status; |
1477 | |
1478 | status = readl(addr: dev->mmio + S626_P_PSR); |
1479 | if (status & S626_PSR_GPIO2) |
1480 | return 0; |
1481 | return -EBUSY; |
1482 | } |
1483 | |
1484 | static int s626_ai_insn_read(struct comedi_device *dev, |
1485 | struct comedi_subdevice *s, |
1486 | struct comedi_insn *insn, |
1487 | unsigned int *data) |
1488 | { |
1489 | u16 chan = CR_CHAN(insn->chanspec); |
1490 | u16 range = CR_RANGE(insn->chanspec); |
1491 | u16 adc_spec = 0; |
1492 | u32 gpio_image; |
1493 | u32 tmp; |
1494 | int ret; |
1495 | int n; |
1496 | |
1497 | /* |
1498 | * Convert application's ADC specification into form |
1499 | * appropriate for register programming. |
1500 | */ |
1501 | if (range == 0) |
1502 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V); |
1503 | else |
1504 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V); |
1505 | |
1506 | /* Switch ADC analog gain. */ |
1507 | s626_debi_write(dev, S626_LP_GSEL, wdata: adc_spec); /* Set gain. */ |
1508 | |
1509 | /* Select ADC analog input channel. */ |
1510 | s626_debi_write(dev, S626_LP_ISEL, wdata: adc_spec); /* Select channel. */ |
1511 | |
1512 | for (n = 0; n < insn->n; n++) { |
1513 | /* Delay 10 microseconds for analog input settling. */ |
1514 | usleep_range(min: 10, max: 20); |
1515 | |
1516 | /* Start ADC by pulsing GPIO1 low */ |
1517 | gpio_image = readl(addr: dev->mmio + S626_P_GPIO); |
1518 | /* Assert ADC Start command */ |
1519 | writel(val: gpio_image & ~S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1520 | /* and stretch it out */ |
1521 | writel(val: gpio_image & ~S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1522 | writel(val: gpio_image & ~S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1523 | /* Negate ADC Start command */ |
1524 | writel(val: gpio_image | S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1525 | |
1526 | /* |
1527 | * Wait for ADC to complete (GPIO2 is asserted high when |
1528 | * ADC not busy) and for data from previous conversion to |
1529 | * shift into FB BUFFER 1 register. |
1530 | */ |
1531 | |
1532 | /* Wait for ADC done */ |
1533 | ret = comedi_timeout(dev, s, insn, cb: s626_ai_eoc, context: 0); |
1534 | if (ret) |
1535 | return ret; |
1536 | |
1537 | /* Fetch ADC data */ |
1538 | if (n != 0) { |
1539 | tmp = readl(addr: dev->mmio + S626_P_FB_BUFFER1); |
1540 | data[n - 1] = s626_ai_reg_to_uint(data: tmp); |
1541 | } |
1542 | |
1543 | /* |
1544 | * Allow the ADC to stabilize for 4 microseconds before |
1545 | * starting the next (final) conversion. This delay is |
1546 | * necessary to allow sufficient time between last |
1547 | * conversion finished and the start of the next |
1548 | * conversion. Without this delay, the last conversion's |
1549 | * data value is sometimes set to the previous |
1550 | * conversion's data value. |
1551 | */ |
1552 | udelay(4); |
1553 | } |
1554 | |
1555 | /* |
1556 | * Start a dummy conversion to cause the data from the |
1557 | * previous conversion to be shifted in. |
1558 | */ |
1559 | gpio_image = readl(addr: dev->mmio + S626_P_GPIO); |
1560 | /* Assert ADC Start command */ |
1561 | writel(val: gpio_image & ~S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1562 | /* and stretch it out */ |
1563 | writel(val: gpio_image & ~S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1564 | writel(val: gpio_image & ~S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1565 | /* Negate ADC Start command */ |
1566 | writel(val: gpio_image | S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
1567 | |
1568 | /* Wait for the data to arrive in FB BUFFER 1 register. */ |
1569 | |
1570 | /* Wait for ADC done */ |
1571 | ret = comedi_timeout(dev, s, insn, cb: s626_ai_eoc, context: 0); |
1572 | if (ret) |
1573 | return ret; |
1574 | |
1575 | /* Fetch ADC data from audio interface's input shift register. */ |
1576 | |
1577 | /* Fetch ADC data */ |
1578 | if (n != 0) { |
1579 | tmp = readl(addr: dev->mmio + S626_P_FB_BUFFER1); |
1580 | data[n - 1] = s626_ai_reg_to_uint(data: tmp); |
1581 | } |
1582 | |
1583 | return n; |
1584 | } |
1585 | |
1586 | static int s626_ai_load_polllist(u8 *ppl, struct comedi_cmd *cmd) |
1587 | { |
1588 | int n; |
1589 | |
1590 | for (n = 0; n < cmd->chanlist_len; n++) { |
1591 | if (CR_RANGE(cmd->chanlist[n]) == 0) |
1592 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V; |
1593 | else |
1594 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V; |
1595 | } |
1596 | if (n != 0) |
1597 | ppl[n - 1] |= S626_EOPL; |
1598 | |
1599 | return n; |
1600 | } |
1601 | |
1602 | static int s626_ai_inttrig(struct comedi_device *dev, |
1603 | struct comedi_subdevice *s, |
1604 | unsigned int trig_num) |
1605 | { |
1606 | struct comedi_cmd *cmd = &s->async->cmd; |
1607 | |
1608 | if (trig_num != cmd->start_arg) |
1609 | return -EINVAL; |
1610 | |
1611 | /* Start executing the RPS program */ |
1612 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
1613 | |
1614 | s->async->inttrig = NULL; |
1615 | |
1616 | return 1; |
1617 | } |
1618 | |
1619 | /* |
1620 | * This function doesn't require a particular form, this is just what |
1621 | * happens to be used in some of the drivers. It should convert ns |
1622 | * nanoseconds to a counter value suitable for programming the device. |
1623 | * Also, it should adjust ns so that it cooresponds to the actual time |
1624 | * that the device will use. |
1625 | */ |
1626 | static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags) |
1627 | { |
1628 | int divider, base; |
1629 | |
1630 | base = 500; /* 2MHz internal clock */ |
1631 | |
1632 | switch (flags & CMDF_ROUND_MASK) { |
1633 | case CMDF_ROUND_NEAREST: |
1634 | default: |
1635 | divider = DIV_ROUND_CLOSEST(*nanosec, base); |
1636 | break; |
1637 | case CMDF_ROUND_DOWN: |
1638 | divider = (*nanosec) / base; |
1639 | break; |
1640 | case CMDF_ROUND_UP: |
1641 | divider = DIV_ROUND_UP(*nanosec, base); |
1642 | break; |
1643 | } |
1644 | |
1645 | *nanosec = base * divider; |
1646 | return divider - 1; |
1647 | } |
1648 | |
1649 | static void s626_timer_load(struct comedi_device *dev, |
1650 | unsigned int chan, int tick) |
1651 | { |
1652 | u16 setup = |
1653 | /* Preload upon index. */ |
1654 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
1655 | /* Disable hardware index. */ |
1656 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
1657 | /* Operating mode is Timer. */ |
1658 | S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) | |
1659 | /* Count direction is Down. */ |
1660 | S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) | |
1661 | /* Clock multiplier is 1x. */ |
1662 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
1663 | /* Enabled by index */ |
1664 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); |
1665 | u16 value_latchsrc = S626_LATCHSRC_A_INDXA; |
1666 | /* uint16_t enab = S626_CLKENAB_ALWAYS; */ |
1667 | |
1668 | s626_set_mode(dev, chan, setup, disable_int_src: false); |
1669 | |
1670 | /* Set the preload register */ |
1671 | s626_preload(dev, chan, value: tick); |
1672 | |
1673 | /* |
1674 | * Software index pulse forces the preload register to load |
1675 | * into the counter |
1676 | */ |
1677 | s626_set_load_trig(dev, chan, trig: 0); |
1678 | s626_pulse_index(dev, chan); |
1679 | |
1680 | /* set reload on counter overflow */ |
1681 | s626_set_load_trig(dev, chan, trig: 1); |
1682 | |
1683 | /* set interrupt on overflow */ |
1684 | s626_set_int_src(dev, chan, S626_INTSRC_OVER); |
1685 | |
1686 | s626_set_latch_source(dev, chan, value: value_latchsrc); |
1687 | /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */ |
1688 | } |
1689 | |
1690 | /* TO COMPLETE */ |
1691 | static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
1692 | { |
1693 | struct s626_private *devpriv = dev->private; |
1694 | u8 ppl[16]; |
1695 | struct comedi_cmd *cmd = &s->async->cmd; |
1696 | int tick; |
1697 | |
1698 | if (devpriv->ai_cmd_running) { |
1699 | dev_err(dev->class_dev, |
1700 | "%s: Another ai_cmd is running\n" , __func__); |
1701 | return -EBUSY; |
1702 | } |
1703 | /* disable interrupt */ |
1704 | writel(val: 0, addr: dev->mmio + S626_P_IER); |
1705 | |
1706 | /* clear interrupt request */ |
1707 | writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, addr: dev->mmio + S626_P_ISR); |
1708 | |
1709 | /* clear any pending interrupt */ |
1710 | s626_dio_clear_irq(dev); |
1711 | /* s626_enc_clear_irq(dev); */ |
1712 | |
1713 | /* reset ai_cmd_running flag */ |
1714 | devpriv->ai_cmd_running = 0; |
1715 | |
1716 | s626_ai_load_polllist(ppl, cmd); |
1717 | devpriv->ai_cmd_running = 1; |
1718 | devpriv->ai_convert_count = 0; |
1719 | |
1720 | switch (cmd->scan_begin_src) { |
1721 | case TRIG_FOLLOW: |
1722 | break; |
1723 | case TRIG_TIMER: |
1724 | /* |
1725 | * set a counter to generate adc trigger at scan_begin_arg |
1726 | * interval |
1727 | */ |
1728 | tick = s626_ns_to_timer(nanosec: &cmd->scan_begin_arg, flags: cmd->flags); |
1729 | |
1730 | /* load timer value and enable interrupt */ |
1731 | s626_timer_load(dev, chan: 5, tick); |
1732 | s626_set_enable(dev, chan: 5, S626_CLKENAB_ALWAYS); |
1733 | break; |
1734 | case TRIG_EXT: |
1735 | /* set the digital line and interrupt for scan trigger */ |
1736 | if (cmd->start_src != TRIG_EXT) |
1737 | s626_dio_set_irq(dev, chan: cmd->scan_begin_arg); |
1738 | break; |
1739 | } |
1740 | |
1741 | switch (cmd->convert_src) { |
1742 | case TRIG_NOW: |
1743 | break; |
1744 | case TRIG_TIMER: |
1745 | /* |
1746 | * set a counter to generate adc trigger at convert_arg |
1747 | * interval |
1748 | */ |
1749 | tick = s626_ns_to_timer(nanosec: &cmd->convert_arg, flags: cmd->flags); |
1750 | |
1751 | /* load timer value and enable interrupt */ |
1752 | s626_timer_load(dev, chan: 4, tick); |
1753 | s626_set_enable(dev, chan: 4, S626_CLKENAB_INDEX); |
1754 | break; |
1755 | case TRIG_EXT: |
1756 | /* set the digital line and interrupt for convert trigger */ |
1757 | if (cmd->scan_begin_src != TRIG_EXT && |
1758 | cmd->start_src == TRIG_EXT) |
1759 | s626_dio_set_irq(dev, chan: cmd->convert_arg); |
1760 | break; |
1761 | } |
1762 | |
1763 | s626_reset_adc(dev, ppl); |
1764 | |
1765 | switch (cmd->start_src) { |
1766 | case TRIG_NOW: |
1767 | /* Trigger ADC scan loop start */ |
1768 | /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */ |
1769 | |
1770 | /* Start executing the RPS program */ |
1771 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
1772 | s->async->inttrig = NULL; |
1773 | break; |
1774 | case TRIG_EXT: |
1775 | /* configure DIO channel for acquisition trigger */ |
1776 | s626_dio_set_irq(dev, chan: cmd->start_arg); |
1777 | s->async->inttrig = NULL; |
1778 | break; |
1779 | case TRIG_INT: |
1780 | s->async->inttrig = s626_ai_inttrig; |
1781 | break; |
1782 | } |
1783 | |
1784 | /* enable interrupt */ |
1785 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, addr: dev->mmio + S626_P_IER); |
1786 | |
1787 | return 0; |
1788 | } |
1789 | |
1790 | static int s626_ai_cmdtest(struct comedi_device *dev, |
1791 | struct comedi_subdevice *s, struct comedi_cmd *cmd) |
1792 | { |
1793 | int err = 0; |
1794 | unsigned int arg; |
1795 | |
1796 | /* Step 1 : check if triggers are trivially valid */ |
1797 | |
1798 | err |= comedi_check_trigger_src(src: &cmd->start_src, |
1799 | TRIG_NOW | TRIG_INT | TRIG_EXT); |
1800 | err |= comedi_check_trigger_src(src: &cmd->scan_begin_src, |
1801 | TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW); |
1802 | err |= comedi_check_trigger_src(src: &cmd->convert_src, |
1803 | TRIG_TIMER | TRIG_EXT | TRIG_NOW); |
1804 | err |= comedi_check_trigger_src(src: &cmd->scan_end_src, TRIG_COUNT); |
1805 | err |= comedi_check_trigger_src(src: &cmd->stop_src, TRIG_COUNT | TRIG_NONE); |
1806 | |
1807 | if (err) |
1808 | return 1; |
1809 | |
1810 | /* Step 2a : make sure trigger sources are unique */ |
1811 | |
1812 | err |= comedi_check_trigger_is_unique(src: cmd->start_src); |
1813 | err |= comedi_check_trigger_is_unique(src: cmd->scan_begin_src); |
1814 | err |= comedi_check_trigger_is_unique(src: cmd->convert_src); |
1815 | err |= comedi_check_trigger_is_unique(src: cmd->stop_src); |
1816 | |
1817 | /* Step 2b : and mutually compatible */ |
1818 | |
1819 | if (err) |
1820 | return 2; |
1821 | |
1822 | /* Step 3: check if arguments are trivially valid */ |
1823 | |
1824 | switch (cmd->start_src) { |
1825 | case TRIG_NOW: |
1826 | case TRIG_INT: |
1827 | err |= comedi_check_trigger_arg_is(arg: &cmd->start_arg, val: 0); |
1828 | break; |
1829 | case TRIG_EXT: |
1830 | err |= comedi_check_trigger_arg_max(arg: &cmd->start_arg, val: 39); |
1831 | break; |
1832 | } |
1833 | |
1834 | if (cmd->scan_begin_src == TRIG_EXT) |
1835 | err |= comedi_check_trigger_arg_max(arg: &cmd->scan_begin_arg, val: 39); |
1836 | if (cmd->convert_src == TRIG_EXT) |
1837 | err |= comedi_check_trigger_arg_max(arg: &cmd->convert_arg, val: 39); |
1838 | |
1839 | #define S626_MAX_SPEED 200000 /* in nanoseconds */ |
1840 | #define S626_MIN_SPEED 2000000000 /* in nanoseconds */ |
1841 | |
1842 | if (cmd->scan_begin_src == TRIG_TIMER) { |
1843 | err |= comedi_check_trigger_arg_min(arg: &cmd->scan_begin_arg, |
1844 | S626_MAX_SPEED); |
1845 | err |= comedi_check_trigger_arg_max(arg: &cmd->scan_begin_arg, |
1846 | S626_MIN_SPEED); |
1847 | } else { |
1848 | /* |
1849 | * external trigger |
1850 | * should be level/edge, hi/lo specification here |
1851 | * should specify multiple external triggers |
1852 | * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9); |
1853 | */ |
1854 | } |
1855 | if (cmd->convert_src == TRIG_TIMER) { |
1856 | err |= comedi_check_trigger_arg_min(arg: &cmd->convert_arg, |
1857 | S626_MAX_SPEED); |
1858 | err |= comedi_check_trigger_arg_max(arg: &cmd->convert_arg, |
1859 | S626_MIN_SPEED); |
1860 | } else { |
1861 | /* |
1862 | * external trigger - see above |
1863 | * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9); |
1864 | */ |
1865 | } |
1866 | |
1867 | err |= comedi_check_trigger_arg_is(arg: &cmd->scan_end_arg, |
1868 | val: cmd->chanlist_len); |
1869 | |
1870 | if (cmd->stop_src == TRIG_COUNT) |
1871 | err |= comedi_check_trigger_arg_min(arg: &cmd->stop_arg, val: 1); |
1872 | else /* TRIG_NONE */ |
1873 | err |= comedi_check_trigger_arg_is(arg: &cmd->stop_arg, val: 0); |
1874 | |
1875 | if (err) |
1876 | return 3; |
1877 | |
1878 | /* step 4: fix up any arguments */ |
1879 | |
1880 | if (cmd->scan_begin_src == TRIG_TIMER) { |
1881 | arg = cmd->scan_begin_arg; |
1882 | s626_ns_to_timer(nanosec: &arg, flags: cmd->flags); |
1883 | err |= comedi_check_trigger_arg_is(arg: &cmd->scan_begin_arg, val: arg); |
1884 | } |
1885 | |
1886 | if (cmd->convert_src == TRIG_TIMER) { |
1887 | arg = cmd->convert_arg; |
1888 | s626_ns_to_timer(nanosec: &arg, flags: cmd->flags); |
1889 | err |= comedi_check_trigger_arg_is(arg: &cmd->convert_arg, val: arg); |
1890 | |
1891 | if (cmd->scan_begin_src == TRIG_TIMER) { |
1892 | arg = cmd->convert_arg * cmd->scan_end_arg; |
1893 | err |= comedi_check_trigger_arg_min( |
1894 | arg: &cmd->scan_begin_arg, val: arg); |
1895 | } |
1896 | } |
1897 | |
1898 | if (err) |
1899 | return 4; |
1900 | |
1901 | return 0; |
1902 | } |
1903 | |
1904 | static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
1905 | { |
1906 | struct s626_private *devpriv = dev->private; |
1907 | |
1908 | /* Stop RPS program in case it is currently running */ |
1909 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
1910 | |
1911 | /* disable master interrupt */ |
1912 | writel(val: 0, addr: dev->mmio + S626_P_IER); |
1913 | |
1914 | devpriv->ai_cmd_running = 0; |
1915 | |
1916 | return 0; |
1917 | } |
1918 | |
1919 | static int s626_ao_insn_write(struct comedi_device *dev, |
1920 | struct comedi_subdevice *s, |
1921 | struct comedi_insn *insn, |
1922 | unsigned int *data) |
1923 | { |
1924 | unsigned int chan = CR_CHAN(insn->chanspec); |
1925 | int i; |
1926 | |
1927 | for (i = 0; i < insn->n; i++) { |
1928 | s16 dacdata = (s16)data[i]; |
1929 | int ret; |
1930 | |
1931 | dacdata -= (0x1fff); |
1932 | |
1933 | ret = s626_set_dac(dev, chan, dacdata); |
1934 | if (ret) |
1935 | return ret; |
1936 | |
1937 | s->readback[chan] = data[i]; |
1938 | } |
1939 | |
1940 | return insn->n; |
1941 | } |
1942 | |
1943 | /* *************** DIGITAL I/O FUNCTIONS *************** */ |
1944 | |
1945 | /* |
1946 | * All DIO functions address a group of DIO channels by means of |
1947 | * "group" argument. group may be 0, 1 or 2, which correspond to DIO |
1948 | * ports A, B and C, respectively. |
1949 | */ |
1950 | |
1951 | static void s626_dio_init(struct comedi_device *dev) |
1952 | { |
1953 | u16 group; |
1954 | |
1955 | /* Prepare to treat writes to WRCapSel as capture disables. */ |
1956 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
1957 | |
1958 | /* For each group of sixteen channels ... */ |
1959 | for (group = 0; group < S626_DIO_BANKS; group++) { |
1960 | /* Disable all interrupts */ |
1961 | s626_debi_write(dev, S626_LP_WRINTSEL(group), wdata: 0); |
1962 | /* Disable all event captures */ |
1963 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), wdata: 0xffff); |
1964 | /* Init all DIOs to default edge polarity */ |
1965 | s626_debi_write(dev, S626_LP_WREDGSEL(group), wdata: 0); |
1966 | /* Program all outputs to inactive state */ |
1967 | s626_debi_write(dev, S626_LP_WRDOUT(group), wdata: 0); |
1968 | } |
1969 | } |
1970 | |
1971 | static int s626_dio_insn_bits(struct comedi_device *dev, |
1972 | struct comedi_subdevice *s, |
1973 | struct comedi_insn *insn, |
1974 | unsigned int *data) |
1975 | { |
1976 | unsigned long group = (unsigned long)s->private; |
1977 | |
1978 | if (comedi_dio_update_state(s, data)) |
1979 | s626_debi_write(dev, S626_LP_WRDOUT(group), wdata: s->state); |
1980 | |
1981 | data[1] = s626_debi_read(dev, S626_LP_RDDIN(group)); |
1982 | |
1983 | return insn->n; |
1984 | } |
1985 | |
1986 | static int s626_dio_insn_config(struct comedi_device *dev, |
1987 | struct comedi_subdevice *s, |
1988 | struct comedi_insn *insn, |
1989 | unsigned int *data) |
1990 | { |
1991 | unsigned long group = (unsigned long)s->private; |
1992 | int ret; |
1993 | |
1994 | ret = comedi_dio_insn_config(dev, s, insn, data, mask: 0); |
1995 | if (ret) |
1996 | return ret; |
1997 | |
1998 | s626_debi_write(dev, S626_LP_WRDOUT(group), wdata: s->io_bits); |
1999 | |
2000 | return insn->n; |
2001 | } |
2002 | |
2003 | /* |
2004 | * Now this function initializes the value of the counter (data[0]) |
2005 | * and set the subdevice. To complete with trigger and interrupt |
2006 | * configuration. |
2007 | * |
2008 | * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating |
2009 | * what is being configured, but this function appears to be using data[0] |
2010 | * as a variable. |
2011 | */ |
2012 | static int s626_enc_insn_config(struct comedi_device *dev, |
2013 | struct comedi_subdevice *s, |
2014 | struct comedi_insn *insn, unsigned int *data) |
2015 | { |
2016 | unsigned int chan = CR_CHAN(insn->chanspec); |
2017 | u16 setup = |
2018 | /* Preload upon index. */ |
2019 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
2020 | /* Disable hardware index. */ |
2021 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
2022 | /* Operating mode is Counter. */ |
2023 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
2024 | /* Active high clock. */ |
2025 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
2026 | /* Clock multiplier is 1x. */ |
2027 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
2028 | /* Enabled by index */ |
2029 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); |
2030 | /* uint16_t disable_int_src = true; */ |
2031 | /* uint32_t Preloadvalue; //Counter initial value */ |
2032 | u16 value_latchsrc = S626_LATCHSRC_AB_READ; |
2033 | u16 enab = S626_CLKENAB_ALWAYS; |
2034 | |
2035 | /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */ |
2036 | |
2037 | s626_set_mode(dev, chan, setup, disable_int_src: true); |
2038 | s626_preload(dev, chan, value: data[0]); |
2039 | s626_pulse_index(dev, chan); |
2040 | s626_set_latch_source(dev, chan, value: value_latchsrc); |
2041 | s626_set_enable(dev, chan, enab: (enab != 0)); |
2042 | |
2043 | return insn->n; |
2044 | } |
2045 | |
2046 | static int s626_enc_insn_read(struct comedi_device *dev, |
2047 | struct comedi_subdevice *s, |
2048 | struct comedi_insn *insn, |
2049 | unsigned int *data) |
2050 | { |
2051 | unsigned int chan = CR_CHAN(insn->chanspec); |
2052 | u16 cntr_latch_reg = S626_LP_CNTR(chan); |
2053 | int i; |
2054 | |
2055 | for (i = 0; i < insn->n; i++) { |
2056 | unsigned int val; |
2057 | |
2058 | /* |
2059 | * Read the counter's output latch LSW/MSW. |
2060 | * Latches on LSW read. |
2061 | */ |
2062 | val = s626_debi_read(dev, addr: cntr_latch_reg); |
2063 | val |= (s626_debi_read(dev, addr: cntr_latch_reg + 2) << 16); |
2064 | data[i] = val; |
2065 | } |
2066 | |
2067 | return insn->n; |
2068 | } |
2069 | |
2070 | static int s626_enc_insn_write(struct comedi_device *dev, |
2071 | struct comedi_subdevice *s, |
2072 | struct comedi_insn *insn, unsigned int *data) |
2073 | { |
2074 | unsigned int chan = CR_CHAN(insn->chanspec); |
2075 | |
2076 | /* Set the preload register */ |
2077 | s626_preload(dev, chan, value: data[0]); |
2078 | |
2079 | /* |
2080 | * Software index pulse forces the preload register to load |
2081 | * into the counter |
2082 | */ |
2083 | s626_set_load_trig(dev, chan, trig: 0); |
2084 | s626_pulse_index(dev, chan); |
2085 | s626_set_load_trig(dev, chan, trig: 2); |
2086 | |
2087 | return 1; |
2088 | } |
2089 | |
2090 | static void s626_write_misc2(struct comedi_device *dev, u16 new_image) |
2091 | { |
2092 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE); |
2093 | s626_debi_write(dev, S626_LP_WRMISC2, wdata: new_image); |
2094 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE); |
2095 | } |
2096 | |
2097 | static void s626_counters_init(struct comedi_device *dev) |
2098 | { |
2099 | int chan; |
2100 | u16 setup = |
2101 | /* Preload upon index. */ |
2102 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
2103 | /* Disable hardware index. */ |
2104 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
2105 | /* Operating mode is counter. */ |
2106 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
2107 | /* Active high clock. */ |
2108 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
2109 | /* Clock multiplier is 1x. */ |
2110 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
2111 | /* Enabled by index */ |
2112 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); |
2113 | |
2114 | /* |
2115 | * Disable all counter interrupts and clear any captured counter events. |
2116 | */ |
2117 | for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) { |
2118 | s626_set_mode(dev, chan, setup, disable_int_src: true); |
2119 | s626_set_int_src(dev, chan, int_source: 0); |
2120 | s626_reset_cap_flags(dev, chan); |
2121 | s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS); |
2122 | } |
2123 | } |
2124 | |
2125 | static int s626_allocate_dma_buffers(struct comedi_device *dev) |
2126 | { |
2127 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
2128 | struct s626_private *devpriv = dev->private; |
2129 | void *addr; |
2130 | dma_addr_t appdma; |
2131 | |
2132 | addr = dma_alloc_coherent(dev: &pcidev->dev, S626_DMABUF_SIZE, dma_handle: &appdma, |
2133 | GFP_KERNEL); |
2134 | if (!addr) |
2135 | return -ENOMEM; |
2136 | devpriv->ana_buf.logical_base = addr; |
2137 | devpriv->ana_buf.physical_base = appdma; |
2138 | |
2139 | addr = dma_alloc_coherent(dev: &pcidev->dev, S626_DMABUF_SIZE, dma_handle: &appdma, |
2140 | GFP_KERNEL); |
2141 | if (!addr) |
2142 | return -ENOMEM; |
2143 | devpriv->rps_buf.logical_base = addr; |
2144 | devpriv->rps_buf.physical_base = appdma; |
2145 | |
2146 | return 0; |
2147 | } |
2148 | |
2149 | static void s626_free_dma_buffers(struct comedi_device *dev) |
2150 | { |
2151 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
2152 | struct s626_private *devpriv = dev->private; |
2153 | |
2154 | if (!devpriv) |
2155 | return; |
2156 | |
2157 | if (devpriv->rps_buf.logical_base) |
2158 | dma_free_coherent(dev: &pcidev->dev, S626_DMABUF_SIZE, |
2159 | cpu_addr: devpriv->rps_buf.logical_base, |
2160 | dma_handle: devpriv->rps_buf.physical_base); |
2161 | if (devpriv->ana_buf.logical_base) |
2162 | dma_free_coherent(dev: &pcidev->dev, S626_DMABUF_SIZE, |
2163 | cpu_addr: devpriv->ana_buf.logical_base, |
2164 | dma_handle: devpriv->ana_buf.physical_base); |
2165 | } |
2166 | |
2167 | static int s626_initialize(struct comedi_device *dev) |
2168 | { |
2169 | struct s626_private *devpriv = dev->private; |
2170 | dma_addr_t phys_buf; |
2171 | u16 chan; |
2172 | int i; |
2173 | int ret; |
2174 | |
2175 | /* Enable DEBI and audio pins, enable I2C interface */ |
2176 | s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C, |
2177 | S626_P_MC1); |
2178 | |
2179 | /* |
2180 | * Configure DEBI operating mode |
2181 | * |
2182 | * Local bus is 16 bits wide |
2183 | * Declare DEBI transfer timeout interval |
2184 | * Set up byte lane steering |
2185 | * Intel-compatible local bus (DEBI never times out) |
2186 | */ |
2187 | writel(S626_DEBI_CFG_SLAVE16 | |
2188 | (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP | |
2189 | S626_DEBI_CFG_INTEL, addr: dev->mmio + S626_P_DEBICFG); |
2190 | |
2191 | /* Disable MMU paging */ |
2192 | writel(S626_DEBI_PAGE_DISABLE, addr: dev->mmio + S626_P_DEBIPAGE); |
2193 | |
2194 | /* Init GPIO so that ADC Start* is negated */ |
2195 | writel(S626_GPIO_BASE | S626_GPIO1_HI, addr: dev->mmio + S626_P_GPIO); |
2196 | |
2197 | /* I2C device address for onboard eeprom (revb) */ |
2198 | devpriv->i2c_adrs = 0xA0; |
2199 | |
2200 | /* |
2201 | * Issue an I2C ABORT command to halt any I2C |
2202 | * operation in progress and reset BUSY flag. |
2203 | */ |
2204 | writel(S626_I2C_CLKSEL | S626_I2C_ABORT, |
2205 | addr: dev->mmio + S626_P_I2CSTAT); |
2206 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
2207 | ret = comedi_timeout(dev, NULL, NULL, cb: s626_i2c_handshake_eoc, context: 0); |
2208 | if (ret) |
2209 | return ret; |
2210 | |
2211 | /* |
2212 | * Per SAA7146 data sheet, write to STATUS |
2213 | * reg twice to reset all I2C error flags. |
2214 | */ |
2215 | for (i = 0; i < 2; i++) { |
2216 | writel(S626_I2C_CLKSEL, addr: dev->mmio + S626_P_I2CSTAT); |
2217 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
2218 | ret = comedi_timeout(dev, NULL, |
2219 | NULL, cb: s626_i2c_handshake_eoc, context: 0); |
2220 | if (ret) |
2221 | return ret; |
2222 | } |
2223 | |
2224 | /* |
2225 | * Init audio interface functional attributes: set DAC/ADC |
2226 | * serial clock rates, invert DAC serial clock so that |
2227 | * DAC data setup times are satisfied, enable DAC serial |
2228 | * clock out. |
2229 | */ |
2230 | writel(S626_ACON2_INIT, addr: dev->mmio + S626_P_ACON2); |
2231 | |
2232 | /* |
2233 | * Set up TSL1 slot list, which is used to control the |
2234 | * accumulation of ADC data: S626_RSD1 = shift data in on SD1. |
2235 | * S626_SIB_A1 = store data uint8_t at next available location |
2236 | * in FB BUFFER1 register. |
2237 | */ |
2238 | writel(S626_RSD1 | S626_SIB_A1, addr: dev->mmio + S626_P_TSL1); |
2239 | writel(S626_RSD1 | S626_SIB_A1 | S626_EOS, |
2240 | addr: dev->mmio + S626_P_TSL1 + 4); |
2241 | |
2242 | /* Enable TSL1 slot list so that it executes all the time */ |
2243 | writel(S626_ACON1_ADCSTART, addr: dev->mmio + S626_P_ACON1); |
2244 | |
2245 | /* |
2246 | * Initialize RPS registers used for ADC |
2247 | */ |
2248 | |
2249 | /* Physical start of RPS program */ |
2250 | writel(val: (u32)devpriv->rps_buf.physical_base, |
2251 | addr: dev->mmio + S626_P_RPSADDR1); |
2252 | /* RPS program performs no explicit mem writes */ |
2253 | writel(val: 0, addr: dev->mmio + S626_P_RPSPAGE1); |
2254 | /* Disable RPS timeouts */ |
2255 | writel(val: 0, addr: dev->mmio + S626_P_RPS1_TOUT); |
2256 | |
2257 | #if 0 |
2258 | /* |
2259 | * SAA7146 BUG WORKAROUND |
2260 | * |
2261 | * Initialize SAA7146 ADC interface to a known state by |
2262 | * invoking ADCs until FB BUFFER 1 register shows that it |
2263 | * is correctly receiving ADC data. This is necessary |
2264 | * because the SAA7146 ADC interface does not start up in |
2265 | * a defined state after a PCI reset. |
2266 | */ |
2267 | { |
2268 | struct comedi_subdevice *s = dev->read_subdev; |
2269 | u8 poll_list; |
2270 | u16 adc_data; |
2271 | u16 start_val; |
2272 | u16 index; |
2273 | unsigned int data[16]; |
2274 | |
2275 | /* Create a simple polling list for analog input channel 0 */ |
2276 | poll_list = S626_EOPL; |
2277 | s626_reset_adc(dev, &poll_list); |
2278 | |
2279 | /* Get initial ADC value */ |
2280 | s626_ai_rinsn(dev, s, NULL, data); |
2281 | start_val = data[0]; |
2282 | |
2283 | /* |
2284 | * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED |
2285 | * EXECUTION. |
2286 | * |
2287 | * Invoke ADCs until the new ADC value differs from the initial |
2288 | * value or a timeout occurs. The timeout protects against the |
2289 | * possibility that the driver is restarting and the ADC data is |
2290 | * a fixed value resulting from the applied ADC analog input |
2291 | * being unusually quiet or at the rail. |
2292 | */ |
2293 | for (index = 0; index < 500; index++) { |
2294 | s626_ai_rinsn(dev, s, NULL, data); |
2295 | adc_data = data[0]; |
2296 | if (adc_data != start_val) |
2297 | break; |
2298 | } |
2299 | } |
2300 | #endif /* SAA7146 BUG WORKAROUND */ |
2301 | |
2302 | /* |
2303 | * Initialize the DAC interface |
2304 | */ |
2305 | |
2306 | /* |
2307 | * Init Audio2's output DMAC attributes: |
2308 | * burst length = 1 DWORD |
2309 | * threshold = 1 DWORD. |
2310 | */ |
2311 | writel(val: 0, addr: dev->mmio + S626_P_PCI_BT_A); |
2312 | |
2313 | /* |
2314 | * Init Audio2's output DMA physical addresses. The protection |
2315 | * address is set to 1 DWORD past the base address so that a |
2316 | * single DWORD will be transferred each time a DMA transfer is |
2317 | * enabled. |
2318 | */ |
2319 | phys_buf = devpriv->ana_buf.physical_base + |
2320 | (S626_DAC_WDMABUF_OS * sizeof(u32)); |
2321 | writel(val: (u32)phys_buf, addr: dev->mmio + S626_P_BASEA2_OUT); |
2322 | writel(val: (u32)(phys_buf + sizeof(u32)), |
2323 | addr: dev->mmio + S626_P_PROTA2_OUT); |
2324 | |
2325 | /* |
2326 | * Cache Audio2's output DMA buffer logical address. This is |
2327 | * where DAC data is buffered for A2 output DMA transfers. |
2328 | */ |
2329 | devpriv->dac_wbuf = (u32 *)devpriv->ana_buf.logical_base + |
2330 | S626_DAC_WDMABUF_OS; |
2331 | |
2332 | /* |
2333 | * Audio2's output channels does not use paging. The |
2334 | * protection violation handling bit is set so that the |
2335 | * DMAC will automatically halt and its PCI address pointer |
2336 | * will be reset when the protection address is reached. |
2337 | */ |
2338 | writel(val: 8, addr: dev->mmio + S626_P_PAGEA2_OUT); |
2339 | |
2340 | /* |
2341 | * Initialize time slot list 2 (TSL2), which is used to control |
2342 | * the clock generation for and serialization of data to be sent |
2343 | * to the DAC devices. Slot 0 is a NOP that is used to trap TSL |
2344 | * execution; this permits other slots to be safely modified |
2345 | * without first turning off the TSL sequencer (which is |
2346 | * apparently impossible to do). Also, SD3 (which is driven by a |
2347 | * pull-up resistor) is shifted in and stored to the MSB of |
2348 | * FB_BUFFER2 to be used as evidence that the slot sequence has |
2349 | * not yet finished executing. |
2350 | */ |
2351 | |
2352 | /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */ |
2353 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS, |
2354 | addr: dev->mmio + S626_VECTPORT(0)); |
2355 | |
2356 | /* |
2357 | * Initialize slot 1, which is constant. Slot 1 causes a |
2358 | * DWORD to be transferred from audio channel 2's output FIFO |
2359 | * to the FIFO's output buffer so that it can be serialized |
2360 | * and sent to the DAC during subsequent slots. All remaining |
2361 | * slots are dynamically populated as required by the target |
2362 | * DAC device. |
2363 | */ |
2364 | |
2365 | /* Slot 1: Fetch DWORD from Audio2's output FIFO */ |
2366 | writel(S626_LF_A2, addr: dev->mmio + S626_VECTPORT(1)); |
2367 | |
2368 | /* Start DAC's audio interface (TSL2) running */ |
2369 | writel(S626_ACON1_DACSTART, addr: dev->mmio + S626_P_ACON1); |
2370 | |
2371 | /* |
2372 | * Init Trim DACs to calibrated values. Do it twice because the |
2373 | * SAA7146 audio channel does not always reset properly and |
2374 | * sometimes causes the first few TrimDAC writes to malfunction. |
2375 | */ |
2376 | s626_load_trim_dacs(dev); |
2377 | ret = s626_load_trim_dacs(dev); |
2378 | if (ret) |
2379 | return ret; |
2380 | |
2381 | /* |
2382 | * Manually init all gate array hardware in case this is a soft |
2383 | * reset (we have no way of determining whether this is a warm |
2384 | * or cold start). This is necessary because the gate array will |
2385 | * reset only in response to a PCI hard reset; there is no soft |
2386 | * reset function. |
2387 | */ |
2388 | |
2389 | /* |
2390 | * Init all DAC outputs to 0V and init all DAC setpoint and |
2391 | * polarity images. |
2392 | */ |
2393 | for (chan = 0; chan < S626_DAC_CHANNELS; chan++) { |
2394 | ret = s626_set_dac(dev, chan, dacdata: 0); |
2395 | if (ret) |
2396 | return ret; |
2397 | } |
2398 | |
2399 | /* Init counters */ |
2400 | s626_counters_init(dev); |
2401 | |
2402 | /* |
2403 | * Without modifying the state of the Battery Backup enab, disable |
2404 | * the watchdog timer, set DIO channels 0-5 to operate in the |
2405 | * standard DIO (vs. counter overflow) mode, disable the battery |
2406 | * charger, and reset the watchdog interval selector to zero. |
2407 | */ |
2408 | s626_write_misc2(dev, new_image: (s626_debi_read(dev, S626_LP_RDMISC2) & |
2409 | S626_MISC2_BATT_ENABLE)); |
2410 | |
2411 | /* Initialize the digital I/O subsystem */ |
2412 | s626_dio_init(dev); |
2413 | |
2414 | return 0; |
2415 | } |
2416 | |
2417 | static int s626_auto_attach(struct comedi_device *dev, |
2418 | unsigned long context_unused) |
2419 | { |
2420 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
2421 | struct s626_private *devpriv; |
2422 | struct comedi_subdevice *s; |
2423 | int ret; |
2424 | |
2425 | devpriv = comedi_alloc_devpriv(dev, size: sizeof(*devpriv)); |
2426 | if (!devpriv) |
2427 | return -ENOMEM; |
2428 | |
2429 | ret = comedi_pci_enable(dev); |
2430 | if (ret) |
2431 | return ret; |
2432 | |
2433 | dev->mmio = pci_ioremap_bar(pdev: pcidev, bar: 0); |
2434 | if (!dev->mmio) |
2435 | return -ENOMEM; |
2436 | |
2437 | /* disable master interrupt */ |
2438 | writel(val: 0, addr: dev->mmio + S626_P_IER); |
2439 | |
2440 | /* soft reset */ |
2441 | writel(S626_MC1_SOFT_RESET, addr: dev->mmio + S626_P_MC1); |
2442 | |
2443 | /* DMA FIXME DMA// */ |
2444 | |
2445 | ret = s626_allocate_dma_buffers(dev); |
2446 | if (ret) |
2447 | return ret; |
2448 | |
2449 | if (pcidev->irq) { |
2450 | ret = request_irq(irq: pcidev->irq, handler: s626_irq_handler, IRQF_SHARED, |
2451 | name: dev->board_name, dev); |
2452 | |
2453 | if (ret == 0) |
2454 | dev->irq = pcidev->irq; |
2455 | } |
2456 | |
2457 | ret = comedi_alloc_subdevices(dev, num_subdevices: 6); |
2458 | if (ret) |
2459 | return ret; |
2460 | |
2461 | s = &dev->subdevices[0]; |
2462 | /* analog input subdevice */ |
2463 | s->type = COMEDI_SUBD_AI; |
2464 | s->subdev_flags = SDF_READABLE | SDF_DIFF; |
2465 | s->n_chan = S626_ADC_CHANNELS; |
2466 | s->maxdata = 0x3fff; |
2467 | s->range_table = &s626_range_table; |
2468 | s->len_chanlist = S626_ADC_CHANNELS; |
2469 | s->insn_read = s626_ai_insn_read; |
2470 | if (dev->irq) { |
2471 | dev->read_subdev = s; |
2472 | s->subdev_flags |= SDF_CMD_READ; |
2473 | s->do_cmd = s626_ai_cmd; |
2474 | s->do_cmdtest = s626_ai_cmdtest; |
2475 | s->cancel = s626_ai_cancel; |
2476 | } |
2477 | |
2478 | s = &dev->subdevices[1]; |
2479 | /* analog output subdevice */ |
2480 | s->type = COMEDI_SUBD_AO; |
2481 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; |
2482 | s->n_chan = S626_DAC_CHANNELS; |
2483 | s->maxdata = 0x3fff; |
2484 | s->range_table = &range_bipolar10; |
2485 | s->insn_write = s626_ao_insn_write; |
2486 | |
2487 | ret = comedi_alloc_subdev_readback(s); |
2488 | if (ret) |
2489 | return ret; |
2490 | |
2491 | s = &dev->subdevices[2]; |
2492 | /* digital I/O subdevice */ |
2493 | s->type = COMEDI_SUBD_DIO; |
2494 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; |
2495 | s->n_chan = 16; |
2496 | s->maxdata = 1; |
2497 | s->io_bits = 0xffff; |
2498 | s->private = (void *)0; /* DIO group 0 */ |
2499 | s->range_table = &range_digital; |
2500 | s->insn_config = s626_dio_insn_config; |
2501 | s->insn_bits = s626_dio_insn_bits; |
2502 | |
2503 | s = &dev->subdevices[3]; |
2504 | /* digital I/O subdevice */ |
2505 | s->type = COMEDI_SUBD_DIO; |
2506 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; |
2507 | s->n_chan = 16; |
2508 | s->maxdata = 1; |
2509 | s->io_bits = 0xffff; |
2510 | s->private = (void *)1; /* DIO group 1 */ |
2511 | s->range_table = &range_digital; |
2512 | s->insn_config = s626_dio_insn_config; |
2513 | s->insn_bits = s626_dio_insn_bits; |
2514 | |
2515 | s = &dev->subdevices[4]; |
2516 | /* digital I/O subdevice */ |
2517 | s->type = COMEDI_SUBD_DIO; |
2518 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; |
2519 | s->n_chan = 16; |
2520 | s->maxdata = 1; |
2521 | s->io_bits = 0xffff; |
2522 | s->private = (void *)2; /* DIO group 2 */ |
2523 | s->range_table = &range_digital; |
2524 | s->insn_config = s626_dio_insn_config; |
2525 | s->insn_bits = s626_dio_insn_bits; |
2526 | |
2527 | s = &dev->subdevices[5]; |
2528 | /* encoder (counter) subdevice */ |
2529 | s->type = COMEDI_SUBD_COUNTER; |
2530 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL; |
2531 | s->n_chan = S626_ENCODER_CHANNELS; |
2532 | s->maxdata = 0xffffff; |
2533 | s->range_table = &range_unknown; |
2534 | s->insn_config = s626_enc_insn_config; |
2535 | s->insn_read = s626_enc_insn_read; |
2536 | s->insn_write = s626_enc_insn_write; |
2537 | |
2538 | return s626_initialize(dev); |
2539 | } |
2540 | |
2541 | static void s626_detach(struct comedi_device *dev) |
2542 | { |
2543 | struct s626_private *devpriv = dev->private; |
2544 | |
2545 | if (devpriv) { |
2546 | /* stop ai_command */ |
2547 | devpriv->ai_cmd_running = 0; |
2548 | |
2549 | if (dev->mmio) { |
2550 | /* interrupt mask */ |
2551 | /* Disable master interrupt */ |
2552 | writel(val: 0, addr: dev->mmio + S626_P_IER); |
2553 | /* Clear board's IRQ status flag */ |
2554 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, |
2555 | addr: dev->mmio + S626_P_ISR); |
2556 | |
2557 | /* Disable the watchdog timer and battery charger. */ |
2558 | s626_write_misc2(dev, new_image: 0); |
2559 | |
2560 | /* Close all interfaces on 7146 device */ |
2561 | writel(S626_MC1_SHUTDOWN, addr: dev->mmio + S626_P_MC1); |
2562 | writel(S626_ACON1_BASE, addr: dev->mmio + S626_P_ACON1); |
2563 | } |
2564 | } |
2565 | comedi_pci_detach(dev); |
2566 | s626_free_dma_buffers(dev); |
2567 | } |
2568 | |
2569 | static struct comedi_driver s626_driver = { |
2570 | .driver_name = "s626" , |
2571 | .module = THIS_MODULE, |
2572 | .auto_attach = s626_auto_attach, |
2573 | .detach = s626_detach, |
2574 | }; |
2575 | |
2576 | static int s626_pci_probe(struct pci_dev *dev, |
2577 | const struct pci_device_id *id) |
2578 | { |
2579 | return comedi_pci_auto_config(pcidev: dev, driver: &s626_driver, context: id->driver_data); |
2580 | } |
2581 | |
2582 | /* |
2583 | * For devices with vendor:device id == 0x1131:0x7146 you must specify |
2584 | * also subvendor:subdevice ids, because otherwise it will conflict with |
2585 | * Philips SAA7146 media/dvb based cards. |
2586 | */ |
2587 | static const struct pci_device_id s626_pci_table[] = { |
2588 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146, |
2589 | 0x6000, 0x0272) }, |
2590 | { 0 } |
2591 | }; |
2592 | MODULE_DEVICE_TABLE(pci, s626_pci_table); |
2593 | |
2594 | static struct pci_driver s626_pci_driver = { |
2595 | .name = "s626" , |
2596 | .id_table = s626_pci_table, |
2597 | .probe = s626_pci_probe, |
2598 | .remove = comedi_pci_auto_unconfig, |
2599 | }; |
2600 | module_comedi_pci_driver(s626_driver, s626_pci_driver); |
2601 | |
2602 | MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>" ); |
2603 | MODULE_DESCRIPTION("Sensoray 626 Comedi driver module" ); |
2604 | MODULE_LICENSE("GPL" ); |
2605 | |