1	/*
2	* Copyright 2020 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*
22	*/
23	#include "amdgpu.h"
24	#include "soc15.h"
25	#include "soc15d.h"
26
27	#include "gc/gc_9_4_2_offset.h"
28	#include "gc/gc_9_4_2_sh_mask.h"
29	#include "gfx_v9_0.h"
30
31	#include "gfx_v9_4_2.h"
32	#include "amdgpu_ras.h"
33	#include "amdgpu_gfx.h"
34
35	#define SE_ID_MAX 8
36	#define CU_ID_MAX 16
37	#define SIMD_ID_MAX 4
38	#define WAVE_ID_MAX 10
39
40	enum gfx_v9_4_2_utc_type {
41	VML2_MEM,
42	VML2_WALKER_MEM,
43	UTCL2_MEM,
44	ATC_L2_CACHE_2M,
45	ATC_L2_CACHE_32K,
46	ATC_L2_CACHE_4K
47	};
48
49	struct gfx_v9_4_2_utc_block {
50	enum gfx_v9_4_2_utc_type type;
51	uint32_t num_banks;
52	uint32_t num_ways;
53	uint32_t num_mem_blocks;
54	struct soc15_reg idx_reg;
55	struct soc15_reg data_reg;
56	uint32_t sec_count_mask;
57	uint32_t sec_count_shift;
58	uint32_t ded_count_mask;
59	uint32_t ded_count_shift;
60	uint32_t clear;
61	};
62
63	static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_0[] = {
64	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920),
65	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93),
66	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583),
67	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6),
68	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6),
69	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351),
70	};
71
72	static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_1[] = {
73	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38),
74	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b),
75	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x2bc3369b),
76	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0xfb74ee),
77	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x21f0a2fe),
78	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x49),
79	};
80
81	static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = {
82	SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
83	SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
84	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_UTCL1_CNTL1, 0xffffffff, 0x30800400),
85	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20),
86	};
87
88	/*
89	* This shader is used to clear VGPRS and LDS, and also write the input
90	* pattern into the write back buffer, which will be used by driver to
91	* check whether all SIMDs have been covered.
92	*/
93	static const u32 vgpr_init_compute_shader_aldebaran[] = {
94	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
95	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
96	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xd3d94000,
97	0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 0xd3d94003,
98	0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 0xd3d94006,
99	0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 0xd3d94009,
100	0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 0xd3d9400c,
101	0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 0xd3d9400f,
102	0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 0xd3d94012,
103	0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 0xd3d94015,
104	0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 0xd3d94018,
105	0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 0xd3d9401b,
106	0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 0xd3d9401e,
107	0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 0xd3d94021,
108	0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 0xd3d94024,
109	0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 0xd3d94027,
110	0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 0xd3d9402a,
111	0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 0xd3d9402d,
112	0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 0xd3d94030,
113	0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 0xd3d94033,
114	0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 0xd3d94036,
115	0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 0xd3d94039,
116	0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 0xd3d9403c,
117	0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 0xd3d9403f,
118	0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 0xd3d94042,
119	0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 0xd3d94045,
120	0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 0xd3d94048,
121	0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 0xd3d9404b,
122	0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 0xd3d9404e,
123	0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 0xd3d94051,
124	0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 0xd3d94054,
125	0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 0xd3d94057,
126	0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 0xd3d9405a,
127	0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 0xd3d9405d,
128	0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 0xd3d94060,
129	0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 0xd3d94063,
130	0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 0xd3d94066,
131	0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 0xd3d94069,
132	0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 0xd3d9406c,
133	0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 0xd3d9406f,
134	0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 0xd3d94072,
135	0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 0xd3d94075,
136	0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 0xd3d94078,
137	0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 0xd3d9407b,
138	0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 0xd3d9407e,
139	0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 0xd3d94081,
140	0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 0xd3d94084,
141	0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 0xd3d94087,
142	0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 0xd3d9408a,
143	0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 0xd3d9408d,
144	0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 0xd3d94090,
145	0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 0xd3d94093,
146	0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 0xd3d94096,
147	0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 0xd3d94099,
148	0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 0xd3d9409c,
149	0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 0xd3d9409f,
150	0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 0xd3d940a2,
151	0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 0xd3d940a5,
152	0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 0xd3d940a8,
153	0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 0xd3d940ab,
154	0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 0xd3d940ae,
155	0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 0xd3d940b1,
156	0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 0xd3d940b4,
157	0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 0xd3d940b7,
158	0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 0xd3d940ba,
159	0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 0xd3d940bd,
160	0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 0xd3d940c0,
161	0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 0xd3d940c3,
162	0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 0xd3d940c6,
163	0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 0xd3d940c9,
164	0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 0xd3d940cc,
165	0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 0xd3d940cf,
166	0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 0xd3d940d2,
167	0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 0xd3d940d5,
168	0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 0xd3d940d8,
169	0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 0xd3d940db,
170	0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 0xd3d940de,
171	0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 0xd3d940e1,
172	0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 0xd3d940e4,
173	0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 0xd3d940e7,
174	0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 0xd3d940ea,
175	0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 0xd3d940ed,
176	0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 0xd3d940f0,
177	0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 0xd3d940f3,
178	0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 0xd3d940f6,
179	0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 0xd3d940f9,
180	0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 0xd3d940fc,
181	0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 0xd3d940ff,
182	0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 0x7e000280,
183	0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 0x7e0c0280,
184	0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 0xd28c0001,
185	0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xbe8b0004, 0xb78b4000,
186	0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 0x00020201,
187	0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 0xbf84fff8,
188	0xbf810000,
189	};
190
191	const struct soc15_reg_entry vgpr_init_regs_aldebaran[] = {
192	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
193	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
194	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 4 },
195	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
196	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0xbf },
197	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x400006 }, /* 64KB LDS */
198	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x3F }, /* 63 - accum-offset = 256 */
199	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
200	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
201	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
202	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
203	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
204	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
205	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
206	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
207	};
208
209	/*
210	* The below shaders are used to clear SGPRS, and also write the input
211	* pattern into the write back buffer. The first two dispatch should be
212	* scheduled simultaneously which make sure that all SGPRS could be
213	* allocated, so the dispatch 1 need check write back buffer before scheduled,
214	* make sure that waves of dispatch 0 are all dispacthed to all simds
215	* balanced. both dispatch 0 and dispatch 1 should be halted until all waves
216	* are dispatched, and then driver write a pattern to the shared memory to make
217	* all waves continue.
218	*/
219	static const u32 sgpr112_init_compute_shader_aldebaran[] = {
220	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
221	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
222	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
223	0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
224	0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
225	0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
226	0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
227	0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
228	0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
229	0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
230	0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
231	0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
232	0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
233	0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
234	0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080,
235	0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080,
236	0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080,
237	0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080,
238	0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080,
239	0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080,
240	0xbeda0080, 0xbedb0080, 0xbedc0080, 0xbedd0080, 0xbede0080, 0xbedf0080,
241	0xbee00080, 0xbee10080, 0xbee20080, 0xbee30080, 0xbee40080, 0xbee50080,
242	0xbf810000
243	};
244
245	const struct soc15_reg_entry sgpr112_init_regs_aldebaran[] = {
246	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
247	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
248	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 8 },
249	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
250	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x340 },
251	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
252	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
253	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
254	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
255	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
256	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
257	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
258	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
259	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
260	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
261	};
262
263	static const u32 sgpr96_init_compute_shader_aldebaran[] = {
264	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
265	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
266	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
267	0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
268	0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
269	0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
270	0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
271	0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
272	0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
273	0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
274	0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
275	0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
276	0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
277	0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
278	0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080,
279	0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080,
280	0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080,
281	0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080,
282	0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080,
283	0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080,
284	0xbf810000,
285	};
286
287	const struct soc15_reg_entry sgpr96_init_regs_aldebaran[] = {
288	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
289	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
290	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0xc },
291	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
292	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x2c0 },
293	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
294	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
295	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
296	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
297	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
298	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
299	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
300	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
301	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
302	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
303	};
304
305	/*
306	* This shader is used to clear the uninitiated sgprs after the above
307	* two dispatches, because of hardware feature, dispath 0 couldn't clear
308	* top hole sgprs. Therefore need 4 waves per SIMD to cover these sgprs
309	*/
310	static const u32 sgpr64_init_compute_shader_aldebaran[] = {
311	0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
312	0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
313	0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
314	0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
315	0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
316	0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
317	0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
318	0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
319	0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
320	0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
321	0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
322	0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
323	0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
324	0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
325	0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbf810000,
326	};
327
328	const struct soc15_reg_entry sgpr64_init_regs_aldebaran[] = {
329	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
330	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
331	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0x10 },
332	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
333	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x1c0 },
334	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
335	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
336	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
337	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
338	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
339	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
340	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
341	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
342	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
343	{ SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
344	};
345
346	static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
347	struct amdgpu_ring *ring,
348	struct amdgpu_ib *ib,
349	const u32 *shader_ptr, u32 shader_size,
350	const struct soc15_reg_entry *init_regs, u32 regs_size,
351	u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern,
352	struct dma_fence **fence_ptr)
353	{
354	int r, i;
355	uint32_t total_size, shader_offset;
356	u64 gpu_addr;
357
358	total_size = (regs_size * 3 + 4 + 5 + 5) * 4;
359	total_size = ALIGN(total_size, 256);
360	shader_offset = total_size;
361	total_size += ALIGN(shader_size, 256);
362
363	/* allocate an indirect buffer to put the commands in */
364	memset(ib, 0, sizeof(*ib));
365	r = amdgpu_ib_get(adev, NULL, size: total_size,
366	pool: AMDGPU_IB_POOL_DIRECT, ib);
367	if (r) {
368	dev_err(adev->dev, "failed to get ib (%d).\n", r);
369	return r;
370	}
371
372	/* load the compute shaders */
373	for (i = 0; i < shader_size/sizeof(u32); i++)
374	ib->ptr[i + (shader_offset / 4)] = shader_ptr[i];
375
376	/* init the ib length to 0 */
377	ib->length_dw = 0;
378
379	/* write the register state for the compute dispatch */
380	for (i = 0; i < regs_size; i++) {
381	ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
382	ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i])
383	- PACKET3_SET_SH_REG_START;
384	ib->ptr[ib->length_dw++] = init_regs[i].reg_value;
385	}
386
387	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
388	gpu_addr = (ib->gpu_addr + (u64)shader_offset) >> 8;
389	ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
390	ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_PGM_LO)
391	- PACKET3_SET_SH_REG_START;
392	ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
393	ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
394
395	/* write the wb buffer address */
396	ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3);
397	ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_USER_DATA_0)
398	- PACKET3_SET_SH_REG_START;
399	ib->ptr[ib->length_dw++] = lower_32_bits(wb_gpu_addr);
400	ib->ptr[ib->length_dw++] = upper_32_bits(wb_gpu_addr);
401	ib->ptr[ib->length_dw++] = pattern;
402
403	/* write dispatch packet */
404	ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
405	ib->ptr[ib->length_dw++] = compute_dim_x; /* x */
406	ib->ptr[ib->length_dw++] = 1; /* y */
407	ib->ptr[ib->length_dw++] = 1; /* z */
408	ib->ptr[ib->length_dw++] =
409	REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
410
411	/* shedule the ib on the ring */
412	r = amdgpu_ib_schedule(ring, num_ibs: 1, ibs: ib, NULL, f: fence_ptr);
413	if (r) {
414	dev_err(adev->dev, "ib submit failed (%d).\n", r);
415	amdgpu_ib_free(ib, NULL);
416	}
417	return r;
418	}
419
420	static void gfx_v9_4_2_log_wave_assignment(struct amdgpu_device *adev, uint32_t *wb_ptr)
421	{
422	uint32_t se, cu, simd, wave;
423	uint32_t offset = 0;
424	char *str;
425	int size;
426
427	str = kmalloc(256, GFP_KERNEL);
428	if (!str)
429	return;
430
431	dev_dbg(adev->dev, "wave assignment:\n");
432
433	for (se = 0; se < adev->gfx.config.max_shader_engines; se++) {
434	for (cu = 0; cu < CU_ID_MAX; cu++) {
435	memset(str, 0, 256);
436	size = sprintf(buf: str, fmt: "SE[%02d]CU[%02d]: ", se, cu);
437	for (simd = 0; simd < SIMD_ID_MAX; simd++) {
438	size += sprintf(buf: str + size, fmt: "[");
439	for (wave = 0; wave < WAVE_ID_MAX; wave++) {
440	size += sprintf(buf: str + size, fmt: "%x", wb_ptr[offset]);
441	offset++;
442	}
443	size += sprintf(buf: str + size, fmt: "] ");
444	}
445	dev_dbg(adev->dev, "%s\n", str);
446	}
447	}
448
449	kfree(objp: str);
450	}
451
452	static int gfx_v9_4_2_wait_for_waves_assigned(struct amdgpu_device *adev,
453	uint32_t *wb_ptr, uint32_t mask,
454	uint32_t pattern, uint32_t num_wave, bool wait)
455	{
456	uint32_t se, cu, simd, wave;
457	uint32_t loop = 0;
458	uint32_t wave_cnt;
459	uint32_t offset;
460
461	do {
462	wave_cnt = 0;
463	offset = 0;
464
465	for (se = 0; se < adev->gfx.config.max_shader_engines; se++)
466	for (cu = 0; cu < CU_ID_MAX; cu++)
467	for (simd = 0; simd < SIMD_ID_MAX; simd++)
468	for (wave = 0; wave < WAVE_ID_MAX; wave++) {
469	if (((1 << wave) & mask) &&
470	(wb_ptr[offset] == pattern))
471	wave_cnt++;
472
473	offset++;
474	}
475
476	if (wave_cnt == num_wave)
477	return 0;
478
479	mdelay(1);
480	} while (++loop < 2000 && wait);
481
482	dev_err(adev->dev, "actual wave num: %d, expected wave num: %d\n",
483	wave_cnt, num_wave);
484
485	gfx_v9_4_2_log_wave_assignment(adev, wb_ptr);
486
487	return -EBADSLT;
488	}
489
490	static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
491	{
492	int r;
493	int wb_size = adev->gfx.config.max_shader_engines *
494	CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
495	struct amdgpu_ib wb_ib;
496	struct amdgpu_ib disp_ibs[3];
497	struct dma_fence *fences[3];
498	u32 pattern[3] = { 0x1, 0x5, 0xa };
499
500	/* bail if the compute ring is not ready */
501	if (!adev->gfx.compute_ring[0].sched.ready ||
502	!adev->gfx.compute_ring[1].sched.ready)
503	return 0;
504
505	/* allocate the write-back buffer from IB */
506	memset(&wb_ib, 0, sizeof(wb_ib));
507	r = amdgpu_ib_get(adev, NULL, size: (1 + wb_size) * sizeof(uint32_t),
508	pool: AMDGPU_IB_POOL_DIRECT, ib: &wb_ib);
509	if (r) {
510	dev_err(adev->dev, "failed to get ib (%d) for wb\n", r);
511	return r;
512	}
513	memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
514
515	r = gfx_v9_4_2_run_shader(adev,
516	ring: &adev->gfx.compute_ring[0],
517	ib: &disp_ibs[0],
518	shader_ptr: sgpr112_init_compute_shader_aldebaran,
519	shader_size: sizeof(sgpr112_init_compute_shader_aldebaran),
520	init_regs: sgpr112_init_regs_aldebaran,
521	ARRAY_SIZE(sgpr112_init_regs_aldebaran),
522	compute_dim_x: adev->gfx.cu_info.number,
523	wb_gpu_addr: wb_ib.gpu_addr, pattern: pattern[0], fence_ptr: &fences[0]);
524	if (r) {
525	dev_err(adev->dev, "failed to clear first 224 sgprs\n");
526	goto pro_end;
527	}
528
529	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
530	wb_ptr: &wb_ib.ptr[1], mask: 0b11,
531	pattern: pattern[0],
532	num_wave: adev->gfx.cu_info.number * SIMD_ID_MAX * 2,
533	wait: true);
534	if (r) {
535	dev_err(adev->dev, "wave coverage failed when clear first 224 sgprs\n");
536	wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
537	goto disp0_failed;
538	}
539
540	r = gfx_v9_4_2_run_shader(adev,
541	ring: &adev->gfx.compute_ring[1],
542	ib: &disp_ibs[1],
543	shader_ptr: sgpr96_init_compute_shader_aldebaran,
544	shader_size: sizeof(sgpr96_init_compute_shader_aldebaran),
545	init_regs: sgpr96_init_regs_aldebaran,
546	ARRAY_SIZE(sgpr96_init_regs_aldebaran),
547	compute_dim_x: adev->gfx.cu_info.number * 2,
548	wb_gpu_addr: wb_ib.gpu_addr, pattern: pattern[1], fence_ptr: &fences[1]);
549	if (r) {
550	dev_err(adev->dev, "failed to clear next 576 sgprs\n");
551	goto disp0_failed;
552	}
553
554	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
555	wb_ptr: &wb_ib.ptr[1], mask: 0b11111100,
556	pattern: pattern[1], num_wave: adev->gfx.cu_info.number * SIMD_ID_MAX * 6,
557	wait: true);
558	if (r) {
559	dev_err(adev->dev, "wave coverage failed when clear first 576 sgprs\n");
560	wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
561	goto disp1_failed;
562	}
563
564	wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
565
566	/* wait for the GPU to finish processing the IB */
567	r = dma_fence_wait(fence: fences[0], intr: false);
568	if (r) {
569	dev_err(adev->dev, "timeout to clear first 224 sgprs\n");
570	goto disp1_failed;
571	}
572
573	r = dma_fence_wait(fence: fences[1], intr: false);
574	if (r) {
575	dev_err(adev->dev, "timeout to clear first 576 sgprs\n");
576	goto disp1_failed;
577	}
578
579	memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
580	r = gfx_v9_4_2_run_shader(adev,
581	ring: &adev->gfx.compute_ring[0],
582	ib: &disp_ibs[2],
583	shader_ptr: sgpr64_init_compute_shader_aldebaran,
584	shader_size: sizeof(sgpr64_init_compute_shader_aldebaran),
585	init_regs: sgpr64_init_regs_aldebaran,
586	ARRAY_SIZE(sgpr64_init_regs_aldebaran),
587	compute_dim_x: adev->gfx.cu_info.number,
588	wb_gpu_addr: wb_ib.gpu_addr, pattern: pattern[2], fence_ptr: &fences[2]);
589	if (r) {
590	dev_err(adev->dev, "failed to clear first 256 sgprs\n");
591	goto disp1_failed;
592	}
593
594	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
595	wb_ptr: &wb_ib.ptr[1], mask: 0b1111,
596	pattern: pattern[2],
597	num_wave: adev->gfx.cu_info.number * SIMD_ID_MAX * 4,
598	wait: true);
599	if (r) {
600	dev_err(adev->dev, "wave coverage failed when clear first 256 sgprs\n");
601	wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
602	goto disp2_failed;
603	}
604
605	wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
606
607	r = dma_fence_wait(fence: fences[2], intr: false);
608	if (r) {
609	dev_err(adev->dev, "timeout to clear first 256 sgprs\n");
610	goto disp2_failed;
611	}
612
613	disp2_failed:
614	amdgpu_ib_free(ib: &disp_ibs[2], NULL);
615	dma_fence_put(fence: fences[2]);
616	disp1_failed:
617	amdgpu_ib_free(ib: &disp_ibs[1], NULL);
618	dma_fence_put(fence: fences[1]);
619	disp0_failed:
620	amdgpu_ib_free(ib: &disp_ibs[0], NULL);
621	dma_fence_put(fence: fences[0]);
622	pro_end:
623	amdgpu_ib_free(ib: &wb_ib, NULL);
624
625	if (r)
626	dev_info(adev->dev, "Init SGPRS Failed\n");
627	else
628	dev_info(adev->dev, "Init SGPRS Successfully\n");
629
630	return r;
631	}
632
633	static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
634	{
635	int r;
636	/* CU_ID: 0~15, SIMD_ID: 0~3, WAVE_ID: 0 ~ 9 */
637	int wb_size = adev->gfx.config.max_shader_engines *
638	CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
639	struct amdgpu_ib wb_ib;
640	struct amdgpu_ib disp_ib;
641	struct dma_fence *fence;
642	u32 pattern = 0xa;
643
644	/* bail if the compute ring is not ready */
645	if (!adev->gfx.compute_ring[0].sched.ready)
646	return 0;
647
648	/* allocate the write-back buffer from IB */
649	memset(&wb_ib, 0, sizeof(wb_ib));
650	r = amdgpu_ib_get(adev, NULL, size: (1 + wb_size) * sizeof(uint32_t),
651	pool: AMDGPU_IB_POOL_DIRECT, ib: &wb_ib);
652	if (r) {
653	dev_err(adev->dev, "failed to get ib (%d) for wb.\n", r);
654	return r;
655	}
656	memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
657
658	r = gfx_v9_4_2_run_shader(adev,
659	ring: &adev->gfx.compute_ring[0],
660	ib: &disp_ib,
661	shader_ptr: vgpr_init_compute_shader_aldebaran,
662	shader_size: sizeof(vgpr_init_compute_shader_aldebaran),
663	init_regs: vgpr_init_regs_aldebaran,
664	ARRAY_SIZE(vgpr_init_regs_aldebaran),
665	compute_dim_x: adev->gfx.cu_info.number,
666	wb_gpu_addr: wb_ib.gpu_addr, pattern, fence_ptr: &fence);
667	if (r) {
668	dev_err(adev->dev, "failed to clear vgprs\n");
669	goto pro_end;
670	}
671
672	/* wait for the GPU to finish processing the IB */
673	r = dma_fence_wait(fence, intr: false);
674	if (r) {
675	dev_err(adev->dev, "timeout to clear vgprs\n");
676	goto disp_failed;
677	}
678
679	r = gfx_v9_4_2_wait_for_waves_assigned(adev,
680	wb_ptr: &wb_ib.ptr[1], mask: 0b1,
681	pattern,
682	num_wave: adev->gfx.cu_info.number * SIMD_ID_MAX,
683	wait: false);
684	if (r) {
685	dev_err(adev->dev, "failed to cover all simds when clearing vgprs\n");
686	goto disp_failed;
687	}
688
689	disp_failed:
690	amdgpu_ib_free(ib: &disp_ib, NULL);
691	dma_fence_put(fence);
692	pro_end:
693	amdgpu_ib_free(ib: &wb_ib, NULL);
694
695	if (r)
696	dev_info(adev->dev, "Init VGPRS Failed\n");
697	else
698	dev_info(adev->dev, "Init VGPRS Successfully\n");
699
700	return r;
701	}
702
703	int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev)
704	{
705	/* only support when RAS is enabled */
706	if (!amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__GFX))
707	return 0;
708
709	/* Workaround for ALDEBARAN, skip GPRs init in GPU reset.
710	Will remove it once GPRs init algorithm works for all CU settings. */
711	if (amdgpu_in_reset(adev))
712	return 0;
713
714	gfx_v9_4_2_do_sgprs_init(adev);
715
716	gfx_v9_4_2_do_vgprs_init(adev);
717
718	return 0;
719	}
720
721	static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev);
722	static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev);
723
724	void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
725	uint32_t die_id)
726	{
727	soc15_program_register_sequence(adev,
728	registers: golden_settings_gc_9_4_2_alde,
729	ARRAY_SIZE(golden_settings_gc_9_4_2_alde));
730
731	/* apply golden settings per die */
732	switch (die_id) {
733	case 0:
734	soc15_program_register_sequence(adev,
735	registers: golden_settings_gc_9_4_2_alde_die_0,
736	ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_0));
737	break;
738	case 1:
739	soc15_program_register_sequence(adev,
740	registers: golden_settings_gc_9_4_2_alde_die_1,
741	ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_1));
742	break;
743	default:
744	dev_warn(adev->dev,
745	"invalid die id %d, ignore channel fabricid remap settings\n",
746	die_id);
747	break;
748	}
749	}
750
751	void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
752	uint32_t first_vmid,
753	uint32_t last_vmid)
754	{
755	uint32_t data;
756	int i;
757
758	mutex_lock(&adev->srbm_mutex);
759
760	for (i = first_vmid; i < last_vmid; i++) {
761	data = 0;
762	soc15_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: i, xcc_id: 0);
763	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
764	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
765	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE,
766	0);
767	WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data);
768	}
769
770	soc15_grbm_select(adev, me: 0, pipe: 0, queue: 0, vmid: 0, xcc_id: 0);
771	mutex_unlock(lock: &adev->srbm_mutex);
772
773	WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA0), 0);
774	WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA1), 0);
775	}
776
777	void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)
778	{
779	u32 tmp;
780
781	gfx_v9_0_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff, xcc_id: 0);
782
783	tmp = 0;
784	tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);
785	WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp);
786
787	tmp = 0;
788	tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
789	WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
790
791	WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
792	tmp = 0;
793	tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);
794	WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp);
795	}
796
797	static const struct soc15_reg_entry gfx_v9_4_2_edc_counter_regs[] = {
798	/* CPF */
799	{ SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), 0, 1, 1 },
800	{ SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT), 0, 1, .hwip: 1 },
801	/* CPC */
802	{ SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
803	{ SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT), 0, 1, .hwip: 1 },
804	{ SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT), 0, 1, 1 },
805	{ SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), 0, 1, .hwip: 1 },
806	{ SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), 0, 1, 1 },
807	/* GDS */
808	{ SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT), 0, 1, .hwip: 1 },
809	{ SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT), 0, 1, 1 },
810	{ SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 1, .hwip: 1 },
811	{ SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
812	{ SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 0, 1, .hwip: 1 },
813	/* RLC */
814	{ SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), 0, 1, 1 },
815	{ SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), 0, 1, .hwip: 1 },
816	/* SPI */
817	{ SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), 0, 8, 1 },
818	/* SQC */
819	{ SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), 0, 8, .hwip: 7 },
820	{ SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), 0, 8, 7 },
821	{ SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), 0, 8, .hwip: 7 },
822	{ SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), 0, 8, 7 },
823	/* SQ */
824	{ SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), 0, 8, .hwip: 14 },
825	/* TCP */
826	{ SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), 0, 8, 14 },
827	/* TCI */
828	{ SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT), 0, 1, .hwip: 69 },
829	/* TCC */
830	{ SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), 0, 1, 16 },
831	{ SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), 0, 1, .hwip: 16 },
832	/* TCA */
833	{ SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), 0, 1, 2 },
834	/* TCX */
835	{ SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), 0, 1, .hwip: 2 },
836	{ SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), 0, 1, 2 },
837	/* TD */
838	{ SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), 0, 8, .hwip: 14 },
839	/* TA */
840	{ SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), 0, 8, 14 },
841	/* GCEA */
842	{ SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), 0, 1, .hwip: 16 },
843	{ SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), 0, 1, 16 },
844	{ SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 1, .hwip: 16 },
845	};
846
847	static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num,
848	u32 sh_num, u32 instance)
849	{
850	u32 data;
851
852	if (instance == 0xffffffff)
853	data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
854	INSTANCE_BROADCAST_WRITES, 1);
855	else
856	data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
857	instance);
858
859	if (se_num == 0xffffffff)
860	data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
861	1);
862	else
863	data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
864
865	if (sh_num == 0xffffffff)
866	data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
867	1);
868	else
869	data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
870
871	WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
872	}
873
874	static const struct soc15_ras_field_entry gfx_v9_4_2_ras_fields[] = {
875	/* CPF */
876	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT),
877	SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2),
878	SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) },
879	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT),
880	SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1),
881	SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) },
882	{ "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT),
883	SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
884	SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) },
885
886	/* CPC */
887	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT),
888	SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
889	SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
890	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT),
891	SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
892	SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) },
893	{ "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT),
894	SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1),
895	SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) },
896	{ "CPC_DC_CSINVOC_RAM_ME1",
897	SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
898	SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1),
899	SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) },
900	{ "CPC_DC_RESTORE_RAM_ME1",
901	SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
902	SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1),
903	SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) },
904	{ "CPC_DC_CSINVOC_RAM1_ME1",
905	SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
906	SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1),
907	SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) },
908	{ "CPC_DC_RESTORE_RAM1_ME1",
909	SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
910	SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1),
911	SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) },
912
913	/* GDS */
914	{ "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT),
915	SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC),
916	SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) },
917	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT),
918	SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
919	SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) },
920	{ "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
921	SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
922	SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
923	{ "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
924	SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC),
925	SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) },
926	{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
927	SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
928	SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
929	{ "GDS_ME1_PIPE0_PIPE_MEM",
930	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
931	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
932	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
933	{ "GDS_ME1_PIPE1_PIPE_MEM",
934	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
935	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
936	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
937	{ "GDS_ME1_PIPE2_PIPE_MEM",
938	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
939	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
940	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
941	{ "GDS_ME1_PIPE3_PIPE_MEM",
942	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
943	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
944	SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
945	{ "GDS_ME0_GFXHP3D_PIX_DED",
946	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, .name: 0,
947	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_PIX_DED) },
948	{ "GDS_ME0_GFXHP3D_VTX_DED",
949	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
950	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_VTX_DED) },
951	{ "GDS_ME0_CS_DED",
952	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, .name: 0,
953	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_CS_DED) },
954	{ "GDS_ME0_GFXHP3D_GS_DED",
955	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
956	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_GS_DED) },
957	{ "GDS_ME1_PIPE0_DED",
958	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, .name: 0,
959	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE0_DED) },
960	{ "GDS_ME1_PIPE1_DED",
961	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
962	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE1_DED) },
963	{ "GDS_ME1_PIPE2_DED",
964	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, .name: 0,
965	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE2_DED) },
966	{ "GDS_ME1_PIPE3_DED",
967	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
968	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE3_DED) },
969	{ "GDS_ME2_PIPE0_DED",
970	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, .name: 0,
971	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE0_DED) },
972	{ "GDS_ME2_PIPE1_DED",
973	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
974	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE1_DED) },
975	{ "GDS_ME2_PIPE2_DED",
976	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, .name: 0,
977	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE2_DED) },
978	{ "GDS_ME2_PIPE3_DED",
979	SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
980	SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE3_DED) },
981
982	/* RLC */
983	{ "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
984	SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT),
985	SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) },
986	{ "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
987	SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT),
988	SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) },
989	{ "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
990	SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT),
991	SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) },
992	{ "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
993	SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT),
994	SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) },
995	{ "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
996	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT),
997	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) },
998	{ "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
999	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT),
1000	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) },
1001	{ "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
1002	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT),
1003	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) },
1004	{ "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
1005	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT),
1006	SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) },
1007	{ "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1008	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT),
1009	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) },
1010	{ "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1011	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT),
1012	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) },
1013	{ "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1014	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT),
1015	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) },
1016	{ "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1017	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT),
1018	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) },
1019	{ "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1020	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT),
1021	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) },
1022	{ "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1023	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT),
1024	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) },
1025	{ "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1026	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT),
1027	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) },
1028	{ "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1029	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT),
1030	SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) },
1031
1032	/* SPI */
1033	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1034	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT),
1035	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) },
1036	{ "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1037	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT),
1038	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) },
1039	{ "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1040	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT),
1041	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) },
1042	{ "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1043	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT),
1044	SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) },
1045
1046	/* SQC - regSQC_EDC_CNT */
1047	{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1048	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
1049	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
1050	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1051	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
1052	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
1053	{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1054	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
1055	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
1056	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1057	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
1058	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
1059	{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1060	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
1061	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
1062	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1063	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
1064	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
1065	{ "SQC_DATA_CU3_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1066	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_SEC_COUNT),
1067	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_DED_COUNT) },
1068	{ "SQC_DATA_CU3_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1069	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_SEC_COUNT),
1070	SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_DED_COUNT) },
1071
1072	/* SQC - regSQC_EDC_CNT2 */
1073	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1074	SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
1075	SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
1076	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1077	SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
1078	SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
1079	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1080	SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
1081	SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
1082	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1083	SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
1084	SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
1085	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1086	SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
1087	SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
1088	{ "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1089	SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT),
1090	SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT) },
1091
1092	/* SQC - regSQC_EDC_CNT3 */
1093	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1094	SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
1095	SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
1096	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1097	SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
1098	SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
1099	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1100	SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
1101	SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
1102	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1103	SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
1104	SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
1105	{ "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1106	SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT),
1107	SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT) },
1108
1109	/* SQC - regSQC_EDC_PARITY_CNT3 */
1110	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1111	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT),
1112	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) },
1113	{ "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1114	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT),
1115	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_DED_COUNT) },
1116	{ "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1117	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT),
1118	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) },
1119	{ "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1120	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT),
1121	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_DED_COUNT) },
1122	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1123	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT),
1124	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) },
1125	{ "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1126	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT),
1127	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_DED_COUNT) },
1128	{ "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1129	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT),
1130	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) },
1131	{ "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1132	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT),
1133	SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_DED_COUNT) },
1134
1135	/* SQ */
1136	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1137	SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
1138	SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) },
1139	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1140	SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
1141	SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) },
1142	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1143	SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
1144	SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) },
1145	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1146	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
1147	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) },
1148	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1149	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
1150	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) },
1151	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1152	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
1153	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) },
1154	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1155	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
1156	SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) },
1157
1158	/* TCP */
1159	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1160	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
1161	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
1162	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1163	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
1164	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
1165	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1166	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT),
1167	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) },
1168	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1169	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
1170	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) },
1171	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1172	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SEC_COUNT),
1173	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_DED_COUNT) },
1174	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1175	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
1176	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
1177	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1178	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
1179	SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
1180
1181	/* TCI */
1182	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT),
1183	SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT),
1184	SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) },
1185
1186	/* TCC */
1187	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1188	SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
1189	SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
1190	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1191	SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
1192	SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
1193	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1194	SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
1195	SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
1196	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1197	SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
1198	SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
1199	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1200	SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
1201	SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
1202	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1203	SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT),
1204	SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) },
1205	{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1206	SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT),
1207	SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) },
1208	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1209	SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT),
1210	SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) },
1211	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1212	SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT),
1213	SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) },
1214	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1215	SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT),
1216	SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) },
1217	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1218	SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT),
1219	SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) },
1220	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1221	SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT),
1222	SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) },
1223	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1224	SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT),
1225	SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) },
1226	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1227	SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT),
1228	SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) },
1229	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1230	SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT),
1231	SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) },
1232
1233	/* TCA */
1234	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT),
1235	SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT),
1236	SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) },
1237	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT),
1238	SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT),
1239	SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) },
1240
1241	/* TCX */
1242	{ "TCX_GROUP0", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1243	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_SEC_COUNT),
1244	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_DED_COUNT) },
1245	{ "TCX_GROUP1", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1246	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_SEC_COUNT),
1247	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_DED_COUNT) },
1248	{ "TCX_GROUP2", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1249	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_SEC_COUNT),
1250	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_DED_COUNT) },
1251	{ "TCX_GROUP3", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1252	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_SEC_COUNT),
1253	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_DED_COUNT) },
1254	{ "TCX_GROUP4", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1255	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_SEC_COUNT),
1256	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_DED_COUNT) },
1257	{ "TCX_GROUP5", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1258	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP5_SED_COUNT), .hwip: 0, .inst: 0 },
1259	{ "TCX_GROUP6", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1260	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP6_SED_COUNT), 0, 0 },
1261	{ "TCX_GROUP7", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1262	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP7_SED_COUNT), .hwip: 0, .inst: 0 },
1263	{ "TCX_GROUP8", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1264	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP8_SED_COUNT), 0, 0 },
1265	{ "TCX_GROUP9", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1266	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP9_SED_COUNT), .hwip: 0, .inst: 0 },
1267	{ "TCX_GROUP10", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1268	SOC15_REG_FIELD(TCX_EDC_CNT, GROUP10_SED_COUNT), 0, 0 },
1269	{ "TCX_GROUP11", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1270	SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP11_SED_COUNT), .hwip: 0, .inst: 0 },
1271	{ "TCX_GROUP12", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1272	SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP12_SED_COUNT), 0, 0 },
1273	{ "TCX_GROUP13", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1274	SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP13_SED_COUNT), .hwip: 0, .inst: 0 },
1275	{ "TCX_GROUP14", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1276	SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP14_SED_COUNT), 0, 0 },
1277
1278	/* TD */
1279	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
1280	SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
1281	SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
1282	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
1283	SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
1284	SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
1285	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
1286	SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT),
1287	SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) },
1288
1289	/* TA */
1290	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1291	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
1292	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
1293	{ "TA_FS_AFIFO_LO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1294	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_SEC_COUNT),
1295	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_DED_COUNT) },
1296	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1297	SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT),
1298	SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) },
1299	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1300	SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT),
1301	SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) },
1302	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1303	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT),
1304	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) },
1305	{ "TA_FS_AFIFO_HI", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1306	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_SEC_COUNT),
1307	SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_DED_COUNT) },
1308
1309	/* EA - regGCEA_EDC_CNT */
1310	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1311	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1312	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
1313	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1314	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1315	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
1316	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1317	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1318	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
1319	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1320	SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1321	SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
1322	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1323	SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1324	SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
1325	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1326	SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1327	SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_DED_COUNT) },
1328	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1329	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 },
1330	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1331	SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), .hwip: 0, .inst: 0 },
1332	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1333	SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 },
1334	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1335	SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), .hwip: 0, .inst: 0 },
1336
1337	/* EA - regGCEA_EDC_CNT2 */
1338	{ "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1339	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1340	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
1341	{ "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1342	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1343	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
1344	{ "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1345	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1346	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
1347	{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1348	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), .hwip: 0, .inst: 0 },
1349	{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1350	SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 },
1351	{ "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1352	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1353	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) },
1354	{ "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1355	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1356	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) },
1357	{ "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1358	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1359	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) },
1360	{ "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1361	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1362	SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) },
1363
1364	/* EA - regGCEA_EDC_CNT3 */
1365	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, .name: 0,
1366	SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) },
1367	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1368	SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) },
1369	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, .name: 0,
1370	SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) },
1371	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1372	SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) },
1373	{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, .name: 0,
1374	SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) },
1375	{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1376	SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) },
1377	{ "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1378	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT),
1379	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) },
1380	{ "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1381	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT),
1382	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) },
1383	{ "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1384	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT),
1385	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) },
1386	{ "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1387	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT),
1388	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) },
1389	{ "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1390	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_SEC_COUNT),
1391	SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) },
1392	};
1393
1394	static const char * const vml2_walker_mems[] = {
1395	"UTC_VML2_CACHE_PDE0_MEM0",
1396	"UTC_VML2_CACHE_PDE0_MEM1",
1397	"UTC_VML2_CACHE_PDE1_MEM0",
1398	"UTC_VML2_CACHE_PDE1_MEM1",
1399	"UTC_VML2_CACHE_PDE2_MEM0",
1400	"UTC_VML2_CACHE_PDE2_MEM1",
1401	"UTC_VML2_RDIF_ARADDRS",
1402	"UTC_VML2_RDIF_LOG_FIFO",
1403	"UTC_VML2_QUEUE_REQ",
1404	"UTC_VML2_QUEUE_RET",
1405	};
1406
1407	static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = {
1408	{ VML2_MEM, 8, 2, 2,
1409	{ SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_INDEX) },
1410	{ SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_CNTL) },
1411	SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, SEC_COUNT),
1412	SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, DED_COUNT),
1413	REG_SET_FIELD(0, VML2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
1414	{ VML2_WALKER_MEM, ARRAY_SIZE(vml2_walker_mems), 1, 1,
1415	{ SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_INDEX) },
1416	{ SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_CNTL) },
1417	SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, SEC_COUNT),
1418	SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, DED_COUNT),
1419	REG_SET_FIELD(0, VML2_WALKER_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
1420	{ UTCL2_MEM, 18, 1, 2,
1421	{ SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_INDEX) },
1422	{ SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_CNTL) },
1423	SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, SEC_COUNT),
1424	SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, DED_COUNT),
1425	REG_SET_FIELD(0, UTCL2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
1426	{ ATC_L2_CACHE_2M, 8, 2, 1,
1427	{ SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_INDEX) },
1428	{ SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_CNTL) },
1429	SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, SEC_COUNT),
1430	SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, DED_COUNT),
1431	REG_SET_FIELD(0, ATC_L2_CACHE_2M_DSM_CNTL, WRITE_COUNTERS, 1) },
1432	{ ATC_L2_CACHE_32K, 8, 2, 2,
1433	{ SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_INDEX) },
1434	{ SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_CNTL) },
1435	SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, SEC_COUNT),
1436	SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, DED_COUNT),
1437	REG_SET_FIELD(0, ATC_L2_CACHE_32K_DSM_CNTL, WRITE_COUNTERS, 1) },
1438	{ ATC_L2_CACHE_4K, 8, 2, 8,
1439	{ SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_INDEX) },
1440	{ SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_CNTL) },
1441	SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, SEC_COUNT),
1442	SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, DED_COUNT),
1443	REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) },
1444	};
1445
1446	static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs = {
1447	SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
1448	};
1449
1450	static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev,
1451	const struct soc15_reg_entry *reg,
1452	uint32_t se_id, uint32_t inst_id,
1453	uint32_t value, uint32_t *sec_count,
1454	uint32_t *ded_count)
1455	{
1456	uint32_t i;
1457	uint32_t sec_cnt, ded_cnt;
1458
1459	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_ras_fields); i++) {
1460	if (gfx_v9_4_2_ras_fields[i].reg_offset != reg->reg_offset ||
1461	gfx_v9_4_2_ras_fields[i].seg != reg->seg ||
1462	gfx_v9_4_2_ras_fields[i].inst != reg->inst)
1463	continue;
1464
1465	sec_cnt = SOC15_RAS_REG_FIELD_VAL(
1466	value, gfx_v9_4_2_ras_fields[i], sec);
1467	if (sec_cnt) {
1468	dev_info(adev->dev,
1469	"GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
1470	gfx_v9_4_2_ras_fields[i].name, se_id, inst_id,
1471	sec_cnt);
1472	*sec_count += sec_cnt;
1473	}
1474
1475	ded_cnt = SOC15_RAS_REG_FIELD_VAL(
1476	value, gfx_v9_4_2_ras_fields[i], ded);
1477	if (ded_cnt) {
1478	dev_info(adev->dev,
1479	"GFX SubBlock %s, Instance[%d][%d], DED %d\n",
1480	gfx_v9_4_2_ras_fields[i].name, se_id, inst_id,
1481	ded_cnt);
1482	*ded_count += ded_cnt;
1483	}
1484	}
1485
1486	return 0;
1487	}
1488
1489	static int gfx_v9_4_2_query_sram_edc_count(struct amdgpu_device *adev,
1490	uint32_t *sec_count, uint32_t *ded_count)
1491	{
1492	uint32_t i, j, k, data;
1493	uint32_t sec_cnt = 0, ded_cnt = 0;
1494
1495	if (sec_count && ded_count) {
1496	*sec_count = 0;
1497	*ded_count = 0;
1498	}
1499
1500	mutex_lock(&adev->grbm_idx_mutex);
1501
1502	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_edc_counter_regs); i++) {
1503	for (j = 0; j < gfx_v9_4_2_edc_counter_regs[i].se_num; j++) {
1504	for (k = 0; k < gfx_v9_4_2_edc_counter_regs[i].instance;
1505	k++) {
1506	gfx_v9_4_2_select_se_sh(adev, se_num: j, sh_num: 0, instance: k);
1507
1508	/* if sec/ded_count is null, just clear counter */
1509	if (!sec_count || !ded_count) {
1510	WREG32(SOC15_REG_ENTRY_OFFSET(
1511	gfx_v9_4_2_edc_counter_regs[i]), 0);
1512	continue;
1513	}
1514
1515	data = RREG32(SOC15_REG_ENTRY_OFFSET(
1516	gfx_v9_4_2_edc_counter_regs[i]));
1517
1518	if (!data)
1519	continue;
1520
1521	gfx_v9_4_2_get_reg_error_count(adev,
1522	reg: &gfx_v9_4_2_edc_counter_regs[i],
1523	se_id: j, inst_id: k, value: data, sec_count: &sec_cnt, ded_count: &ded_cnt);
1524
1525	/* clear counter after read */
1526	WREG32(SOC15_REG_ENTRY_OFFSET(
1527	gfx_v9_4_2_edc_counter_regs[i]), 0);
1528	}
1529	}
1530	}
1531
1532	if (sec_count && ded_count) {
1533	*sec_count += sec_cnt;
1534	*ded_count += ded_cnt;
1535	}
1536
1537	gfx_v9_4_2_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff);
1538	mutex_unlock(lock: &adev->grbm_idx_mutex);
1539
1540	return 0;
1541	}
1542
1543	static void gfx_v9_4_2_log_utc_edc_count(struct amdgpu_device *adev,
1544	struct gfx_v9_4_2_utc_block *blk,
1545	uint32_t instance, uint32_t sec_cnt,
1546	uint32_t ded_cnt)
1547	{
1548	uint32_t bank, way, mem;
1549	static const char * const vml2_way_str[] = { "BIGK", "4K" };
1550	static const char * const utcl2_router_str[] = { "VMC", "APT" };
1551
1552	mem = instance % blk->num_mem_blocks;
1553	way = (instance / blk->num_mem_blocks) % blk->num_ways;
1554	bank = instance / (blk->num_mem_blocks * blk->num_ways);
1555
1556	switch (blk->type) {
1557	case VML2_MEM:
1558	dev_info(
1559	adev->dev,
1560	"GFX SubBlock UTC_VML2_BANK_CACHE_%d_%s_MEM%d, SED %d, DED %d\n",
1561	bank, vml2_way_str[way], mem, sec_cnt, ded_cnt);
1562	break;
1563	case VML2_WALKER_MEM:
1564	dev_info(adev->dev, "GFX SubBlock %s, SED %d, DED %d\n",
1565	vml2_walker_mems[bank], sec_cnt, ded_cnt);
1566	break;
1567	case UTCL2_MEM:
1568	dev_info(
1569	adev->dev,
1570	"GFX SubBlock UTCL2_ROUTER_IFIF%d_GROUP0_%s, SED %d, DED %d\n",
1571	bank, utcl2_router_str[mem], sec_cnt, ded_cnt);
1572	break;
1573	case ATC_L2_CACHE_2M:
1574	dev_info(
1575	adev->dev,
1576	"GFX SubBlock UTC_ATCL2_CACHE_2M_BANK%d_WAY%d_MEM, SED %d, DED %d\n",
1577	bank, way, sec_cnt, ded_cnt);
1578	break;
1579	case ATC_L2_CACHE_32K:
1580	dev_info(
1581	adev->dev,
1582	"GFX SubBlock UTC_ATCL2_CACHE_32K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n",
1583	bank, way, mem, sec_cnt, ded_cnt);
1584	break;
1585	case ATC_L2_CACHE_4K:
1586	dev_info(
1587	adev->dev,
1588	"GFX SubBlock UTC_ATCL2_CACHE_4K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n",
1589	bank, way, mem, sec_cnt, ded_cnt);
1590	break;
1591	}
1592	}
1593
1594	static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev,
1595	uint32_t *sec_count,
1596	uint32_t *ded_count)
1597	{
1598	uint32_t i, j, data;
1599	uint32_t sec_cnt, ded_cnt;
1600	uint32_t num_instances;
1601	struct gfx_v9_4_2_utc_block *blk;
1602
1603	if (sec_count && ded_count) {
1604	*sec_count = 0;
1605	*ded_count = 0;
1606	}
1607
1608	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_utc_blocks); i++) {
1609	blk = &gfx_v9_4_2_utc_blocks[i];
1610	num_instances =
1611	blk->num_banks * blk->num_ways * blk->num_mem_blocks;
1612	for (j = 0; j < num_instances; j++) {
1613	WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j);
1614
1615	/* if sec/ded_count is NULL, just clear counter */
1616	if (!sec_count || !ded_count) {
1617	WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
1618	blk->clear);
1619	continue;
1620	}
1621
1622	data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg));
1623	if (!data)
1624	continue;
1625
1626	sec_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, sec);
1627	*sec_count += sec_cnt;
1628	ded_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, ded);
1629	*ded_count += ded_cnt;
1630
1631	/* clear counter after read */
1632	WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
1633	blk->clear);
1634
1635	/* print the edc count */
1636	if (sec_cnt || ded_cnt)
1637	gfx_v9_4_2_log_utc_edc_count(adev, blk, instance: j, sec_cnt,
1638	ded_cnt);
1639	}
1640	}
1641
1642	return 0;
1643	}
1644
1645	static void gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
1646	void *ras_error_status)
1647	{
1648	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1649	uint32_t sec_count = 0, ded_count = 0;
1650
1651	if (!amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__GFX))
1652	return;
1653
1654	err_data->ue_count = 0;
1655	err_data->ce_count = 0;
1656
1657	gfx_v9_4_2_query_sram_edc_count(adev, sec_count: &sec_count, ded_count: &ded_count);
1658	err_data->ce_count += sec_count;
1659	err_data->ue_count += ded_count;
1660
1661	gfx_v9_4_2_query_utc_edc_count(adev, sec_count: &sec_count, ded_count: &ded_count);
1662	err_data->ce_count += sec_count;
1663	err_data->ue_count += ded_count;
1664
1665	}
1666
1667	static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev)
1668	{
1669	WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
1670	WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
1671	WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
1672	}
1673
1674	static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev)
1675	{
1676	uint32_t i, j;
1677	uint32_t value;
1678
1679	mutex_lock(&adev->grbm_idx_mutex);
1680	for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
1681	for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
1682	j++) {
1683	gfx_v9_4_2_select_se_sh(adev, se_num: i, sh_num: 0, instance: j);
1684	value = RREG32(SOC15_REG_ENTRY_OFFSET(
1685	gfx_v9_4_2_ea_err_status_regs));
1686	value = REG_SET_FIELD(value, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);
1687	WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value);
1688	}
1689	}
1690	gfx_v9_4_2_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff);
1691	mutex_unlock(lock: &adev->grbm_idx_mutex);
1692	}
1693
1694	static void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
1695	{
1696	if (!amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__GFX))
1697	return;
1698
1699	gfx_v9_4_2_query_sram_edc_count(adev, NULL, NULL);
1700	gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL);
1701	}
1702
1703	static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
1704	{
1705	uint32_t i, j;
1706	uint32_t reg_value;
1707
1708	mutex_lock(&adev->grbm_idx_mutex);
1709
1710	for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
1711	for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
1712	j++) {
1713	gfx_v9_4_2_select_se_sh(adev, se_num: i, sh_num: 0, instance: j);
1714	reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1715	gfx_v9_4_2_ea_err_status_regs));
1716
1717	if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
1718	REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
1719	REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1720	dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n",
1721	j, reg_value);
1722	}
1723	/* clear after read */
1724	reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
1725	CLEAR_ERROR_STATUS, 0x1);
1726	WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), reg_value);
1727	}
1728	}
1729
1730	gfx_v9_4_2_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff);
1731	mutex_unlock(lock: &adev->grbm_idx_mutex);
1732	}
1733
1734	static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev)
1735	{
1736	uint32_t data;
1737
1738	data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS);
1739	if (data) {
1740	dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
1741	WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
1742	}
1743
1744	data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS);
1745	if (data) {
1746	dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
1747	WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
1748	}
1749
1750	data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS);
1751	if (data) {
1752	dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
1753	WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
1754	}
1755	}
1756
1757	static void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
1758	{
1759	if (!amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__GFX))
1760	return;
1761
1762	gfx_v9_4_2_query_ea_err_status(adev);
1763	gfx_v9_4_2_query_utc_err_status(adev);
1764	gfx_v9_4_2_query_sq_timeout_status(adev);
1765	}
1766
1767	static void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
1768	{
1769	if (!amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__GFX))
1770	return;
1771
1772	gfx_v9_4_2_reset_utc_err_status(adev);
1773	gfx_v9_4_2_reset_ea_err_status(adev);
1774	gfx_v9_4_2_reset_sq_timeout_status(adev);
1775	}
1776
1777	static void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
1778	{
1779	uint32_t i;
1780	uint32_t data;
1781
1782	data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
1783	amdgpu_watchdog_timer.timeout_fatal_disable ? 1 :
1784	0);
1785
1786	if (amdgpu_watchdog_timer.timeout_fatal_disable &&
1787	(amdgpu_watchdog_timer.period < 1 ||
1788	amdgpu_watchdog_timer.period > 0x23)) {
1789	dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
1790	amdgpu_watchdog_timer.period = 0x23;
1791	}
1792	data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
1793	amdgpu_watchdog_timer.period);
1794
1795	mutex_lock(&adev->grbm_idx_mutex);
1796	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1797	gfx_v9_4_2_select_se_sh(adev, se_num: i, sh_num: 0xffffffff, instance: 0xffffffff);
1798	WREG32_SOC15(GC, 0, regSQ_TIMEOUT_CONFIG, data);
1799	}
1800	gfx_v9_4_2_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff);
1801	mutex_unlock(lock: &adev->grbm_idx_mutex);
1802	}
1803
1804	static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1805	{
1806	WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX,
1807	(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1808	(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1809	(address << SQ_IND_INDEX__INDEX__SHIFT) |
1810	(SQ_IND_INDEX__FORCE_READ_MASK));
1811	return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
1812	}
1813
1814	static void gfx_v9_4_2_log_cu_timeout_status(struct amdgpu_device *adev,
1815	uint32_t status)
1816	{
1817	struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1818	uint32_t i, simd, wave;
1819	uint32_t wave_status;
1820	uint32_t wave_pc_lo, wave_pc_hi;
1821	uint32_t wave_exec_lo, wave_exec_hi;
1822	uint32_t wave_inst_dw0, wave_inst_dw1;
1823	uint32_t wave_ib_sts;
1824
1825	for (i = 0; i < 32; i++) {
1826	if (!((i << 1) & status))
1827	continue;
1828
1829	simd = i / cu_info->max_waves_per_simd;
1830	wave = i % cu_info->max_waves_per_simd;
1831
1832	wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1833	wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1834	wave_pc_hi = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1835	wave_exec_lo =
1836	wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1837	wave_exec_hi =
1838	wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1839	wave_inst_dw0 =
1840	wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1841	wave_inst_dw1 =
1842	wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1843	wave_ib_sts = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1844
1845	dev_info(
1846	adev->dev,
1847	"\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",
1848	simd, wave, wave_status,
1849	((uint64_t)wave_pc_hi << 32 | wave_pc_lo),
1850	((uint64_t)wave_exec_hi << 32 | wave_exec_lo),
1851	((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0),
1852	wave_ib_sts);
1853	}
1854	}
1855
1856	static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev)
1857	{
1858	uint32_t se_idx, sh_idx, cu_idx;
1859	uint32_t status;
1860
1861	mutex_lock(&adev->grbm_idx_mutex);
1862	for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;
1863	se_idx++) {
1864	for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;
1865	sh_idx++) {
1866	for (cu_idx = 0;
1867	cu_idx < adev->gfx.config.max_cu_per_sh;
1868	cu_idx++) {
1869	gfx_v9_4_2_select_se_sh(adev, se_num: se_idx, sh_num: sh_idx,
1870	instance: cu_idx);
1871	status = RREG32_SOC15(GC, 0,
1872	regSQ_TIMEOUT_STATUS);
1873	if (status != 0) {
1874	dev_info(
1875	adev->dev,
1876	"GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",
1877	se_idx, sh_idx, cu_idx);
1878	gfx_v9_4_2_log_cu_timeout_status(
1879	adev, status);
1880	}
1881	/* clear old status */
1882	WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0);
1883	}
1884	}
1885	}
1886	gfx_v9_4_2_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff);
1887	mutex_unlock(lock: &adev->grbm_idx_mutex);
1888	}
1889
1890	static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev)
1891	{
1892	uint32_t se_idx, sh_idx, cu_idx;
1893
1894	mutex_lock(&adev->grbm_idx_mutex);
1895	for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;
1896	se_idx++) {
1897	for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;
1898	sh_idx++) {
1899	for (cu_idx = 0;
1900	cu_idx < adev->gfx.config.max_cu_per_sh;
1901	cu_idx++) {
1902	gfx_v9_4_2_select_se_sh(adev, se_num: se_idx, sh_num: sh_idx,
1903	instance: cu_idx);
1904	WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0);
1905	}
1906	}
1907	}
1908	gfx_v9_4_2_select_se_sh(adev, se_num: 0xffffffff, sh_num: 0xffffffff, instance: 0xffffffff);
1909	mutex_unlock(lock: &adev->grbm_idx_mutex);
1910	}
1911
1912
1913
1914	struct amdgpu_ras_block_hw_ops gfx_v9_4_2_ras_ops = {
1915	.query_ras_error_count = &gfx_v9_4_2_query_ras_error_count,
1916	.reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count,
1917	.query_ras_error_status = &gfx_v9_4_2_query_ras_error_status,
1918	.reset_ras_error_status = &gfx_v9_4_2_reset_ras_error_status,
1919	};
1920
1921	struct amdgpu_gfx_ras gfx_v9_4_2_ras = {
1922	.ras_block = {
1923	.hw_ops = &gfx_v9_4_2_ras_ops,
1924	},
1925	.enable_watchdog_timer = &gfx_v9_4_2_enable_watchdog_timer,
1926	};
1927