1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53
54#include <drm/ttm/ttm_bo.h>
55#include <drm/ttm/ttm_placement.h>
56
57#include <drm/amdgpu_drm.h>
58#include <drm/drm_gem.h>
59#include <drm/drm_ioctl.h>
60
61#include <kgd_kfd_interface.h>
62#include "dm_pp_interface.h"
63#include "kgd_pp_interface.h"
64
65#include "amd_shared.h"
66#include "amdgpu_mode.h"
67#include "amdgpu_ih.h"
68#include "amdgpu_irq.h"
69#include "amdgpu_ucode.h"
70#include "amdgpu_ttm.h"
71#include "amdgpu_psp.h"
72#include "amdgpu_gds.h"
73#include "amdgpu_sync.h"
74#include "amdgpu_ring.h"
75#include "amdgpu_vm.h"
76#include "amdgpu_dpm.h"
77#include "amdgpu_acp.h"
78#include "amdgpu_uvd.h"
79#include "amdgpu_vce.h"
80#include "amdgpu_vcn.h"
81#include "amdgpu_jpeg.h"
82#include "amdgpu_vpe.h"
83#include "amdgpu_umsch_mm.h"
84#include "amdgpu_gmc.h"
85#include "amdgpu_gfx.h"
86#include "amdgpu_sdma.h"
87#include "amdgpu_lsdma.h"
88#include "amdgpu_nbio.h"
89#include "amdgpu_hdp.h"
90#include "amdgpu_dm.h"
91#include "amdgpu_virt.h"
92#include "amdgpu_csa.h"
93#include "amdgpu_mes_ctx.h"
94#include "amdgpu_gart.h"
95#include "amdgpu_debugfs.h"
96#include "amdgpu_job.h"
97#include "amdgpu_bo_list.h"
98#include "amdgpu_gem.h"
99#include "amdgpu_doorbell.h"
100#include "amdgpu_amdkfd.h"
101#include "amdgpu_discovery.h"
102#include "amdgpu_mes.h"
103#include "amdgpu_umc.h"
104#include "amdgpu_mmhub.h"
105#include "amdgpu_gfxhub.h"
106#include "amdgpu_df.h"
107#include "amdgpu_smuio.h"
108#include "amdgpu_fdinfo.h"
109#include "amdgpu_mca.h"
110#include "amdgpu_ras.h"
111#include "amdgpu_xcp.h"
112
113#define MAX_GPU_INSTANCE 64
114
115struct amdgpu_gpu_instance
116{
117 struct amdgpu_device *adev;
118 int mgpu_fan_enabled;
119};
120
121struct amdgpu_mgpu_info
122{
123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
124 struct mutex mutex;
125 uint32_t num_gpu;
126 uint32_t num_dgpu;
127 uint32_t num_apu;
128
129 /* delayed reset_func for XGMI configuration if necessary */
130 struct delayed_work delayed_reset_work;
131 bool pending_reset;
132};
133
134enum amdgpu_ss {
135 AMDGPU_SS_DRV_LOAD,
136 AMDGPU_SS_DEV_D0,
137 AMDGPU_SS_DEV_D3,
138 AMDGPU_SS_DRV_UNLOAD
139};
140
141struct amdgpu_watchdog_timer
142{
143 bool timeout_fatal_disable;
144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
145};
146
147#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
148
149/*
150 * Modules parameters.
151 */
152extern int amdgpu_modeset;
153extern unsigned int amdgpu_vram_limit;
154extern int amdgpu_vis_vram_limit;
155extern int amdgpu_gart_size;
156extern int amdgpu_gtt_size;
157extern int amdgpu_moverate;
158extern int amdgpu_audio;
159extern int amdgpu_disp_priority;
160extern int amdgpu_hw_i2c;
161extern int amdgpu_pcie_gen2;
162extern int amdgpu_msi;
163extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
164extern int amdgpu_dpm;
165extern int amdgpu_fw_load_type;
166extern int amdgpu_aspm;
167extern int amdgpu_runtime_pm;
168extern uint amdgpu_ip_block_mask;
169extern int amdgpu_bapm;
170extern int amdgpu_deep_color;
171extern int amdgpu_vm_size;
172extern int amdgpu_vm_block_size;
173extern int amdgpu_vm_fragment_size;
174extern int amdgpu_vm_fault_stop;
175extern int amdgpu_vm_debug;
176extern int amdgpu_vm_update_mode;
177extern int amdgpu_exp_hw_support;
178extern int amdgpu_dc;
179extern int amdgpu_sched_jobs;
180extern int amdgpu_sched_hw_submission;
181extern uint amdgpu_pcie_gen_cap;
182extern uint amdgpu_pcie_lane_cap;
183extern u64 amdgpu_cg_mask;
184extern uint amdgpu_pg_mask;
185extern uint amdgpu_sdma_phase_quantum;
186extern char *amdgpu_disable_cu;
187extern char *amdgpu_virtual_display;
188extern uint amdgpu_pp_feature_mask;
189extern uint amdgpu_force_long_training;
190extern int amdgpu_lbpw;
191extern int amdgpu_compute_multipipe;
192extern int amdgpu_gpu_recovery;
193extern int amdgpu_emu_mode;
194extern uint amdgpu_smu_memory_pool_size;
195extern int amdgpu_smu_pptable_id;
196extern uint amdgpu_dc_feature_mask;
197extern uint amdgpu_dc_debug_mask;
198extern uint amdgpu_dc_visual_confirm;
199extern uint amdgpu_dm_abm_level;
200extern int amdgpu_backlight;
201extern struct amdgpu_mgpu_info mgpu_info;
202extern int amdgpu_ras_enable;
203extern uint amdgpu_ras_mask;
204extern int amdgpu_bad_page_threshold;
205extern bool amdgpu_ignore_bad_page_threshold;
206extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
207extern int amdgpu_async_gfx_ring;
208extern int amdgpu_mcbp;
209extern int amdgpu_discovery;
210extern int amdgpu_mes;
211extern int amdgpu_mes_kiq;
212extern int amdgpu_noretry;
213extern int amdgpu_force_asic_type;
214extern int amdgpu_smartshift_bias;
215extern int amdgpu_use_xgmi_p2p;
216extern int amdgpu_mtype_local;
217extern bool enforce_isolation;
218#ifdef CONFIG_HSA_AMD
219extern int sched_policy;
220extern bool debug_evictions;
221extern bool no_system_mem_limit;
222extern int halt_if_hws_hang;
223#else
224static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
225static const bool __maybe_unused debug_evictions; /* = false */
226static const bool __maybe_unused no_system_mem_limit;
227static const int __maybe_unused halt_if_hws_hang;
228#endif
229#ifdef CONFIG_HSA_AMD_P2P
230extern bool pcie_p2p;
231#endif
232
233extern int amdgpu_tmz;
234extern int amdgpu_reset_method;
235
236#ifdef CONFIG_DRM_AMDGPU_SI
237extern int amdgpu_si_support;
238#endif
239#ifdef CONFIG_DRM_AMDGPU_CIK
240extern int amdgpu_cik_support;
241#endif
242extern int amdgpu_num_kcq;
243
244#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
245extern int amdgpu_vcnfw_log;
246extern int amdgpu_sg_display;
247extern int amdgpu_umsch_mm;
248extern int amdgpu_seamless;
249
250extern int amdgpu_user_partt_mode;
251
252#define AMDGPU_VM_MAX_NUM_CTX 4096
253#define AMDGPU_SG_THRESHOLD (256*1024*1024)
254#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
255#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
256#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
257#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
258#define AMDGPUFB_CONN_LIMIT 4
259#define AMDGPU_BIOS_NUM_SCRATCH 16
260
261#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
262
263/* hard reset data */
264#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
265
266/* reset flags */
267#define AMDGPU_RESET_GFX (1 << 0)
268#define AMDGPU_RESET_COMPUTE (1 << 1)
269#define AMDGPU_RESET_DMA (1 << 2)
270#define AMDGPU_RESET_CP (1 << 3)
271#define AMDGPU_RESET_GRBM (1 << 4)
272#define AMDGPU_RESET_DMA1 (1 << 5)
273#define AMDGPU_RESET_RLC (1 << 6)
274#define AMDGPU_RESET_SEM (1 << 7)
275#define AMDGPU_RESET_IH (1 << 8)
276#define AMDGPU_RESET_VMC (1 << 9)
277#define AMDGPU_RESET_MC (1 << 10)
278#define AMDGPU_RESET_DISPLAY (1 << 11)
279#define AMDGPU_RESET_UVD (1 << 12)
280#define AMDGPU_RESET_VCE (1 << 13)
281#define AMDGPU_RESET_VCE1 (1 << 14)
282
283/* max cursor sizes (in pixels) */
284#define CIK_CURSOR_WIDTH 128
285#define CIK_CURSOR_HEIGHT 128
286
287/* smart shift bias level limits */
288#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
289#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
290
291/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
292#define AMDGPU_SWCTF_EXTRA_DELAY 50
293
294struct amdgpu_xcp_mgr;
295struct amdgpu_device;
296struct amdgpu_irq_src;
297struct amdgpu_fpriv;
298struct amdgpu_bo_va_mapping;
299struct kfd_vm_fault_info;
300struct amdgpu_hive_info;
301struct amdgpu_reset_context;
302struct amdgpu_reset_control;
303
304enum amdgpu_cp_irq {
305 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
306 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
307 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
308 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
309 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
310 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
311 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
312 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
313 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
314 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
315
316 AMDGPU_CP_IRQ_LAST
317};
318
319enum amdgpu_thermal_irq {
320 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
321 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
322
323 AMDGPU_THERMAL_IRQ_LAST
324};
325
326enum amdgpu_kiq_irq {
327 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
328 AMDGPU_CP_KIQ_IRQ_LAST
329};
330#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
331#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
332#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
333#define MAX_KIQ_REG_TRY 1000
334
335int amdgpu_device_ip_set_clockgating_state(void *dev,
336 enum amd_ip_block_type block_type,
337 enum amd_clockgating_state state);
338int amdgpu_device_ip_set_powergating_state(void *dev,
339 enum amd_ip_block_type block_type,
340 enum amd_powergating_state state);
341void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
342 u64 *flags);
343int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
344 enum amd_ip_block_type block_type);
345bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
346 enum amd_ip_block_type block_type);
347
348#define AMDGPU_MAX_IP_NUM 16
349
350struct amdgpu_ip_block_status {
351 bool valid;
352 bool sw;
353 bool hw;
354 bool late_initialized;
355 bool hang;
356};
357
358struct amdgpu_ip_block_version {
359 const enum amd_ip_block_type type;
360 const u32 major;
361 const u32 minor;
362 const u32 rev;
363 const struct amd_ip_funcs *funcs;
364};
365
366struct amdgpu_ip_block {
367 struct amdgpu_ip_block_status status;
368 const struct amdgpu_ip_block_version *version;
369};
370
371int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
372 enum amd_ip_block_type type,
373 u32 major, u32 minor);
374
375struct amdgpu_ip_block *
376amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
377 enum amd_ip_block_type type);
378
379int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
380 const struct amdgpu_ip_block_version *ip_block_version);
381
382/*
383 * BIOS.
384 */
385bool amdgpu_get_bios(struct amdgpu_device *adev);
386bool amdgpu_read_bios(struct amdgpu_device *adev);
387bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
388 u8 *bios, u32 length_bytes);
389/*
390 * Clocks
391 */
392
393#define AMDGPU_MAX_PPLL 3
394
395struct amdgpu_clock {
396 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
397 struct amdgpu_pll spll;
398 struct amdgpu_pll mpll;
399 /* 10 Khz units */
400 uint32_t default_mclk;
401 uint32_t default_sclk;
402 uint32_t default_dispclk;
403 uint32_t current_dispclk;
404 uint32_t dp_extclk;
405 uint32_t max_pixel_clock;
406};
407
408/* sub-allocation manager, it has to be protected by another lock.
409 * By conception this is an helper for other part of the driver
410 * like the indirect buffer or semaphore, which both have their
411 * locking.
412 *
413 * Principe is simple, we keep a list of sub allocation in offset
414 * order (first entry has offset == 0, last entry has the highest
415 * offset).
416 *
417 * When allocating new object we first check if there is room at
418 * the end total_size - (last_object_offset + last_object_size) >=
419 * alloc_size. If so we allocate new object there.
420 *
421 * When there is not enough room at the end, we start waiting for
422 * each sub object until we reach object_offset+object_size >=
423 * alloc_size, this object then become the sub object we return.
424 *
425 * Alignment can't be bigger than page size.
426 *
427 * Hole are not considered for allocation to keep things simple.
428 * Assumption is that there won't be hole (all object on same
429 * alignment).
430 */
431
432struct amdgpu_sa_manager {
433 struct drm_suballoc_manager base;
434 struct amdgpu_bo *bo;
435 uint64_t gpu_addr;
436 void *cpu_ptr;
437};
438
439int amdgpu_fence_slab_init(void);
440void amdgpu_fence_slab_fini(void);
441
442/*
443 * IRQS.
444 */
445
446struct amdgpu_flip_work {
447 struct delayed_work flip_work;
448 struct work_struct unpin_work;
449 struct amdgpu_device *adev;
450 int crtc_id;
451 u32 target_vblank;
452 uint64_t base;
453 struct drm_pending_vblank_event *event;
454 struct amdgpu_bo *old_abo;
455 unsigned shared_count;
456 struct dma_fence **shared;
457 struct dma_fence_cb cb;
458 bool async;
459};
460
461
462/*
463 * file private structure
464 */
465
466struct amdgpu_fpriv {
467 struct amdgpu_vm vm;
468 struct amdgpu_bo_va *prt_va;
469 struct amdgpu_bo_va *csa_va;
470 struct mutex bo_list_lock;
471 struct idr bo_list_handles;
472 struct amdgpu_ctx_mgr ctx_mgr;
473 /** GPU partition selection */
474 uint32_t xcp_id;
475};
476
477int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
478
479/*
480 * Writeback
481 */
482#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
483
484struct amdgpu_wb {
485 struct amdgpu_bo *wb_obj;
486 volatile uint32_t *wb;
487 uint64_t gpu_addr;
488 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
489 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
490};
491
492int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
493void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
494
495/*
496 * Benchmarking
497 */
498int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
499
500/*
501 * ASIC specific register table accessible by UMD
502 */
503struct amdgpu_allowed_register_entry {
504 uint32_t reg_offset;
505 bool grbm_indexed;
506};
507
508enum amd_reset_method {
509 AMD_RESET_METHOD_NONE = -1,
510 AMD_RESET_METHOD_LEGACY = 0,
511 AMD_RESET_METHOD_MODE0,
512 AMD_RESET_METHOD_MODE1,
513 AMD_RESET_METHOD_MODE2,
514 AMD_RESET_METHOD_BACO,
515 AMD_RESET_METHOD_PCI,
516};
517
518struct amdgpu_video_codec_info {
519 u32 codec_type;
520 u32 max_width;
521 u32 max_height;
522 u32 max_pixels_per_frame;
523 u32 max_level;
524};
525
526#define codec_info_build(type, width, height, level) \
527 .codec_type = type,\
528 .max_width = width,\
529 .max_height = height,\
530 .max_pixels_per_frame = height * width,\
531 .max_level = level,
532
533struct amdgpu_video_codecs {
534 const u32 codec_count;
535 const struct amdgpu_video_codec_info *codec_array;
536};
537
538/*
539 * ASIC specific functions.
540 */
541struct amdgpu_asic_funcs {
542 bool (*read_disabled_bios)(struct amdgpu_device *adev);
543 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
544 u8 *bios, u32 length_bytes);
545 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
546 u32 sh_num, u32 reg_offset, u32 *value);
547 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
548 int (*reset)(struct amdgpu_device *adev);
549 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
550 /* get the reference clock */
551 u32 (*get_xclk)(struct amdgpu_device *adev);
552 /* MM block clocks */
553 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
554 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
555 /* static power management */
556 int (*get_pcie_lanes)(struct amdgpu_device *adev);
557 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
558 /* get config memsize register */
559 u32 (*get_config_memsize)(struct amdgpu_device *adev);
560 /* flush hdp write queue */
561 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
562 /* invalidate hdp read cache */
563 void (*invalidate_hdp)(struct amdgpu_device *adev,
564 struct amdgpu_ring *ring);
565 /* check if the asic needs a full reset of if soft reset will work */
566 bool (*need_full_reset)(struct amdgpu_device *adev);
567 /* initialize doorbell layout for specific asic*/
568 void (*init_doorbell_index)(struct amdgpu_device *adev);
569 /* PCIe bandwidth usage */
570 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
571 uint64_t *count1);
572 /* do we need to reset the asic at init time (e.g., kexec) */
573 bool (*need_reset_on_init)(struct amdgpu_device *adev);
574 /* PCIe replay counter */
575 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
576 /* device supports BACO */
577 bool (*supports_baco)(struct amdgpu_device *adev);
578 /* pre asic_init quirks */
579 void (*pre_asic_init)(struct amdgpu_device *adev);
580 /* enter/exit umd stable pstate */
581 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
582 /* query video codecs */
583 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
584 const struct amdgpu_video_codecs **codecs);
585 /* encode "> 32bits" smn addressing */
586 u64 (*encode_ext_smn_addressing)(int ext_id);
587};
588
589/*
590 * IOCTL.
591 */
592int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
593 struct drm_file *filp);
594
595int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
596int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
597 struct drm_file *filp);
598int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
599int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
600 struct drm_file *filp);
601
602/* VRAM scratch page for HDP bug, default vram page */
603struct amdgpu_mem_scratch {
604 struct amdgpu_bo *robj;
605 volatile uint32_t *ptr;
606 u64 gpu_addr;
607};
608
609/*
610 * CGS
611 */
612struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
613void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
614
615/*
616 * Core structure, functions and helpers.
617 */
618typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
619typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
620
621typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
622typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
623
624typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
625typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
626
627typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
628typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
629
630typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
631typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
632
633struct amdgpu_mmio_remap {
634 u32 reg_offset;
635 resource_size_t bus_addr;
636};
637
638/* Define the HW IP blocks will be used in driver , add more if necessary */
639enum amd_hw_ip_block_type {
640 GC_HWIP = 1,
641 HDP_HWIP,
642 SDMA0_HWIP,
643 SDMA1_HWIP,
644 SDMA2_HWIP,
645 SDMA3_HWIP,
646 SDMA4_HWIP,
647 SDMA5_HWIP,
648 SDMA6_HWIP,
649 SDMA7_HWIP,
650 LSDMA_HWIP,
651 MMHUB_HWIP,
652 ATHUB_HWIP,
653 NBIO_HWIP,
654 MP0_HWIP,
655 MP1_HWIP,
656 UVD_HWIP,
657 VCN_HWIP = UVD_HWIP,
658 JPEG_HWIP = VCN_HWIP,
659 VCN1_HWIP,
660 VCE_HWIP,
661 VPE_HWIP,
662 DF_HWIP,
663 DCE_HWIP,
664 OSSSYS_HWIP,
665 SMUIO_HWIP,
666 PWR_HWIP,
667 NBIF_HWIP,
668 THM_HWIP,
669 CLK_HWIP,
670 UMC_HWIP,
671 RSMU_HWIP,
672 XGMI_HWIP,
673 DCI_HWIP,
674 PCIE_HWIP,
675 MAX_HWIP
676};
677
678#define HWIP_MAX_INSTANCE 44
679
680#define HW_ID_MAX 300
681#define IP_VERSION_FULL(mj, mn, rv, var, srev) \
682 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
683#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
684#define IP_VERSION_MAJ(ver) ((ver) >> 24)
685#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
686#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
687#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
688#define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
689#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
690
691struct amdgpu_ip_map_info {
692 /* Map of logical to actual dev instances/mask */
693 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
694 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
695 enum amd_hw_ip_block_type block,
696 int8_t inst);
697 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
698 enum amd_hw_ip_block_type block,
699 uint32_t mask);
700};
701
702struct amd_powerplay {
703 void *pp_handle;
704 const struct amd_pm_funcs *pp_funcs;
705};
706
707struct ip_discovery_top;
708
709/* polaris10 kickers */
710#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
711 ((rid == 0xE3) || \
712 (rid == 0xE4) || \
713 (rid == 0xE5) || \
714 (rid == 0xE7) || \
715 (rid == 0xEF))) || \
716 ((did == 0x6FDF) && \
717 ((rid == 0xE7) || \
718 (rid == 0xEF) || \
719 (rid == 0xFF))))
720
721#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
722 ((rid == 0xE1) || \
723 (rid == 0xF7)))
724
725/* polaris11 kickers */
726#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
727 ((rid == 0xE0) || \
728 (rid == 0xE5))) || \
729 ((did == 0x67FF) && \
730 ((rid == 0xCF) || \
731 (rid == 0xEF) || \
732 (rid == 0xFF))))
733
734#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
735 ((rid == 0xE2)))
736
737/* polaris12 kickers */
738#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
739 ((rid == 0xC0) || \
740 (rid == 0xC1) || \
741 (rid == 0xC3) || \
742 (rid == 0xC7))) || \
743 ((did == 0x6981) && \
744 ((rid == 0x00) || \
745 (rid == 0x01) || \
746 (rid == 0x10))))
747
748struct amdgpu_mqd_prop {
749 uint64_t mqd_gpu_addr;
750 uint64_t hqd_base_gpu_addr;
751 uint64_t rptr_gpu_addr;
752 uint64_t wptr_gpu_addr;
753 uint32_t queue_size;
754 bool use_doorbell;
755 uint32_t doorbell_index;
756 uint64_t eop_gpu_addr;
757 uint32_t hqd_pipe_priority;
758 uint32_t hqd_queue_priority;
759 bool hqd_active;
760};
761
762struct amdgpu_mqd {
763 unsigned mqd_size;
764 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
765 struct amdgpu_mqd_prop *p);
766};
767
768#define AMDGPU_RESET_MAGIC_NUM 64
769#define AMDGPU_MAX_DF_PERFMONS 4
770struct amdgpu_reset_domain;
771struct amdgpu_fru_info;
772
773struct amdgpu_reset_info {
774 /* reset dump register */
775 u32 *reset_dump_reg_list;
776 u32 *reset_dump_reg_value;
777 int num_regs;
778
779#ifdef CONFIG_DEV_COREDUMP
780 struct amdgpu_coredump_info *coredump_info;
781#endif
782};
783
784/*
785 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
786 */
787#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
788
789struct amdgpu_device {
790 struct device *dev;
791 struct pci_dev *pdev;
792 struct drm_device ddev;
793
794#ifdef CONFIG_DRM_AMD_ACP
795 struct amdgpu_acp acp;
796#endif
797 struct amdgpu_hive_info *hive;
798 struct amdgpu_xcp_mgr *xcp_mgr;
799 /* ASIC */
800 enum amd_asic_type asic_type;
801 uint32_t family;
802 uint32_t rev_id;
803 uint32_t external_rev_id;
804 unsigned long flags;
805 unsigned long apu_flags;
806 int usec_timeout;
807 const struct amdgpu_asic_funcs *asic_funcs;
808 bool shutdown;
809 bool need_swiotlb;
810 bool accel_working;
811 struct notifier_block acpi_nb;
812 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
813 struct debugfs_blob_wrapper debugfs_vbios_blob;
814 struct debugfs_blob_wrapper debugfs_discovery_blob;
815 struct mutex srbm_mutex;
816 /* GRBM index mutex. Protects concurrent access to GRBM index */
817 struct mutex grbm_idx_mutex;
818 struct dev_pm_domain vga_pm_domain;
819 bool have_disp_power_ref;
820 bool have_atomics_support;
821
822 /* BIOS */
823 bool is_atom_fw;
824 uint8_t *bios;
825 uint32_t bios_size;
826 uint32_t bios_scratch_reg_offset;
827 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
828
829 /* Register/doorbell mmio */
830 resource_size_t rmmio_base;
831 resource_size_t rmmio_size;
832 void __iomem *rmmio;
833 /* protects concurrent MM_INDEX/DATA based register access */
834 spinlock_t mmio_idx_lock;
835 struct amdgpu_mmio_remap rmmio_remap;
836 /* protects concurrent SMC based register access */
837 spinlock_t smc_idx_lock;
838 amdgpu_rreg_t smc_rreg;
839 amdgpu_wreg_t smc_wreg;
840 /* protects concurrent PCIE register access */
841 spinlock_t pcie_idx_lock;
842 amdgpu_rreg_t pcie_rreg;
843 amdgpu_wreg_t pcie_wreg;
844 amdgpu_rreg_t pciep_rreg;
845 amdgpu_wreg_t pciep_wreg;
846 amdgpu_rreg_ext_t pcie_rreg_ext;
847 amdgpu_wreg_ext_t pcie_wreg_ext;
848 amdgpu_rreg64_t pcie_rreg64;
849 amdgpu_wreg64_t pcie_wreg64;
850 amdgpu_rreg64_ext_t pcie_rreg64_ext;
851 amdgpu_wreg64_ext_t pcie_wreg64_ext;
852 /* protects concurrent UVD register access */
853 spinlock_t uvd_ctx_idx_lock;
854 amdgpu_rreg_t uvd_ctx_rreg;
855 amdgpu_wreg_t uvd_ctx_wreg;
856 /* protects concurrent DIDT register access */
857 spinlock_t didt_idx_lock;
858 amdgpu_rreg_t didt_rreg;
859 amdgpu_wreg_t didt_wreg;
860 /* protects concurrent gc_cac register access */
861 spinlock_t gc_cac_idx_lock;
862 amdgpu_rreg_t gc_cac_rreg;
863 amdgpu_wreg_t gc_cac_wreg;
864 /* protects concurrent se_cac register access */
865 spinlock_t se_cac_idx_lock;
866 amdgpu_rreg_t se_cac_rreg;
867 amdgpu_wreg_t se_cac_wreg;
868 /* protects concurrent ENDPOINT (audio) register access */
869 spinlock_t audio_endpt_idx_lock;
870 amdgpu_block_rreg_t audio_endpt_rreg;
871 amdgpu_block_wreg_t audio_endpt_wreg;
872 struct amdgpu_doorbell doorbell;
873
874 /* clock/pll info */
875 struct amdgpu_clock clock;
876
877 /* MC */
878 struct amdgpu_gmc gmc;
879 struct amdgpu_gart gart;
880 dma_addr_t dummy_page_addr;
881 struct amdgpu_vm_manager vm_manager;
882 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
883 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
884
885 /* memory management */
886 struct amdgpu_mman mman;
887 struct amdgpu_mem_scratch mem_scratch;
888 struct amdgpu_wb wb;
889 atomic64_t num_bytes_moved;
890 atomic64_t num_evictions;
891 atomic64_t num_vram_cpu_page_faults;
892 atomic_t gpu_reset_counter;
893 atomic_t vram_lost_counter;
894
895 /* data for buffer migration throttling */
896 struct {
897 spinlock_t lock;
898 s64 last_update_us;
899 s64 accum_us; /* accumulated microseconds */
900 s64 accum_us_vis; /* for visible VRAM */
901 u32 log2_max_MBps;
902 } mm_stats;
903
904 /* display */
905 bool enable_virtual_display;
906 struct amdgpu_vkms_output *amdgpu_vkms_output;
907 struct amdgpu_mode_info mode_info;
908 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
909 struct delayed_work hotplug_work;
910 struct amdgpu_irq_src crtc_irq;
911 struct amdgpu_irq_src vline0_irq;
912 struct amdgpu_irq_src vupdate_irq;
913 struct amdgpu_irq_src pageflip_irq;
914 struct amdgpu_irq_src hpd_irq;
915 struct amdgpu_irq_src dmub_trace_irq;
916 struct amdgpu_irq_src dmub_outbox_irq;
917
918 /* rings */
919 u64 fence_context;
920 unsigned num_rings;
921 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
922 struct dma_fence __rcu *gang_submit;
923 bool ib_pool_ready;
924 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
925 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
926
927 /* interrupts */
928 struct amdgpu_irq irq;
929
930 /* powerplay */
931 struct amd_powerplay powerplay;
932 struct amdgpu_pm pm;
933 u64 cg_flags;
934 u32 pg_flags;
935
936 /* nbio */
937 struct amdgpu_nbio nbio;
938
939 /* hdp */
940 struct amdgpu_hdp hdp;
941
942 /* smuio */
943 struct amdgpu_smuio smuio;
944
945 /* mmhub */
946 struct amdgpu_mmhub mmhub;
947
948 /* gfxhub */
949 struct amdgpu_gfxhub gfxhub;
950
951 /* gfx */
952 struct amdgpu_gfx gfx;
953
954 /* sdma */
955 struct amdgpu_sdma sdma;
956
957 /* lsdma */
958 struct amdgpu_lsdma lsdma;
959
960 /* uvd */
961 struct amdgpu_uvd uvd;
962
963 /* vce */
964 struct amdgpu_vce vce;
965
966 /* vcn */
967 struct amdgpu_vcn vcn;
968
969 /* jpeg */
970 struct amdgpu_jpeg jpeg;
971
972 /* vpe */
973 struct amdgpu_vpe vpe;
974
975 /* umsch */
976 struct amdgpu_umsch_mm umsch_mm;
977 bool enable_umsch_mm;
978
979 /* firmwares */
980 struct amdgpu_firmware firmware;
981
982 /* PSP */
983 struct psp_context psp;
984
985 /* GDS */
986 struct amdgpu_gds gds;
987
988 /* KFD */
989 struct amdgpu_kfd_dev kfd;
990
991 /* UMC */
992 struct amdgpu_umc umc;
993
994 /* display related functionality */
995 struct amdgpu_display_manager dm;
996
997 /* mes */
998 bool enable_mes;
999 bool enable_mes_kiq;
1000 struct amdgpu_mes mes;
1001 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1002
1003 /* df */
1004 struct amdgpu_df df;
1005
1006 /* MCA */
1007 struct amdgpu_mca mca;
1008
1009 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1010 uint32_t harvest_ip_mask;
1011 int num_ip_blocks;
1012 struct mutex mn_lock;
1013 DECLARE_HASHTABLE(mn_hash, 7);
1014
1015 /* tracking pinned memory */
1016 atomic64_t vram_pin_size;
1017 atomic64_t visible_pin_size;
1018 atomic64_t gart_pin_size;
1019
1020 /* soc15 register offset based on ip, instance and segment */
1021 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1022 struct amdgpu_ip_map_info ip_map;
1023
1024 /* delayed work_func for deferring clockgating during resume */
1025 struct delayed_work delayed_init_work;
1026
1027 struct amdgpu_virt virt;
1028
1029 /* link all shadow bo */
1030 struct list_head shadow_list;
1031 struct mutex shadow_list_lock;
1032
1033 /* record hw reset is performed */
1034 bool has_hw_reset;
1035 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1036
1037 /* s3/s4 mask */
1038 bool in_suspend;
1039 bool in_s3;
1040 bool in_s4;
1041 bool in_s0ix;
1042
1043 enum pp_mp1_state mp1_state;
1044 struct amdgpu_doorbell_index doorbell_index;
1045
1046 struct mutex notifier_lock;
1047
1048 int asic_reset_res;
1049 struct work_struct xgmi_reset_work;
1050 struct list_head reset_list;
1051
1052 long gfx_timeout;
1053 long sdma_timeout;
1054 long video_timeout;
1055 long compute_timeout;
1056
1057 uint64_t unique_id;
1058 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1059
1060 /* enable runtime pm on the device */
1061 bool in_runpm;
1062 bool has_pr3;
1063
1064 bool ucode_sysfs_en;
1065
1066 struct amdgpu_fru_info *fru_info;
1067 atomic_t throttling_logging_enabled;
1068 struct ratelimit_state throttling_logging_rs;
1069 uint32_t ras_hw_enabled;
1070 uint32_t ras_enabled;
1071
1072 bool no_hw_access;
1073 struct pci_saved_state *pci_state;
1074 pci_channel_state_t pci_channel_state;
1075
1076 /* Track auto wait count on s_barrier settings */
1077 bool barrier_has_auto_waitcnt;
1078
1079 struct amdgpu_reset_control *reset_cntl;
1080 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1081
1082 bool ram_is_direct_mapped;
1083
1084 struct list_head ras_list;
1085
1086 struct ip_discovery_top *ip_top;
1087
1088 struct amdgpu_reset_domain *reset_domain;
1089
1090 struct mutex benchmark_mutex;
1091
1092 struct amdgpu_reset_info reset_info;
1093
1094 bool scpm_enabled;
1095 uint32_t scpm_status;
1096
1097 struct work_struct reset_work;
1098
1099 bool job_hang;
1100 bool dc_enabled;
1101 /* Mask of active clusters */
1102 uint32_t aid_mask;
1103
1104 /* Debug */
1105 bool debug_vm;
1106 bool debug_largebar;
1107 bool debug_disable_soft_recovery;
1108};
1109
1110static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1111 uint8_t ip, uint8_t inst)
1112{
1113 /* This considers only major/minor/rev and ignores
1114 * subrevision/variant fields.
1115 */
1116 return adev->ip_versions[ip][inst] & ~0xFFU;
1117}
1118
1119static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1120 uint8_t ip, uint8_t inst)
1121{
1122 /* This returns full version - major/minor/rev/variant/subrevision */
1123 return adev->ip_versions[ip][inst];
1124}
1125
1126static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1127{
1128 return container_of(ddev, struct amdgpu_device, ddev);
1129}
1130
1131static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1132{
1133 return &adev->ddev;
1134}
1135
1136static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1137{
1138 return container_of(bdev, struct amdgpu_device, mman.bdev);
1139}
1140
1141int amdgpu_device_init(struct amdgpu_device *adev,
1142 uint32_t flags);
1143void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1144void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1145
1146int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1147
1148void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1149 void *buf, size_t size, bool write);
1150size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1151 void *buf, size_t size, bool write);
1152
1153void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1154 void *buf, size_t size, bool write);
1155uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1156 uint32_t inst, uint32_t reg_addr, char reg_name[],
1157 uint32_t expected_value, uint32_t mask);
1158uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1159 uint32_t reg, uint32_t acc_flags);
1160u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1161 u64 reg_addr);
1162void amdgpu_device_wreg(struct amdgpu_device *adev,
1163 uint32_t reg, uint32_t v,
1164 uint32_t acc_flags);
1165void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1166 u64 reg_addr, u32 reg_data);
1167void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1168 uint32_t reg, uint32_t v, uint32_t xcc_id);
1169void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1170uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1171
1172u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1173 u32 reg_addr);
1174u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1175 u32 reg_addr);
1176u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1177 u64 reg_addr);
1178void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1179 u32 reg_addr, u32 reg_data);
1180void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1181 u32 reg_addr, u64 reg_data);
1182void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1183 u64 reg_addr, u64 reg_data);
1184u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1185bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1186bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1187
1188void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1189
1190int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1191 struct amdgpu_reset_context *reset_context);
1192
1193int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1194 struct amdgpu_reset_context *reset_context);
1195
1196int emu_soc_asic_init(struct amdgpu_device *adev);
1197
1198/*
1199 * Registers read & write functions.
1200 */
1201#define AMDGPU_REGS_NO_KIQ (1<<1)
1202#define AMDGPU_REGS_RLC (1<<2)
1203
1204#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1205#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1206
1207#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1208#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1209
1210#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1211#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1212
1213#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1214#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1215#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1216#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1217#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1218#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1219#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1220#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1221#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1222#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1223#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1224#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1225#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1226#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1227#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1228#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1229#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1230#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1231#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1232#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1233#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1234#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1235#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1236#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1237#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1238#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1239#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1240#define WREG32_P(reg, val, mask) \
1241 do { \
1242 uint32_t tmp_ = RREG32(reg); \
1243 tmp_ &= (mask); \
1244 tmp_ |= ((val) & ~(mask)); \
1245 WREG32(reg, tmp_); \
1246 } while (0)
1247#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1248#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1249#define WREG32_PLL_P(reg, val, mask) \
1250 do { \
1251 uint32_t tmp_ = RREG32_PLL(reg); \
1252 tmp_ &= (mask); \
1253 tmp_ |= ((val) & ~(mask)); \
1254 WREG32_PLL(reg, tmp_); \
1255 } while (0)
1256
1257#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1258 do { \
1259 u32 tmp = RREG32_SMC(_Reg); \
1260 tmp &= (_Mask); \
1261 tmp |= ((_Val) & ~(_Mask)); \
1262 WREG32_SMC(_Reg, tmp); \
1263 } while (0)
1264
1265#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1266
1267#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1268#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1269
1270#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1271 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1272 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1273
1274#define REG_GET_FIELD(value, reg, field) \
1275 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1276
1277#define WREG32_FIELD(reg, field, val) \
1278 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1279
1280#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1281 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1282
1283/*
1284 * BIOS helpers.
1285 */
1286#define RBIOS8(i) (adev->bios[i])
1287#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1288#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1289
1290/*
1291 * ASICs macro.
1292 */
1293#define amdgpu_asic_set_vga_state(adev, state) \
1294 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1295#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1296#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1297#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1298#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1299#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1300#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1301#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1302#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1303#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1304#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1305#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1306#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1307#define amdgpu_asic_flush_hdp(adev, r) \
1308 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1309#define amdgpu_asic_invalidate_hdp(adev, r) \
1310 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1311 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1312#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1313#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1314#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1315#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1316#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1317#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1318#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1319#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1320 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1321#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1322
1323#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1324
1325#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1326#define for_each_inst(i, inst_mask) \
1327 for (i = ffs(inst_mask); i-- != 0; \
1328 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1329
1330/* Common functions */
1331bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1332bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1333int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1334 struct amdgpu_job *job,
1335 struct amdgpu_reset_context *reset_context);
1336void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1337int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1338bool amdgpu_device_need_post(struct amdgpu_device *adev);
1339bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1340bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1341
1342void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1343 u64 num_vis_bytes);
1344int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1345void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1346 const u32 *registers,
1347 const u32 array_size);
1348
1349int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1350bool amdgpu_device_supports_atpx(struct drm_device *dev);
1351bool amdgpu_device_supports_px(struct drm_device *dev);
1352bool amdgpu_device_supports_boco(struct drm_device *dev);
1353bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1354bool amdgpu_device_supports_baco(struct drm_device *dev);
1355bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1356 struct amdgpu_device *peer_adev);
1357int amdgpu_device_baco_enter(struct drm_device *dev);
1358int amdgpu_device_baco_exit(struct drm_device *dev);
1359
1360void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1361 struct amdgpu_ring *ring);
1362void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1363 struct amdgpu_ring *ring);
1364
1365void amdgpu_device_halt(struct amdgpu_device *adev);
1366u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1367 u32 reg);
1368void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1369 u32 reg, u32 v);
1370struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1371 struct dma_fence *gang);
1372bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1373
1374/* atpx handler */
1375#if defined(CONFIG_VGA_SWITCHEROO)
1376void amdgpu_register_atpx_handler(void);
1377void amdgpu_unregister_atpx_handler(void);
1378bool amdgpu_has_atpx_dgpu_power_cntl(void);
1379bool amdgpu_is_atpx_hybrid(void);
1380bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1381bool amdgpu_has_atpx(void);
1382#else
1383static inline void amdgpu_register_atpx_handler(void) {}
1384static inline void amdgpu_unregister_atpx_handler(void) {}
1385static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1386static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1387static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1388static inline bool amdgpu_has_atpx(void) { return false; }
1389#endif
1390
1391#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1392void *amdgpu_atpx_get_dhandle(void);
1393#else
1394static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1395#endif
1396
1397/*
1398 * KMS
1399 */
1400extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1401extern const int amdgpu_max_kms_ioctl;
1402
1403int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1404void amdgpu_driver_unload_kms(struct drm_device *dev);
1405void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1406int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1407void amdgpu_driver_postclose_kms(struct drm_device *dev,
1408 struct drm_file *file_priv);
1409void amdgpu_driver_release_kms(struct drm_device *dev);
1410
1411int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1412int amdgpu_device_prepare(struct drm_device *dev);
1413int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1414int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1415u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1416int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1417void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1418int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1419 struct drm_file *filp);
1420
1421/*
1422 * functions used by amdgpu_encoder.c
1423 */
1424struct amdgpu_afmt_acr {
1425 u32 clock;
1426
1427 int n_32khz;
1428 int cts_32khz;
1429
1430 int n_44_1khz;
1431 int cts_44_1khz;
1432
1433 int n_48khz;
1434 int cts_48khz;
1435
1436};
1437
1438struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1439
1440/* amdgpu_acpi.c */
1441
1442struct amdgpu_numa_info {
1443 uint64_t size;
1444 int pxm;
1445 int nid;
1446};
1447
1448/* ATCS Device/Driver State */
1449#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1450#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1451#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1452#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1453
1454#if defined(CONFIG_ACPI)
1455int amdgpu_acpi_init(struct amdgpu_device *adev);
1456void amdgpu_acpi_fini(struct amdgpu_device *adev);
1457bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1458bool amdgpu_acpi_is_power_shift_control_supported(void);
1459int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1460 u8 perf_req, bool advertise);
1461int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1462 u8 dev_state, bool drv_state);
1463int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1464int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1465int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1466 u64 *tmr_size);
1467int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1468 struct amdgpu_numa_info *numa_info);
1469
1470void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1471bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1472void amdgpu_acpi_detect(void);
1473void amdgpu_acpi_release(void);
1474#else
1475static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1476static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1477 u64 *tmr_offset, u64 *tmr_size)
1478{
1479 return -EINVAL;
1480}
1481static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1482 int xcc_id,
1483 struct amdgpu_numa_info *numa_info)
1484{
1485 return -EINVAL;
1486}
1487static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1488static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1489static inline void amdgpu_acpi_detect(void) { }
1490static inline void amdgpu_acpi_release(void) { }
1491static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1492static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1493 u8 dev_state, bool drv_state) { return 0; }
1494static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1495 enum amdgpu_ss ss_state) { return 0; }
1496#endif
1497
1498#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1499bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1500bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1501#else
1502static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1503static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1504#endif
1505
1506#if defined(CONFIG_DRM_AMD_DC)
1507int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1508#else
1509static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1510#endif
1511
1512
1513void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1514void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1515
1516pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1517 pci_channel_state_t state);
1518pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1519pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1520void amdgpu_pci_resume(struct pci_dev *pdev);
1521
1522bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1523bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1524
1525bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1526
1527int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1528 enum amd_clockgating_state state);
1529int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1530 enum amd_powergating_state state);
1531
1532static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1533{
1534 return amdgpu_gpu_recovery != 0 &&
1535 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1536 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1537 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1538 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1539}
1540
1541#include "amdgpu_object.h"
1542
1543static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1544{
1545 return adev->gmc.tmz_enabled;
1546}
1547
1548int amdgpu_in_reset(struct amdgpu_device *adev);
1549
1550extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1551extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1552extern const struct attribute_group amdgpu_flash_attr_group;
1553
1554#endif
1555

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h