1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32#include "ta_rap_if.h"
33#include "ta_secureDisplay_if.h"
34
35#define PSP_FENCE_BUFFER_SIZE 0x1000
36#define PSP_CMD_BUFFER_SIZE 0x1000
37#define PSP_1_MEG 0x100000
38#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39#define PSP_FW_NAME_LEN 0x24
40
41enum psp_shared_mem_size {
42 PSP_ASD_SHARED_MEM_SIZE = 0x0,
43 PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
44 PSP_RAS_SHARED_MEM_SIZE = 0x4000,
45 PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
46 PSP_DTM_SHARED_MEM_SIZE = 0x4000,
47 PSP_RAP_SHARED_MEM_SIZE = 0x4000,
48 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
49};
50
51enum ta_type_id {
52 TA_TYPE_XGMI = 1,
53 TA_TYPE_RAS,
54 TA_TYPE_HDCP,
55 TA_TYPE_DTM,
56 TA_TYPE_RAP,
57 TA_TYPE_SECUREDISPLAY,
58
59 TA_TYPE_MAX_INDEX,
60};
61
62struct psp_context;
63struct psp_xgmi_node_info;
64struct psp_xgmi_topology_info;
65struct psp_bin_desc;
66
67enum psp_bootloader_cmd {
68 PSP_BL__LOAD_SYSDRV = 0x10000,
69 PSP_BL__LOAD_SOSDRV = 0x20000,
70 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
71 PSP_BL__LOAD_SOCDRV = 0xB0000,
72 PSP_BL__LOAD_DBGDRV = 0xC0000,
73 PSP_BL__LOAD_INTFDRV = 0xD0000,
74 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
75 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
76 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
77};
78
79enum psp_ring_type
80{
81 PSP_RING_TYPE__INVALID = 0,
82 /*
83 * These values map to the way the PSP kernel identifies the
84 * rings.
85 */
86 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
87 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
88};
89
90struct psp_ring
91{
92 enum psp_ring_type ring_type;
93 struct psp_gfx_rb_frame *ring_mem;
94 uint64_t ring_mem_mc_addr;
95 void *ring_mem_handle;
96 uint32_t ring_size;
97 uint32_t ring_wptr;
98};
99
100/* More registers may will be supported */
101enum psp_reg_prog_id {
102 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
103 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
104 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
105 PSP_REG_LAST
106};
107
108struct psp_funcs
109{
110 int (*init_microcode)(struct psp_context *psp);
111 int (*bootloader_load_kdb)(struct psp_context *psp);
112 int (*bootloader_load_spl)(struct psp_context *psp);
113 int (*bootloader_load_sysdrv)(struct psp_context *psp);
114 int (*bootloader_load_soc_drv)(struct psp_context *psp);
115 int (*bootloader_load_intf_drv)(struct psp_context *psp);
116 int (*bootloader_load_dbg_drv)(struct psp_context *psp);
117 int (*bootloader_load_sos)(struct psp_context *psp);
118 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
119 int (*ring_create)(struct psp_context *psp,
120 enum psp_ring_type ring_type);
121 int (*ring_stop)(struct psp_context *psp,
122 enum psp_ring_type ring_type);
123 int (*ring_destroy)(struct psp_context *psp,
124 enum psp_ring_type ring_type);
125 bool (*smu_reload_quirk)(struct psp_context *psp);
126 int (*mode1_reset)(struct psp_context *psp);
127 int (*mem_training)(struct psp_context *psp, uint32_t ops);
128 uint32_t (*ring_get_wptr)(struct psp_context *psp);
129 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
130 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
131 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
132 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
133 int (*vbflash_stat)(struct psp_context *psp);
134};
135
136#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
137struct psp_xgmi_node_info {
138 uint64_t node_id;
139 uint8_t num_hops;
140 uint8_t is_sharing_enabled;
141 enum ta_xgmi_assigned_sdma_engine sdma_engine;
142 uint8_t num_links;
143};
144
145struct psp_xgmi_topology_info {
146 uint32_t num_nodes;
147 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
148};
149
150struct psp_bin_desc {
151 uint32_t fw_version;
152 uint32_t feature_version;
153 uint32_t size_bytes;
154 uint8_t *start_addr;
155};
156
157struct ta_mem_context {
158 struct amdgpu_bo *shared_bo;
159 uint64_t shared_mc_addr;
160 void *shared_buf;
161 enum psp_shared_mem_size shared_mem_size;
162};
163
164struct ta_context {
165 bool initialized;
166 uint32_t session_id;
167 uint32_t resp_status;
168 struct ta_mem_context mem_context;
169 struct psp_bin_desc bin_desc;
170 enum psp_gfx_cmd_id ta_load_type;
171 enum ta_type_id ta_type;
172};
173
174struct ta_cp_context {
175 struct ta_context context;
176 struct mutex mutex;
177};
178
179struct psp_xgmi_context {
180 struct ta_context context;
181 struct psp_xgmi_topology_info top_info;
182 bool supports_extended_data;
183};
184
185struct psp_ras_context {
186 struct ta_context context;
187 struct amdgpu_ras *ras;
188};
189
190#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
191#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
192#define GDDR6_MEM_TRAINING_OFFSET 0x8000
193/*Define the VRAM size that will be encroached by BIST training.*/
194#define GDDR6_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
195
196enum psp_memory_training_init_flag {
197 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
198 PSP_MEM_TRAIN_SUPPORT = 0x1,
199 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
200 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
201 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
202};
203
204enum psp_memory_training_ops {
205 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
206 PSP_MEM_TRAIN_SAVE = 0x2,
207 PSP_MEM_TRAIN_RESTORE = 0x4,
208 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
209 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
210 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
211};
212
213struct psp_memory_training_context {
214 /*training data size*/
215 u64 train_data_size;
216 /*
217 * sys_cache
218 * cpu virtual address
219 * system memory buffer that used to store the training data.
220 */
221 void *sys_cache;
222
223 /*vram offset of the p2c training data*/
224 u64 p2c_train_data_offset;
225
226 /*vram offset of the c2p training data*/
227 u64 c2p_train_data_offset;
228 struct amdgpu_bo *c2p_bo;
229
230 enum psp_memory_training_init_flag init;
231 u32 training_cnt;
232 bool enable_mem_training;
233};
234
235/** PSP runtime DB **/
236#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
237#define PSP_RUNTIME_DB_OFFSET 0x100000
238#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
239#define PSP_RUNTIME_DB_VER_1 0x0100
240#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
241
242enum psp_runtime_entry_type {
243 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
244 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
245 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
246 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
247 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
248 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
249 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
250};
251
252/* PSP runtime DB header */
253struct psp_runtime_data_header {
254 /* determine the existence of runtime db */
255 uint16_t cookie;
256 /* version of runtime db */
257 uint16_t version;
258};
259
260/* PSP runtime DB entry */
261struct psp_runtime_entry {
262 /* type of runtime db entry */
263 uint32_t entry_type;
264 /* offset of entry in bytes */
265 uint16_t offset;
266 /* size of entry in bytes */
267 uint16_t size;
268};
269
270/* PSP runtime DB directory */
271struct psp_runtime_data_directory {
272 /* number of valid entries */
273 uint16_t entry_count;
274 /* db entries*/
275 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
276};
277
278/* PSP runtime DB boot config feature bitmask */
279enum psp_runtime_boot_cfg_feature {
280 BOOT_CFG_FEATURE_GECC = 0x1,
281 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
282};
283
284/* PSP run time DB SCPM authentication defines */
285enum psp_runtime_scpm_authentication {
286 SCPM_DISABLE = 0x0,
287 SCPM_ENABLE = 0x1,
288 SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
289};
290
291/* PSP runtime DB boot config entry */
292struct psp_runtime_boot_cfg_entry {
293 uint32_t boot_cfg_bitmask;
294 uint32_t reserved;
295};
296
297/* PSP runtime DB SCPM entry */
298struct psp_runtime_scpm_entry {
299 enum psp_runtime_scpm_authentication scpm_status;
300};
301
302struct psp_context
303{
304 struct amdgpu_device *adev;
305 struct psp_ring km_ring;
306 struct psp_gfx_cmd_resp *cmd;
307
308 const struct psp_funcs *funcs;
309
310 /* firmware buffer */
311 struct amdgpu_bo *fw_pri_bo;
312 uint64_t fw_pri_mc_addr;
313 void *fw_pri_buf;
314
315 /* sos firmware */
316 const struct firmware *sos_fw;
317 struct psp_bin_desc sys;
318 struct psp_bin_desc sos;
319 struct psp_bin_desc toc;
320 struct psp_bin_desc kdb;
321 struct psp_bin_desc spl;
322 struct psp_bin_desc rl;
323 struct psp_bin_desc soc_drv;
324 struct psp_bin_desc intf_drv;
325 struct psp_bin_desc dbg_drv;
326
327 /* tmr buffer */
328 struct amdgpu_bo *tmr_bo;
329 uint64_t tmr_mc_addr;
330
331 /* asd firmware */
332 const struct firmware *asd_fw;
333
334 /* toc firmware */
335 const struct firmware *toc_fw;
336
337 /* cap firmware */
338 const struct firmware *cap_fw;
339
340 /* fence buffer */
341 struct amdgpu_bo *fence_buf_bo;
342 uint64_t fence_buf_mc_addr;
343 void *fence_buf;
344
345 /* cmd buffer */
346 struct amdgpu_bo *cmd_buf_bo;
347 uint64_t cmd_buf_mc_addr;
348 struct psp_gfx_cmd_resp *cmd_buf_mem;
349
350 /* fence value associated with cmd buffer */
351 atomic_t fence_value;
352 /* flag to mark whether gfx fw autoload is supported or not */
353 bool autoload_supported;
354 /* flag to mark whether df cstate management centralized to PMFW */
355 bool pmfw_centralized_cstate_management;
356
357 /* xgmi ta firmware and buffer */
358 const struct firmware *ta_fw;
359 uint32_t ta_fw_version;
360
361 uint32_t cap_fw_version;
362 uint32_t cap_feature_version;
363 uint32_t cap_ucode_size;
364
365 struct ta_context asd_context;
366 struct psp_xgmi_context xgmi_context;
367 struct psp_ras_context ras_context;
368 struct ta_cp_context hdcp_context;
369 struct ta_cp_context dtm_context;
370 struct ta_cp_context rap_context;
371 struct ta_cp_context securedisplay_context;
372 struct mutex mutex;
373 struct psp_memory_training_context mem_train_ctx;
374
375 uint32_t boot_cfg_bitmask;
376
377 char *vbflash_tmp_buf;
378 size_t vbflash_image_size;
379 bool vbflash_done;
380};
381
382struct amdgpu_psp_funcs {
383 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
384 enum AMDGPU_UCODE_ID);
385};
386
387
388#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
389#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
390#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
391#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
392#define psp_init_microcode(psp) \
393 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
394#define psp_bootloader_load_kdb(psp) \
395 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
396#define psp_bootloader_load_spl(psp) \
397 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
398#define psp_bootloader_load_sysdrv(psp) \
399 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
400#define psp_bootloader_load_soc_drv(psp) \
401 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
402#define psp_bootloader_load_intf_drv(psp) \
403 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
404#define psp_bootloader_load_dbg_drv(psp) \
405 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
406#define psp_bootloader_load_sos(psp) \
407 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
408#define psp_smu_reload_quirk(psp) \
409 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
410#define psp_mode1_reset(psp) \
411 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
412#define psp_mem_training(psp, ops) \
413 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
414
415#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
416#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
417
418#define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
419 ((psp)->funcs->load_usbc_pd_fw ? \
420 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
421
422#define psp_read_usbc_pd_fw(psp, fw_ver) \
423 ((psp)->funcs->read_usbc_pd_fw ? \
424 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
425
426#define psp_update_spirom(psp, fw_pri_mc_addr) \
427 ((psp)->funcs->update_spirom ? \
428 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
429
430#define psp_vbflash_status(psp) \
431 ((psp)->funcs->vbflash_stat ? \
432 (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
433
434extern const struct amd_ip_funcs psp_ip_funcs;
435
436extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
437extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
438extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
439extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
440extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
441extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
442extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
443
444extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
445 uint32_t field_val, uint32_t mask, bool check_changed);
446
447int psp_gpu_reset(struct amdgpu_device *adev);
448int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
449 uint64_t cmd_gpu_addr, int cmd_size);
450
451int psp_ta_init_shared_buf(struct psp_context *psp,
452 struct ta_mem_context *mem_ctx);
453void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
454int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
455int psp_ta_load(struct psp_context *psp, struct ta_context *context);
456int psp_ta_invoke(struct psp_context *psp,
457 uint32_t ta_cmd_id,
458 struct ta_context *context);
459int psp_ta_invoke_indirect(struct psp_context *psp,
460 uint32_t ta_cmd_id,
461 struct ta_context *context);
462
463int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
464int psp_xgmi_terminate(struct psp_context *psp);
465int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
466int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
467int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
468int psp_xgmi_get_topology_info(struct psp_context *psp,
469 int number_devices,
470 struct psp_xgmi_topology_info *topology,
471 bool get_extended_data);
472int psp_xgmi_set_topology_info(struct psp_context *psp,
473 int number_devices,
474 struct psp_xgmi_topology_info *topology);
475
476int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
477int psp_ras_enable_features(struct psp_context *psp,
478 union ta_ras_cmd_input *info, bool enable);
479int psp_ras_trigger_error(struct psp_context *psp,
480 struct ta_ras_trigger_error_input *info);
481int psp_ras_terminate(struct psp_context *psp);
482
483int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
484int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
485int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
486int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
487
488int psp_rlc_autoload_start(struct psp_context *psp);
489
490int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
491 uint32_t value);
492int psp_ring_cmd_submit(struct psp_context *psp,
493 uint64_t cmd_buf_mc_addr,
494 uint64_t fence_mc_addr,
495 int index);
496int psp_init_asd_microcode(struct psp_context *psp,
497 const char *chip_name);
498int psp_init_toc_microcode(struct psp_context *psp,
499 const char *chip_name);
500int psp_init_sos_microcode(struct psp_context *psp,
501 const char *chip_name);
502int psp_init_ta_microcode(struct psp_context *psp,
503 const char *chip_name);
504int psp_init_cap_microcode(struct psp_context *psp,
505 const char *chip_name);
506int psp_get_fw_attestation_records_addr(struct psp_context *psp,
507 uint64_t *output_ptr);
508
509int psp_load_fw_list(struct psp_context *psp,
510 struct amdgpu_firmware_info **ucode_list, int ucode_count);
511void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
512
513int is_psp_fw_valid(struct psp_bin_desc bin);
514
515int amdgpu_psp_sysfs_init(struct amdgpu_device *adev);
516void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev);
517#endif
518

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h