1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32#include "ta_rap_if.h"
33#include "ta_secureDisplay_if.h"
34
35#define PSP_FENCE_BUFFER_SIZE 0x1000
36#define PSP_CMD_BUFFER_SIZE 0x1000
37#define PSP_1_MEG 0x100000
38#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39#define PSP_TMR_ALIGNMENT 0x100000
40#define PSP_FW_NAME_LEN 0x24
41
42/* VBIOS gfl defines */
43#define MBOX_READY_MASK 0x80000000
44#define MBOX_STATUS_MASK 0x0000FFFF
45#define MBOX_COMMAND_MASK 0x00FF0000
46#define MBOX_READY_FLAG 0x80000000
47#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
48#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
49#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
50#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO 0xf
51#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10
52#define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11
53
54extern const struct attribute_group amdgpu_flash_attr_group;
55
56enum psp_shared_mem_size {
57 PSP_ASD_SHARED_MEM_SIZE = 0x0,
58 PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
59 PSP_RAS_SHARED_MEM_SIZE = 0x4000,
60 PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
61 PSP_DTM_SHARED_MEM_SIZE = 0x4000,
62 PSP_RAP_SHARED_MEM_SIZE = 0x4000,
63 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
64};
65
66enum ta_type_id {
67 TA_TYPE_XGMI = 1,
68 TA_TYPE_RAS,
69 TA_TYPE_HDCP,
70 TA_TYPE_DTM,
71 TA_TYPE_RAP,
72 TA_TYPE_SECUREDISPLAY,
73
74 TA_TYPE_MAX_INDEX,
75};
76
77struct psp_context;
78struct psp_xgmi_node_info;
79struct psp_xgmi_topology_info;
80struct psp_bin_desc;
81
82enum psp_bootloader_cmd {
83 PSP_BL__LOAD_SYSDRV = 0x10000,
84 PSP_BL__LOAD_SOSDRV = 0x20000,
85 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
86 PSP_BL__LOAD_SOCDRV = 0xB0000,
87 PSP_BL__LOAD_DBGDRV = 0xC0000,
88 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV,
89 PSP_BL__LOAD_INTFDRV = 0xD0000,
90 PSP_BL__LOAD_RASDRV = 0xE0000,
91 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000,
92 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
93 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
94 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
95 PSP_BL__LOAD_SPDMDRV = 0x20000000,
96};
97
98enum psp_ring_type {
99 PSP_RING_TYPE__INVALID = 0,
100 /*
101 * These values map to the way the PSP kernel identifies the
102 * rings.
103 */
104 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
105 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
106};
107
108struct psp_ring {
109 enum psp_ring_type ring_type;
110 struct psp_gfx_rb_frame *ring_mem;
111 uint64_t ring_mem_mc_addr;
112 void *ring_mem_handle;
113 uint32_t ring_size;
114 uint32_t ring_wptr;
115};
116
117/* More registers may will be supported */
118enum psp_reg_prog_id {
119 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
120 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
121 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
122 PSP_REG_MMHUB_L1_TLB_CNTL = 25,
123 PSP_REG_LAST
124};
125
126struct psp_funcs {
127 int (*init_microcode)(struct psp_context *psp);
128 int (*wait_for_bootloader)(struct psp_context *psp);
129 int (*bootloader_load_kdb)(struct psp_context *psp);
130 int (*bootloader_load_spl)(struct psp_context *psp);
131 int (*bootloader_load_sysdrv)(struct psp_context *psp);
132 int (*bootloader_load_soc_drv)(struct psp_context *psp);
133 int (*bootloader_load_intf_drv)(struct psp_context *psp);
134 int (*bootloader_load_dbg_drv)(struct psp_context *psp);
135 int (*bootloader_load_ras_drv)(struct psp_context *psp);
136 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp);
137 int (*bootloader_load_spdm_drv)(struct psp_context *psp);
138 int (*bootloader_load_sos)(struct psp_context *psp);
139 int (*ring_create)(struct psp_context *psp,
140 enum psp_ring_type ring_type);
141 int (*ring_stop)(struct psp_context *psp,
142 enum psp_ring_type ring_type);
143 int (*ring_destroy)(struct psp_context *psp,
144 enum psp_ring_type ring_type);
145 bool (*smu_reload_quirk)(struct psp_context *psp);
146 int (*mode1_reset)(struct psp_context *psp);
147 int (*mem_training)(struct psp_context *psp, uint32_t ops);
148 uint32_t (*ring_get_wptr)(struct psp_context *psp);
149 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
150 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
151 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
152 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
153 int (*dump_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
154 int (*vbflash_stat)(struct psp_context *psp);
155 int (*fatal_error_recovery_quirk)(struct psp_context *psp);
156 bool (*get_ras_capability)(struct psp_context *psp);
157 bool (*is_aux_sos_load_required)(struct psp_context *psp);
158 bool (*is_reload_needed)(struct psp_context *psp);
159 int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val,
160 enum psp_reg_prog_id id);
161};
162
163struct ta_funcs {
164 int (*fn_ta_initialize)(struct psp_context *psp);
165 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
166 int (*fn_ta_terminate)(struct psp_context *psp);
167};
168
169#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
170struct psp_xgmi_node_info {
171 uint64_t node_id;
172 uint8_t num_hops;
173 uint8_t is_sharing_enabled;
174 enum ta_xgmi_assigned_sdma_engine sdma_engine;
175 uint8_t num_links;
176 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM];
177};
178
179struct psp_xgmi_topology_info {
180 uint32_t num_nodes;
181 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
182};
183
184struct psp_bin_desc {
185 uint32_t fw_version;
186 uint32_t feature_version;
187 uint32_t size_bytes;
188 uint8_t *start_addr;
189};
190
191struct ta_mem_context {
192 struct amdgpu_bo *shared_bo;
193 uint64_t shared_mc_addr;
194 void *shared_buf;
195 enum psp_shared_mem_size shared_mem_size;
196};
197
198struct ta_context {
199 bool initialized;
200 uint32_t session_id;
201 uint32_t resp_status;
202 struct ta_mem_context mem_context;
203 struct psp_bin_desc bin_desc;
204 enum psp_gfx_cmd_id ta_load_type;
205 enum ta_type_id ta_type;
206};
207
208struct ta_cp_context {
209 struct ta_context context;
210 struct mutex mutex;
211};
212
213struct psp_xgmi_context {
214 struct ta_context context;
215 struct psp_xgmi_topology_info top_info;
216 bool supports_extended_data;
217 uint8_t xgmi_ta_caps;
218};
219
220struct psp_ras_context {
221 struct ta_context context;
222 struct amdgpu_ras *ras;
223 struct mutex mutex;
224};
225
226#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
227#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
228#define GDDR6_MEM_TRAINING_OFFSET 0x8000
229/*Define the VRAM size that will be encroached by BIST training.*/
230#define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
231
232enum psp_memory_training_init_flag {
233 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
234 PSP_MEM_TRAIN_SUPPORT = 0x1,
235 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
236 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
237 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
238};
239
240enum psp_memory_training_ops {
241 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
242 PSP_MEM_TRAIN_SAVE = 0x2,
243 PSP_MEM_TRAIN_RESTORE = 0x4,
244 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
245 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
246 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
247};
248
249struct psp_memory_training_context {
250 /*training data size*/
251 u64 train_data_size;
252 /*
253 * sys_cache
254 * cpu virtual address
255 * system memory buffer that used to store the training data.
256 */
257 void *sys_cache;
258
259 /*vram offset of the p2c training data*/
260 u64 p2c_train_data_offset;
261
262 /*vram offset of the c2p training data*/
263 u64 c2p_train_data_offset;
264 struct amdgpu_bo *c2p_bo;
265
266 enum psp_memory_training_init_flag init;
267 u32 training_cnt;
268 bool enable_mem_training;
269};
270
271/** PSP runtime DB **/
272#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
273#define PSP_RUNTIME_DB_OFFSET 0x100000
274#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
275#define PSP_RUNTIME_DB_VER_1 0x0100
276#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
277
278enum psp_runtime_entry_type {
279 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
280 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
281 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
282 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
283 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
284 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
285 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
286};
287
288/* PSP runtime DB header */
289struct psp_runtime_data_header {
290 /* determine the existence of runtime db */
291 uint16_t cookie;
292 /* version of runtime db */
293 uint16_t version;
294};
295
296/* PSP runtime DB entry */
297struct psp_runtime_entry {
298 /* type of runtime db entry */
299 uint32_t entry_type;
300 /* offset of entry in bytes */
301 uint16_t offset;
302 /* size of entry in bytes */
303 uint16_t size;
304};
305
306/* PSP runtime DB directory */
307struct psp_runtime_data_directory {
308 /* number of valid entries */
309 uint16_t entry_count;
310 /* db entries*/
311 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
312};
313
314/* PSP runtime DB boot config feature bitmask */
315enum psp_runtime_boot_cfg_feature {
316 BOOT_CFG_FEATURE_GECC = 0x1,
317 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
318};
319
320/* PSP run time DB SCPM authentication defines */
321enum psp_runtime_scpm_authentication {
322 SCPM_DISABLE = 0x0,
323 SCPM_ENABLE = 0x1,
324 SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
325};
326
327/* PSP runtime DB boot config entry */
328struct psp_runtime_boot_cfg_entry {
329 uint32_t boot_cfg_bitmask;
330 uint32_t reserved;
331};
332
333/* PSP runtime DB SCPM entry */
334struct psp_runtime_scpm_entry {
335 enum psp_runtime_scpm_authentication scpm_status;
336};
337
338#if defined(CONFIG_DEBUG_FS)
339struct spirom_bo {
340 struct amdgpu_bo *bo;
341 uint64_t mc_addr;
342 void *cpu_addr;
343};
344#endif
345
346struct psp_context {
347 struct amdgpu_device *adev;
348 struct psp_ring km_ring;
349 struct psp_gfx_cmd_resp *cmd;
350
351 const struct psp_funcs *funcs;
352 const struct ta_funcs *ta_funcs;
353
354 /* firmware buffer */
355 struct amdgpu_bo *fw_pri_bo;
356 uint64_t fw_pri_mc_addr;
357 void *fw_pri_buf;
358
359 /* sos firmware */
360 const struct firmware *sos_fw;
361 struct psp_bin_desc sys;
362 struct psp_bin_desc sos;
363 struct psp_bin_desc toc;
364 struct psp_bin_desc kdb;
365 struct psp_bin_desc spl;
366 struct psp_bin_desc rl;
367 struct psp_bin_desc soc_drv;
368 struct psp_bin_desc intf_drv;
369 struct psp_bin_desc dbg_drv;
370 struct psp_bin_desc ras_drv;
371 struct psp_bin_desc ipkeymgr_drv;
372 struct psp_bin_desc spdm_drv;
373
374 /* tmr buffer */
375 struct amdgpu_bo *tmr_bo;
376 uint64_t tmr_mc_addr;
377
378 /* asd firmware */
379 const struct firmware *asd_fw;
380
381 /* toc firmware */
382 const struct firmware *toc_fw;
383
384 /* cap firmware */
385 const struct firmware *cap_fw;
386
387 /* fence buffer */
388 struct amdgpu_bo *fence_buf_bo;
389 uint64_t fence_buf_mc_addr;
390 void *fence_buf;
391
392 /* cmd buffer */
393 struct amdgpu_bo *cmd_buf_bo;
394 uint64_t cmd_buf_mc_addr;
395 struct psp_gfx_cmd_resp *cmd_buf_mem;
396
397 /* fence value associated with cmd buffer */
398 atomic_t fence_value;
399 /* flag to mark whether gfx fw autoload is supported or not */
400 bool autoload_supported;
401 /* flag to mark whether psp use runtime TMR or boottime TMR */
402 bool boot_time_tmr;
403 /* flag to mark whether df cstate management centralized to PMFW */
404 bool pmfw_centralized_cstate_management;
405
406 /* xgmi ta firmware and buffer */
407 const struct firmware *ta_fw;
408 uint32_t ta_fw_version;
409
410 uint32_t cap_fw_version;
411 uint32_t cap_feature_version;
412 uint32_t cap_ucode_size;
413
414 struct ta_context asd_context;
415 struct psp_xgmi_context xgmi_context;
416 struct psp_ras_context ras_context;
417 struct ta_cp_context hdcp_context;
418 struct ta_cp_context dtm_context;
419 struct ta_cp_context rap_context;
420 struct ta_cp_context securedisplay_context;
421 struct mutex mutex;
422 struct psp_memory_training_context mem_train_ctx;
423
424 uint32_t boot_cfg_bitmask;
425
426 /* firmware upgrades supported */
427 bool sup_pd_fw_up;
428 bool sup_ifwi_up;
429
430 char *vbflash_tmp_buf;
431 size_t vbflash_image_size;
432 bool vbflash_done;
433#if defined(CONFIG_DEBUG_FS)
434 struct spirom_bo *spirom_dump_trip;
435#endif
436};
437
438struct amdgpu_psp_funcs {
439 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
440 enum AMDGPU_UCODE_ID);
441};
442
443
444#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
445#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
446#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
447#define psp_init_microcode(psp) \
448 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
449#define psp_bootloader_load_kdb(psp) \
450 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
451#define psp_bootloader_load_spl(psp) \
452 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
453#define psp_bootloader_load_sysdrv(psp) \
454 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
455#define psp_bootloader_load_soc_drv(psp) \
456 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
457#define psp_bootloader_load_intf_drv(psp) \
458 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
459#define psp_bootloader_load_dbg_drv(psp) \
460 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
461#define psp_bootloader_load_ras_drv(psp) \
462 ((psp)->funcs->bootloader_load_ras_drv ? \
463 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
464#define psp_bootloader_load_ipkeymgr_drv(psp) \
465 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \
466 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0)
467#define psp_bootloader_load_spdm_drv(psp) \
468 ((psp)->funcs->bootloader_load_spdm_drv ? \
469 (psp)->funcs->bootloader_load_spdm_drv((psp)) : 0)
470#define psp_bootloader_load_sos(psp) \
471 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
472#define psp_smu_reload_quirk(psp) \
473 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
474#define psp_mode1_reset(psp) \
475 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
476#define psp_mem_training(psp, ops) \
477 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
478
479#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
480#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
481
482#define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
483 ((psp)->funcs->load_usbc_pd_fw ? \
484 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
485
486#define psp_read_usbc_pd_fw(psp, fw_ver) \
487 ((psp)->funcs->read_usbc_pd_fw ? \
488 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
489
490#define psp_update_spirom(psp, fw_pri_mc_addr) \
491 ((psp)->funcs->update_spirom ? \
492 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
493
494#define psp_dump_spirom(psp, fw_pri_mc_addr) \
495 ((psp)->funcs->dump_spirom ? \
496 (psp)->funcs->dump_spirom((psp), fw_pri_mc_addr) : -EINVAL)
497
498#define psp_vbflash_status(psp) \
499 ((psp)->funcs->vbflash_stat ? \
500 (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
501
502#define psp_fatal_error_recovery_quirk(psp) \
503 ((psp)->funcs->fatal_error_recovery_quirk ? \
504 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)
505
506#define psp_is_aux_sos_load_required(psp) \
507 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0)
508
509#define psp_reg_program_no_ring(psp, val, id) \
510 ((psp)->funcs->reg_program_no_ring ? \
511 (psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL)
512
513extern const struct amd_ip_funcs psp_ip_funcs;
514
515extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
516extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
517extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
518extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
519extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
520extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
521extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
522extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
523
524extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
525 uint32_t field_val, uint32_t mask, bool check_changed);
526extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
527 uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
528
529int psp_execute_ip_fw_load(struct psp_context *psp,
530 struct amdgpu_firmware_info *ucode);
531
532int psp_gpu_reset(struct amdgpu_device *adev);
533
534int psp_ta_init_shared_buf(struct psp_context *psp,
535 struct ta_mem_context *mem_ctx);
536void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
537int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
538int psp_ta_load(struct psp_context *psp, struct ta_context *context);
539int psp_ta_invoke(struct psp_context *psp,
540 uint32_t ta_cmd_id,
541 struct ta_context *context);
542
543int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
544int psp_xgmi_terminate(struct psp_context *psp);
545int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
546int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
547int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
548int psp_xgmi_get_topology_info(struct psp_context *psp,
549 int number_devices,
550 struct psp_xgmi_topology_info *topology,
551 bool get_extended_data);
552int psp_xgmi_set_topology_info(struct psp_context *psp,
553 int number_devices,
554 struct psp_xgmi_topology_info *topology);
555int psp_ras_initialize(struct psp_context *psp);
556int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
557int psp_ras_enable_features(struct psp_context *psp,
558 union ta_ras_cmd_input *info, bool enable);
559int psp_ras_trigger_error(struct psp_context *psp,
560 struct ta_ras_trigger_error_input *info, uint32_t instance_mask);
561int psp_ras_terminate(struct psp_context *psp);
562int psp_ras_query_address(struct psp_context *psp,
563 struct ta_ras_query_address_input *addr_in,
564 struct ta_ras_query_address_output *addr_out);
565
566int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
567int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
568int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
569int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
570
571int psp_rlc_autoload_start(struct psp_context *psp);
572
573int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
574 uint32_t value);
575int psp_ring_cmd_submit(struct psp_context *psp,
576 uint64_t cmd_buf_mc_addr,
577 uint64_t fence_mc_addr,
578 int index);
579int psp_init_asd_microcode(struct psp_context *psp,
580 const char *chip_name);
581int psp_init_toc_microcode(struct psp_context *psp,
582 const char *chip_name);
583int psp_init_sos_microcode(struct psp_context *psp,
584 const char *chip_name);
585int psp_init_ta_microcode(struct psp_context *psp,
586 const char *chip_name);
587int psp_init_cap_microcode(struct psp_context *psp,
588 const char *chip_name);
589int psp_get_fw_attestation_records_addr(struct psp_context *psp,
590 uint64_t *output_ptr);
591
592int psp_load_fw_list(struct psp_context *psp,
593 struct amdgpu_firmware_info **ucode_list, int ucode_count);
594void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
595
596int psp_spatial_partition(struct psp_context *psp, int mode);
597int psp_memory_partition(struct psp_context *psp, int mode);
598
599int is_psp_fw_valid(struct psp_bin_desc bin);
600
601int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
602bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
603
604int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id,
605 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable);
606bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev);
607int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val,
608 enum psp_reg_prog_id id);
609void amdgpu_psp_debugfs_init(struct amdgpu_device *adev);
610
611
612#endif
613

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source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h