1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_DPM_H__
24#define __AMDGPU_DPM_H__
25
26/* Argument for PPSMC_MSG_GpuChangeState */
27enum gfx_change_state {
28 sGpuChangeState_D0Entry = 1,
29 sGpuChangeState_D3Entry,
30};
31
32enum amdgpu_int_thermal_type {
33 THERMAL_TYPE_NONE,
34 THERMAL_TYPE_EXTERNAL,
35 THERMAL_TYPE_EXTERNAL_GPIO,
36 THERMAL_TYPE_RV6XX,
37 THERMAL_TYPE_RV770,
38 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
39 THERMAL_TYPE_EVERGREEN,
40 THERMAL_TYPE_SUMO,
41 THERMAL_TYPE_NI,
42 THERMAL_TYPE_SI,
43 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
44 THERMAL_TYPE_CI,
45 THERMAL_TYPE_KV,
46};
47
48enum amdgpu_runpm_mode {
49 AMDGPU_RUNPM_NONE,
50 AMDGPU_RUNPM_PX,
51 AMDGPU_RUNPM_BOCO,
52 AMDGPU_RUNPM_BACO,
53};
54
55struct amdgpu_ps {
56 u32 caps; /* vbios flags */
57 u32 class; /* vbios flags */
58 u32 class2; /* vbios flags */
59 /* UVD clocks */
60 u32 vclk;
61 u32 dclk;
62 /* VCE clocks */
63 u32 evclk;
64 u32 ecclk;
65 bool vce_active;
66 enum amd_vce_level vce_level;
67 /* asic priv */
68 void *ps_priv;
69};
70
71struct amdgpu_dpm_thermal {
72 /* thermal interrupt work */
73 struct work_struct work;
74 /* low temperature threshold */
75 int min_temp;
76 /* high temperature threshold */
77 int max_temp;
78 /* edge max emergency(shutdown) temp */
79 int max_edge_emergency_temp;
80 /* hotspot low temperature threshold */
81 int min_hotspot_temp;
82 /* hotspot high temperature critical threshold */
83 int max_hotspot_crit_temp;
84 /* hotspot max emergency(shutdown) temp */
85 int max_hotspot_emergency_temp;
86 /* memory low temperature threshold */
87 int min_mem_temp;
88 /* memory high temperature critical threshold */
89 int max_mem_crit_temp;
90 /* memory max emergency(shutdown) temp */
91 int max_mem_emergency_temp;
92 /* SWCTF threshold */
93 int sw_ctf_threshold;
94 /* was last interrupt low to high or high to low */
95 bool high_to_low;
96 /* interrupt source */
97 struct amdgpu_irq_src irq;
98};
99
100struct amdgpu_clock_and_voltage_limits {
101 u32 sclk;
102 u32 mclk;
103 u16 vddc;
104 u16 vddci;
105};
106
107struct amdgpu_clock_array {
108 u32 count;
109 u32 *values;
110};
111
112struct amdgpu_clock_voltage_dependency_entry {
113 u32 clk;
114 u16 v;
115};
116
117struct amdgpu_clock_voltage_dependency_table {
118 u32 count;
119 struct amdgpu_clock_voltage_dependency_entry *entries;
120};
121
122union amdgpu_cac_leakage_entry {
123 struct {
124 u16 vddc;
125 u32 leakage;
126 };
127 struct {
128 u16 vddc1;
129 u16 vddc2;
130 u16 vddc3;
131 };
132};
133
134struct amdgpu_cac_leakage_table {
135 u32 count;
136 union amdgpu_cac_leakage_entry *entries;
137};
138
139struct amdgpu_phase_shedding_limits_entry {
140 u16 voltage;
141 u32 sclk;
142 u32 mclk;
143};
144
145struct amdgpu_phase_shedding_limits_table {
146 u32 count;
147 struct amdgpu_phase_shedding_limits_entry *entries;
148};
149
150struct amdgpu_uvd_clock_voltage_dependency_entry {
151 u32 vclk;
152 u32 dclk;
153 u16 v;
154};
155
156struct amdgpu_uvd_clock_voltage_dependency_table {
157 u8 count;
158 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
159};
160
161struct amdgpu_vce_clock_voltage_dependency_entry {
162 u32 ecclk;
163 u32 evclk;
164 u16 v;
165};
166
167struct amdgpu_vce_clock_voltage_dependency_table {
168 u8 count;
169 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
170};
171
172struct amdgpu_ppm_table {
173 u8 ppm_design;
174 u16 cpu_core_number;
175 u32 platform_tdp;
176 u32 small_ac_platform_tdp;
177 u32 platform_tdc;
178 u32 small_ac_platform_tdc;
179 u32 apu_tdp;
180 u32 dgpu_tdp;
181 u32 dgpu_ulv_power;
182 u32 tj_max;
183};
184
185struct amdgpu_cac_tdp_table {
186 u16 tdp;
187 u16 configurable_tdp;
188 u16 tdc;
189 u16 battery_power_limit;
190 u16 small_power_limit;
191 u16 low_cac_leakage;
192 u16 high_cac_leakage;
193 u16 maximum_power_delivery_limit;
194};
195
196struct amdgpu_dpm_dynamic_state {
197 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
198 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
199 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
200 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
201 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
202 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
203 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
204 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
205 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
206 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
207 struct amdgpu_clock_array valid_sclk_values;
208 struct amdgpu_clock_array valid_mclk_values;
209 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
210 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
211 u32 mclk_sclk_ratio;
212 u32 sclk_mclk_delta;
213 u16 vddc_vddci_delta;
214 u16 min_vddc_for_pcie_gen2;
215 struct amdgpu_cac_leakage_table cac_leakage_table;
216 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
217 struct amdgpu_ppm_table *ppm_table;
218 struct amdgpu_cac_tdp_table *cac_tdp_table;
219};
220
221struct amdgpu_dpm_fan {
222 u16 t_min;
223 u16 t_med;
224 u16 t_high;
225 u16 pwm_min;
226 u16 pwm_med;
227 u16 pwm_high;
228 u8 t_hyst;
229 u32 cycle_delay;
230 u16 t_max;
231 u8 control_mode;
232 u16 default_max_fan_pwm;
233 u16 default_fan_output_sensitivity;
234 u16 fan_output_sensitivity;
235 bool ucode_fan_control;
236};
237
238struct amdgpu_dpm {
239 struct amdgpu_ps *ps;
240 /* number of valid power states */
241 int num_ps;
242 /* current power state that is active */
243 struct amdgpu_ps *current_ps;
244 /* requested power state */
245 struct amdgpu_ps *requested_ps;
246 /* boot up power state */
247 struct amdgpu_ps *boot_ps;
248 /* default uvd power state */
249 struct amdgpu_ps *uvd_ps;
250 /* vce requirements */
251 u32 num_of_vce_states;
252 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
253 enum amd_vce_level vce_level;
254 enum amd_pm_state_type state;
255 enum amd_pm_state_type user_state;
256 enum amd_pm_state_type last_state;
257 enum amd_pm_state_type last_user_state;
258 u32 platform_caps;
259 u32 voltage_response_time;
260 u32 backbias_response_time;
261 void *priv;
262 u32 new_active_crtcs;
263 int new_active_crtc_count;
264 u32 current_active_crtcs;
265 int current_active_crtc_count;
266 struct amdgpu_dpm_dynamic_state dyn_state;
267 struct amdgpu_dpm_fan fan;
268 u32 tdp_limit;
269 u32 near_tdp_limit;
270 u32 near_tdp_limit_adjusted;
271 u32 sq_ramping_threshold;
272 u32 cac_leakage;
273 u16 tdp_od_limit;
274 u32 tdp_adjustment;
275 u16 load_line_slope;
276 bool power_control;
277 /* special states active */
278 bool thermal_active;
279 bool uvd_active;
280 bool vce_active;
281 /* thermal handling */
282 struct amdgpu_dpm_thermal thermal;
283 /* forced levels */
284 enum amd_dpm_forced_level forced_level;
285};
286
287enum ip_power_state {
288 POWER_STATE_UNKNOWN,
289 POWER_STATE_ON,
290 POWER_STATE_OFF,
291};
292
293/* Used to mask smu debug modes */
294#define SMU_DEBUG_HALT_ON_ERROR 0x1
295
296#define MAX_SMU_I2C_BUSES 2
297
298struct amdgpu_smu_i2c_bus {
299 struct i2c_adapter adapter;
300 struct amdgpu_device *adev;
301 int port;
302 struct mutex mutex;
303};
304
305struct config_table_setting
306{
307 uint16_t gfxclk_average_tau;
308 uint16_t socclk_average_tau;
309 uint16_t uclk_average_tau;
310 uint16_t gfx_activity_average_tau;
311 uint16_t mem_activity_average_tau;
312 uint16_t socket_power_average_tau;
313 uint16_t apu_socket_power_average_tau;
314 uint16_t fclk_average_tau;
315};
316
317#define OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE BIT(0)
318#define OD_OPS_SUPPORT_FAN_CURVE_SET BIT(1)
319#define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE BIT(2)
320#define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET BIT(3)
321#define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE BIT(4)
322#define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET BIT(5)
323#define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE BIT(6)
324#define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET BIT(7)
325#define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE BIT(8)
326#define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET BIT(9)
327
328struct amdgpu_pm {
329 struct mutex mutex;
330 u32 current_sclk;
331 u32 current_mclk;
332 u32 default_sclk;
333 u32 default_mclk;
334 struct amdgpu_i2c_chan *i2c_bus;
335 bool bus_locked;
336 /* internal thermal controller on rv6xx+ */
337 enum amdgpu_int_thermal_type int_thermal_type;
338 struct device *int_hwmon_dev;
339 /* fan control parameters */
340 bool no_fan;
341 u8 fan_pulses_per_revolution;
342 u8 fan_min_rpm;
343 u8 fan_max_rpm;
344 /* dpm */
345 bool dpm_enabled;
346 bool sysfs_initialized;
347 struct amdgpu_dpm dpm;
348 const struct firmware *fw; /* SMC firmware */
349 uint32_t fw_version;
350 uint32_t pcie_gen_mask;
351 uint32_t pcie_mlw_mask;
352 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
353 uint32_t smu_prv_buffer_size;
354 struct amdgpu_bo *smu_prv_buffer;
355 bool ac_power;
356 /* powerplay feature */
357 uint32_t pp_feature;
358
359 /* Used for I2C access to various EEPROMs on relevant ASICs */
360 struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES];
361 struct i2c_adapter *ras_eeprom_i2c_bus;
362 struct i2c_adapter *fru_eeprom_i2c_bus;
363 struct list_head pm_attr_list;
364
365 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM];
366
367 /*
368 * 0 = disabled (default), otherwise enable corresponding debug mode
369 */
370 uint32_t smu_debug_mask;
371
372 bool pp_force_state_enabled;
373
374 struct mutex stable_pstate_ctx_lock;
375 struct amdgpu_ctx *stable_pstate_ctx;
376
377 struct config_table_setting config_table;
378 /* runtime mode */
379 enum amdgpu_runpm_mode rpm_mode;
380
381 struct list_head od_kobj_list;
382 uint32_t od_feature_mask;
383};
384
385int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
386 void *data, uint32_t *size);
387
388int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit);
389int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit);
390
391int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
392 uint32_t block_type, bool gate);
393
394extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
395
396extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
397
398int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
399 uint32_t pstate);
400
401int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
402 enum PP_SMC_POWER_PROFILE type,
403 bool en);
404
405int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
406
407int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
408int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev);
409
410bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev);
411
412bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev);
413int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);
414
415int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
416 enum pp_mp1_state mp1_state);
417
418int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en);
419
420int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
421
422int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
423
424int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
425
426int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
427 uint32_t cstate);
428
429int amdgpu_dpm_get_xgmi_plpd_mode(struct amdgpu_device *adev,
430 char **mode);
431
432int amdgpu_dpm_set_xgmi_plpd_mode(struct amdgpu_device *adev, int mode);
433
434int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev);
435
436int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,
437 uint32_t msg_id);
438
439int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,
440 bool acquire);
441
442void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
443
444void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
445void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
446void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
447void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
448void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);
449int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
450int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);
451int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
452int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size);
453int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev);
454int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
455 enum pp_clock_type type,
456 uint32_t *min,
457 uint32_t *max);
458int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,
459 enum pp_clock_type type,
460 uint32_t min,
461 uint32_t max);
462int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
463int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
464 uint64_t event_arg);
465int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value);
466int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value);
467int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value);
468int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
469uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev);
470void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
471 enum gfx_change_state state);
472int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev,
473 void *umc_ecc);
474struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev,
475 uint32_t idx);
476void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state);
477void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
478 enum amd_pm_state_type state);
479enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev);
480int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
481 enum amd_dpm_forced_level level);
482int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev,
483 struct pp_states_info *states);
484int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev,
485 enum amd_pp_task task_id,
486 enum amd_pm_state_type *user_state);
487int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table);
488int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev,
489 uint32_t type,
490 long *input,
491 uint32_t size);
492int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev,
493 uint32_t type,
494 long *input,
495 uint32_t size);
496int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev,
497 enum pp_clock_type type,
498 char *buf);
499int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
500 enum pp_clock_type type,
501 char *buf,
502 int *offset);
503int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
504 uint64_t ppfeature_masks);
505int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf);
506int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev,
507 enum pp_clock_type type,
508 uint32_t mask);
509int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev);
510int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value);
511int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev);
512int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value);
513int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,
514 char *buf);
515int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,
516 long *input, uint32_t size);
517int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table);
518
519/**
520 * @get_pm_metrics: Get one snapshot of power management metrics from PMFW. The
521 * sample is copied to pm_metrics buffer. It's expected to be allocated by the
522 * caller and size of the allocated buffer is passed. Max size expected for a
523 * metrics sample is 4096 bytes.
524 *
525 * Return: Actual size of the metrics sample
526 */
527ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics,
528 size_t size);
529
530int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,
531 uint32_t *fan_mode);
532int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,
533 uint32_t speed);
534int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev,
535 uint32_t *speed);
536int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev,
537 uint32_t *speed);
538int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev,
539 uint32_t speed);
540int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev,
541 uint32_t mode);
542int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev,
543 uint32_t *limit,
544 enum pp_power_limit_level pp_limit_level,
545 enum pp_power_type power_type);
546int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev,
547 uint32_t limit);
548int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev);
549int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
550 struct seq_file *m);
551int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
552 void **addr,
553 size_t *size);
554int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev);
555int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
556 const char *buf,
557 size_t size);
558int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev);
559void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev);
560int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev,
561 const struct amd_pp_display_configuration *input);
562int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev,
563 enum amd_pp_clock_type type,
564 struct amd_pp_clocks *clocks);
565int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev,
566 struct amd_pp_simple_clock_info *clocks);
567int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev,
568 enum amd_pp_clock_type type,
569 struct pp_clock_levels_with_latency *clocks);
570int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev,
571 enum amd_pp_clock_type type,
572 struct pp_clock_levels_with_voltage *clocks);
573int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev,
574 void *clock_ranges);
575int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev,
576 struct pp_display_clock_request *clock);
577int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev,
578 struct amd_pp_clock_info *clocks);
579void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev);
580int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev,
581 uint32_t count);
582int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev,
583 uint32_t clock);
584void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev,
585 uint32_t clock);
586void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev,
587 uint32_t clock);
588int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev,
589 bool disable_memory_clock_switch);
590int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev,
591 struct pp_smu_nv_clock_table *max_clocks);
592enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
593 unsigned int *clock_values_in_khz,
594 unsigned int *num_states);
595int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev,
596 struct dpm_clocks *clock_table);
597#endif
598

source code of linux/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h