1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef AMDGPU_DOORBELL_H
25#define AMDGPU_DOORBELL_H
26
27/*
28 * GPU doorbell structures, functions & helpers
29 */
30struct amdgpu_doorbell {
31 /* doorbell mmio */
32 resource_size_t base;
33 resource_size_t size;
34 u32 __iomem *ptr;
35
36 /* Number of doorbells reserved for amdgpu kernel driver */
37 u32 num_kernel_doorbells;
38};
39
40/* Reserved doorbells for amdgpu (including multimedia).
41 * KFD can use all the rest in the 2M doorbell bar.
42 * For asic before vega10, doorbell is 32-bit, so the
43 * index/offset is in dword. For vega10 and after, doorbell
44 * can be 64-bit, so the index defined is in qword.
45 */
46struct amdgpu_doorbell_index {
47 uint32_t kiq;
48 uint32_t mec_ring0;
49 uint32_t mec_ring1;
50 uint32_t mec_ring2;
51 uint32_t mec_ring3;
52 uint32_t mec_ring4;
53 uint32_t mec_ring5;
54 uint32_t mec_ring6;
55 uint32_t mec_ring7;
56 uint32_t userqueue_start;
57 uint32_t userqueue_end;
58 uint32_t gfx_ring0;
59 uint32_t gfx_ring1;
60 uint32_t gfx_userqueue_start;
61 uint32_t gfx_userqueue_end;
62 uint32_t sdma_engine[8];
63 uint32_t mes_ring0;
64 uint32_t mes_ring1;
65 uint32_t ih;
66 union {
67 struct {
68 uint32_t vcn_ring0_1;
69 uint32_t vcn_ring2_3;
70 uint32_t vcn_ring4_5;
71 uint32_t vcn_ring6_7;
72 } vcn;
73 struct {
74 uint32_t uvd_ring0_1;
75 uint32_t uvd_ring2_3;
76 uint32_t uvd_ring4_5;
77 uint32_t uvd_ring6_7;
78 uint32_t vce_ring0_1;
79 uint32_t vce_ring2_3;
80 uint32_t vce_ring4_5;
81 uint32_t vce_ring6_7;
82 } uvd_vce;
83 };
84 uint32_t first_non_cp;
85 uint32_t last_non_cp;
86 uint32_t max_assignment;
87 /* Per engine SDMA doorbell size in dword */
88 uint32_t sdma_doorbell_range;
89};
90
91typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
92{
93 AMDGPU_DOORBELL_KIQ = 0x000,
94 AMDGPU_DOORBELL_HIQ = 0x001,
95 AMDGPU_DOORBELL_DIQ = 0x002,
96 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
97 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
98 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
99 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
100 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
101 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
102 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
103 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
104 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
105 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
106 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
107 AMDGPU_DOORBELL_IH = 0x1E8,
108 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
109 AMDGPU_DOORBELL_INVALID = 0xFFFF
110} AMDGPU_DOORBELL_ASSIGNMENT;
111
112typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
113{
114 /* Compute + GFX: 0~255 */
115 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
116 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
117 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
118 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
119 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
120 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
121 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
122 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
123 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
124 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
125 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
126 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
127 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
128 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
129 /* SDMA:256~335*/
130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
131 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A,
132 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
133 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E,
134 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128,
135 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
136 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C,
137 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146,
138 /* IH: 376~391 */
139 AMDGPU_VEGA20_DOORBELL_IH = 0x178,
140 /* MMSCH: 392~407
141 * overlap the doorbell assignment with VCN as they are mutually exclusive
142 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
143 */
144 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */
145 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
146 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
147 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
148
149 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */
150 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D,
151 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E,
152 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F,
153
154 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
155 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
156 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
157 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
158
159 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
160 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
161 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
162 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
163
164 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
165 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
166
167 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
168 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
169} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
170
171typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
172{
173 /* Compute + GFX: 0~255 */
174 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000,
175 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001,
176 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002,
177 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003,
178 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004,
179 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005,
180 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006,
181 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007,
182 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008,
183 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009,
184 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A,
185 AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B,
186 AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C,
187 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D,
188 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A,
189 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B,
190 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C,
191 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D,
192 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF,
193
194 /* SDMA:256~335*/
195 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100,
196 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A,
197 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114,
198 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E,
199 /* IH: 376~391 */
200 AMDGPU_NAVI10_DOORBELL_IH = 0x178,
201 /* MMSCH: 392~407
202 * overlap the doorbell assignment with VCN as they are mutually exclusive
203 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
204 */
205 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
206 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189,
207 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A,
208 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B,
209
210 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C,
211 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D,
212 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E,
213 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F,
214
215 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
216 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f,
217
218 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F,
219 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF
220} AMDGPU_NAVI10_DOORBELL_ASSIGNMENT;
221
222/*
223 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
224 */
225typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
226{
227 /*
228 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
229 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
230 * Compute related doorbells are allocated from 0x00 to 0x8a
231 */
232
233
234 /* kernel scheduling */
235 AMDGPU_DOORBELL64_KIQ = 0x00,
236
237 /* HSA interface queue and debug queue */
238 AMDGPU_DOORBELL64_HIQ = 0x01,
239 AMDGPU_DOORBELL64_DIQ = 0x02,
240
241 /* Compute engines */
242 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
243 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
244 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
245 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
246 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
247 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
248 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
249 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
250
251 /* User queue doorbell range (128 doorbells) */
252 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
253 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
254
255 /* Graphics engine */
256 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
257
258 /*
259 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
260 * Graphics voltage island aperture 1
261 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
262 */
263
264 /* For vega10 sriov, the sdma doorbell must be fixed as follow
265 * to keep the same setting with host driver, or it will
266 * happen conflicts
267 */
268 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
269 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
270 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
271 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
272
273 /* Interrupt handler */
274 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
275 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
276 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
277
278 /* VCN engine use 32 bits doorbell */
279 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
280 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
281 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
282 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
283
284 /* overlap the doorbell assignment with VCN as they are mutually exclusive
285 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
286 */
287 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
288 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
289 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
290 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
291
292 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
293 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
294 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
295 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
296
297 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0,
298 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
299
300 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
301 AMDGPU_DOORBELL64_INVALID = 0xFFFF
302} AMDGPU_DOORBELL64_ASSIGNMENT;
303
304u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
305void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
306u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
307void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
308
309#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
310#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
311#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
312#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
313
314#endif
315

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h