1 | /* |
2 | * Copyright 2022 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #ifndef __JPEG_V4_0_3_H__ |
25 | #define __JPEG_V4_0_3_H__ |
26 | |
27 | #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff |
28 | #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d |
29 | #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e |
30 | #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f |
31 | #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab |
32 | #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac |
33 | #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4 |
34 | #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6 |
35 | #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6 |
36 | #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7 |
37 | #define regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082 |
38 | #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x42d4 |
39 | #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x42d5 |
40 | #define regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085 |
41 | #define regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084 |
42 | #define regUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089 |
43 | #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x4043 |
44 | #define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET 0x4094 |
45 | #define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET 0x1bffe |
46 | |
47 | #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 |
48 | |
49 | extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block; |
50 | |
51 | void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, |
52 | struct amdgpu_job *job, |
53 | struct amdgpu_ib *ib, |
54 | uint32_t flags); |
55 | void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, |
56 | unsigned int flags); |
57 | void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, |
58 | unsigned int vmid, uint64_t pd_addr); |
59 | void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count); |
60 | void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring); |
61 | void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring); |
62 | void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); |
63 | void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, |
64 | uint32_t val, uint32_t mask); |
65 | |
66 | #endif /* __JPEG_V4_0_3_H__ */ |
67 | |