1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include "amdgpu.h" |
24 | #include "amdgpu_ras.h" |
25 | #include "mmhub_v1_7.h" |
26 | |
27 | #include "mmhub/mmhub_1_7_offset.h" |
28 | #include "mmhub/mmhub_1_7_sh_mask.h" |
29 | #include "vega10_enum.h" |
30 | |
31 | #include "soc15_common.h" |
32 | #include "soc15.h" |
33 | |
34 | #define regVM_L2_CNTL3_DEFAULT 0x80100007 |
35 | #define regVM_L2_CNTL4_DEFAULT 0x000000c1 |
36 | |
37 | static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev) |
38 | { |
39 | u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE); |
40 | u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP); |
41 | |
42 | base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; |
43 | base <<= 24; |
44 | |
45 | top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; |
46 | top <<= 24; |
47 | |
48 | adev->gmc.fb_start = base; |
49 | adev->gmc.fb_end = top; |
50 | |
51 | return base; |
52 | } |
53 | |
54 | static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, |
55 | uint64_t page_table_base) |
56 | { |
57 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
58 | |
59 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, |
60 | hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base)); |
61 | |
62 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, |
63 | hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base)); |
64 | } |
65 | |
66 | static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev) |
67 | { |
68 | uint64_t pt_base; |
69 | |
70 | if (adev->gmc.pdb0_bo) |
71 | pt_base = amdgpu_gmc_pd_addr(bo: adev->gmc.pdb0_bo); |
72 | else |
73 | pt_base = amdgpu_gmc_pd_addr(bo: adev->gart.bo); |
74 | |
75 | mmhub_v1_7_setup_vm_pt_regs(adev, vmid: 0, page_table_base: pt_base); |
76 | |
77 | /* If use GART for FB translation, vmid0 page table covers both |
78 | * vram and system memory (gart) |
79 | */ |
80 | if (adev->gmc.pdb0_bo) { |
81 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, |
82 | (u32)(adev->gmc.fb_start >> 12)); |
83 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, |
84 | (u32)(adev->gmc.fb_start >> 44)); |
85 | |
86 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, |
87 | (u32)(adev->gmc.gart_end >> 12)); |
88 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, |
89 | (u32)(adev->gmc.gart_end >> 44)); |
90 | |
91 | } else { |
92 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, |
93 | (u32)(adev->gmc.gart_start >> 12)); |
94 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, |
95 | (u32)(adev->gmc.gart_start >> 44)); |
96 | |
97 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, |
98 | (u32)(adev->gmc.gart_end >> 12)); |
99 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, |
100 | (u32)(adev->gmc.gart_end >> 44)); |
101 | } |
102 | } |
103 | |
104 | static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev) |
105 | { |
106 | uint64_t value; |
107 | uint32_t tmp; |
108 | |
109 | /* Program the AGP BAR */ |
110 | WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0); |
111 | WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); |
112 | WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); |
113 | |
114 | if (amdgpu_sriov_vf(adev)) |
115 | return; |
116 | |
117 | /* Program the system aperture low logical page number. */ |
118 | WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, |
119 | min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); |
120 | |
121 | WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
122 | max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); |
123 | |
124 | /* In the case squeezing vram into GART aperture, we don't use |
125 | * FB aperture and AGP aperture. Disable them. |
126 | */ |
127 | if (adev->gmc.pdb0_bo) { |
128 | WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF); |
129 | WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0); |
130 | WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0); |
131 | WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); |
132 | WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF); |
133 | WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0); |
134 | } |
135 | |
136 | /* Set default page address. */ |
137 | value = amdgpu_gmc_vram_mc2pa(adev, mc_addr: adev->mem_scratch.gpu_addr); |
138 | WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, |
139 | (u32)(value >> 12)); |
140 | WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, |
141 | (u32)(value >> 44)); |
142 | |
143 | /* Program "protection fault". */ |
144 | WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, |
145 | (u32)(adev->dummy_page_addr >> 12)); |
146 | WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, |
147 | (u32)((u64)adev->dummy_page_addr >> 44)); |
148 | |
149 | tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2); |
150 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, |
151 | ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); |
152 | WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp); |
153 | } |
154 | |
155 | static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev) |
156 | { |
157 | uint32_t tmp; |
158 | |
159 | /* Setup TLB control */ |
160 | tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); |
161 | |
162 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); |
163 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); |
164 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, |
165 | ENABLE_ADVANCED_DRIVER_MODEL, 1); |
166 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, |
167 | SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); |
168 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, |
169 | MTYPE, MTYPE_UC);/* XXX for emulation. */ |
170 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); |
171 | |
172 | WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); |
173 | } |
174 | |
175 | static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev) |
176 | { |
177 | uint32_t tmp; |
178 | |
179 | if (amdgpu_sriov_vf(adev)) |
180 | return; |
181 | |
182 | /* Setup L2 cache */ |
183 | tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL); |
184 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); |
185 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); |
186 | /* XXX for emulation, Refer to closed source code.*/ |
187 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, |
188 | 0); |
189 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); |
190 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); |
191 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); |
192 | WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp); |
193 | |
194 | tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2); |
195 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); |
196 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); |
197 | WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp); |
198 | |
199 | tmp = regVM_L2_CNTL3_DEFAULT; |
200 | if (adev->gmc.translate_further) { |
201 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); |
202 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, |
203 | L2_CACHE_BIGK_FRAGMENT_SIZE, 9); |
204 | } else { |
205 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); |
206 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, |
207 | L2_CACHE_BIGK_FRAGMENT_SIZE, 6); |
208 | } |
209 | WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp); |
210 | |
211 | tmp = regVM_L2_CNTL4_DEFAULT; |
212 | if (adev->gmc.xgmi.connected_to_cpu) { |
213 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, |
214 | VMC_TAP_PDE_REQUEST_PHYSICAL, 1); |
215 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, |
216 | VMC_TAP_PTE_REQUEST_PHYSICAL, 1); |
217 | } else { |
218 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, |
219 | VMC_TAP_PDE_REQUEST_PHYSICAL, 0); |
220 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, |
221 | VMC_TAP_PTE_REQUEST_PHYSICAL, 0); |
222 | } |
223 | WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp); |
224 | } |
225 | |
226 | static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev) |
227 | { |
228 | uint32_t tmp; |
229 | |
230 | tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL); |
231 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); |
232 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, |
233 | adev->gmc.vmid0_page_table_depth); |
234 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, |
235 | adev->gmc.vmid0_page_table_block_size); |
236 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, |
237 | RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); |
238 | WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp); |
239 | } |
240 | |
241 | static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev) |
242 | { |
243 | if (amdgpu_sriov_vf(adev)) |
244 | return; |
245 | |
246 | WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, |
247 | 0XFFFFFFFF); |
248 | WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, |
249 | 0x0000000F); |
250 | |
251 | WREG32_SOC15(MMHUB, 0, |
252 | regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); |
253 | WREG32_SOC15(MMHUB, 0, |
254 | regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); |
255 | |
256 | WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, |
257 | 0); |
258 | WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, |
259 | 0); |
260 | } |
261 | |
262 | static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev) |
263 | { |
264 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
265 | unsigned num_level, block_size; |
266 | uint32_t tmp; |
267 | int i; |
268 | |
269 | num_level = adev->vm_manager.num_level; |
270 | block_size = adev->vm_manager.block_size; |
271 | if (adev->gmc.translate_further) |
272 | num_level -= 1; |
273 | else |
274 | block_size -= 9; |
275 | |
276 | for (i = 0; i <= 14; i++) { |
277 | tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i * hub->ctx_distance); |
278 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); |
279 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, |
280 | num_level); |
281 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
282 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
283 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
284 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, |
285 | 1); |
286 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
287 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
288 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
289 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
290 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
291 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
292 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
293 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
294 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
295 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
296 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
297 | PAGE_TABLE_BLOCK_SIZE, |
298 | block_size); |
299 | /* On Aldebaran, XNACK can be enabled in the SQ per-process. |
300 | * Retry faults need to be enabled for that to work. |
301 | */ |
302 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
303 | RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, |
304 | 1); |
305 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, |
306 | i * hub->ctx_distance, tmp); |
307 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, |
308 | i * hub->ctx_addr_distance, 0); |
309 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, |
310 | i * hub->ctx_addr_distance, 0); |
311 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, |
312 | i * hub->ctx_addr_distance, |
313 | lower_32_bits(adev->vm_manager.max_pfn - 1)); |
314 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, |
315 | i * hub->ctx_addr_distance, |
316 | upper_32_bits(adev->vm_manager.max_pfn - 1)); |
317 | } |
318 | } |
319 | |
320 | static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev) |
321 | { |
322 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
323 | unsigned i; |
324 | |
325 | for (i = 0; i < 18; ++i) { |
326 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, |
327 | i * hub->eng_addr_distance, 0xffffffff); |
328 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, |
329 | i * hub->eng_addr_distance, 0x1f); |
330 | } |
331 | } |
332 | |
333 | static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev) |
334 | { |
335 | /* GART Enable. */ |
336 | mmhub_v1_7_init_gart_aperture_regs(adev); |
337 | mmhub_v1_7_init_system_aperture_regs(adev); |
338 | mmhub_v1_7_init_tlb_regs(adev); |
339 | mmhub_v1_7_init_cache_regs(adev); |
340 | |
341 | mmhub_v1_7_enable_system_domain(adev); |
342 | mmhub_v1_7_disable_identity_aperture(adev); |
343 | mmhub_v1_7_setup_vmid_config(adev); |
344 | mmhub_v1_7_program_invalidation(adev); |
345 | |
346 | return 0; |
347 | } |
348 | |
349 | static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev) |
350 | { |
351 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
352 | u32 tmp; |
353 | u32 i; |
354 | |
355 | /* Disable all tables */ |
356 | for (i = 0; i < 16; i++) |
357 | WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL, |
358 | i * hub->ctx_distance, 0); |
359 | |
360 | /* Setup TLB control */ |
361 | tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); |
362 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); |
363 | tmp = REG_SET_FIELD(tmp, |
364 | MC_VM_MX_L1_TLB_CNTL, |
365 | ENABLE_ADVANCED_DRIVER_MODEL, |
366 | 0); |
367 | WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); |
368 | |
369 | if (!amdgpu_sriov_vf(adev)) { |
370 | /* Setup L2 cache */ |
371 | tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL); |
372 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); |
373 | WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp); |
374 | WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0); |
375 | } |
376 | } |
377 | |
378 | /** |
379 | * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling |
380 | * |
381 | * @adev: amdgpu_device pointer |
382 | * @value: true redirects VM faults to the default page |
383 | */ |
384 | static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value) |
385 | { |
386 | u32 tmp; |
387 | |
388 | if (amdgpu_sriov_vf(adev)) |
389 | return; |
390 | |
391 | tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); |
392 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
393 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
394 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
395 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
396 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
397 | PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
398 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
399 | PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
400 | tmp = REG_SET_FIELD(tmp, |
401 | VM_L2_PROTECTION_FAULT_CNTL, |
402 | TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, |
403 | value); |
404 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
405 | NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
406 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
407 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
408 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
409 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
410 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
411 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
412 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
413 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
414 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
415 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
416 | if (!value) { |
417 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
418 | CRASH_ON_NO_RETRY_FAULT, 1); |
419 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
420 | CRASH_ON_RETRY_FAULT, 1); |
421 | } |
422 | |
423 | WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp); |
424 | } |
425 | |
426 | static void mmhub_v1_7_init(struct amdgpu_device *adev) |
427 | { |
428 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
429 | |
430 | hub->ctx0_ptb_addr_lo32 = |
431 | SOC15_REG_OFFSET(MMHUB, 0, |
432 | regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); |
433 | hub->ctx0_ptb_addr_hi32 = |
434 | SOC15_REG_OFFSET(MMHUB, 0, |
435 | regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); |
436 | hub->vm_inv_eng0_req = |
437 | SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ); |
438 | hub->vm_inv_eng0_ack = |
439 | SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK); |
440 | hub->vm_context0_cntl = |
441 | SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL); |
442 | hub->vm_l2_pro_fault_status = |
443 | SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS); |
444 | hub->vm_l2_pro_fault_cntl = |
445 | SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); |
446 | |
447 | hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL; |
448 | hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - |
449 | regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; |
450 | hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ; |
451 | hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - |
452 | regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; |
453 | |
454 | } |
455 | |
456 | static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
457 | bool enable) |
458 | { |
459 | uint32_t def, data, def1, data1, def2 = 0, data2 = 0; |
460 | |
461 | def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); |
462 | |
463 | def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); |
464 | def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); |
465 | |
466 | if (enable) { |
467 | data |= ATC_L2_MISC_CG__ENABLE_MASK; |
468 | |
469 | data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | |
470 | DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | |
471 | DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | |
472 | DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | |
473 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | |
474 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); |
475 | |
476 | data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | |
477 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | |
478 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | |
479 | DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | |
480 | DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | |
481 | DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); |
482 | } else { |
483 | data &= ~ATC_L2_MISC_CG__ENABLE_MASK; |
484 | |
485 | data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | |
486 | DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | |
487 | DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | |
488 | DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | |
489 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | |
490 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); |
491 | |
492 | data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | |
493 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | |
494 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | |
495 | DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | |
496 | DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | |
497 | DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); |
498 | } |
499 | |
500 | if (def != data) |
501 | WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data); |
502 | |
503 | if (def1 != data1) |
504 | WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1); |
505 | |
506 | if (def2 != data2) |
507 | WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); |
508 | } |
509 | |
510 | static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev, |
511 | bool enable) |
512 | { |
513 | uint32_t def, data; |
514 | |
515 | def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); |
516 | |
517 | if (enable) |
518 | data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; |
519 | else |
520 | data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; |
521 | |
522 | if (def != data) |
523 | WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data); |
524 | } |
525 | |
526 | static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev, |
527 | enum amd_clockgating_state state) |
528 | { |
529 | if (amdgpu_sriov_vf(adev)) |
530 | return 0; |
531 | |
532 | /* Change state only if MCCG support is enabled through driver */ |
533 | if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) |
534 | mmhub_v1_7_update_medium_grain_clock_gating(adev, |
535 | enable: state == AMD_CG_STATE_GATE); |
536 | |
537 | /* Change state only if LS support is enabled through driver */ |
538 | if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) |
539 | mmhub_v1_7_update_medium_grain_light_sleep(adev, |
540 | enable: state == AMD_CG_STATE_GATE); |
541 | |
542 | return 0; |
543 | } |
544 | |
545 | static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u64 *flags) |
546 | { |
547 | int data, data1; |
548 | |
549 | if (amdgpu_sriov_vf(adev)) |
550 | *flags = 0; |
551 | |
552 | data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); |
553 | |
554 | data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); |
555 | |
556 | /* AMD_CG_SUPPORT_MC_MGCG */ |
557 | if ((data & ATC_L2_MISC_CG__ENABLE_MASK) && |
558 | !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | |
559 | DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | |
560 | DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | |
561 | DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | |
562 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | |
563 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) |
564 | *flags |= AMD_CG_SUPPORT_MC_MGCG; |
565 | |
566 | /* AMD_CG_SUPPORT_MC_LS */ |
567 | if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) |
568 | *flags |= AMD_CG_SUPPORT_MC_LS; |
569 | } |
570 | |
571 | static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = { |
572 | /* MMHUB Range 0 */ |
573 | { "MMEA0_DRAMRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
574 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), |
575 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), |
576 | }, |
577 | { "MMEA0_DRAMWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
578 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), |
579 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), |
580 | }, |
581 | { "MMEA0_DRAMWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
582 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), |
583 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), |
584 | }, |
585 | { "MMEA0_RRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
586 | SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT), |
587 | SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT), |
588 | }, |
589 | { "MMEA0_WRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
590 | SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT), |
591 | SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT), |
592 | }, |
593 | { "MMEA0_IOWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
594 | SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), |
595 | SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT), |
596 | }, |
597 | { "MMEA0_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
598 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), |
599 | 0, 0, |
600 | }, |
601 | { "MMEA0_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
602 | SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), |
603 | 0, 0, |
604 | }, |
605 | { "MMEA0_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
606 | SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT), |
607 | 0, 0, |
608 | }, |
609 | { "MMEA0_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), |
610 | SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT), |
611 | 0, 0, |
612 | }, |
613 | { "MMEA0_GMIRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
614 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), |
615 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), |
616 | }, |
617 | { "MMEA0_GMIWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
618 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), |
619 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), |
620 | }, |
621 | { "MMEA0_GMIWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
622 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), |
623 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), |
624 | }, |
625 | { "MMEA0_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
626 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), |
627 | 0, 0, |
628 | }, |
629 | { "MMEA0_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
630 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), |
631 | 0, 0, |
632 | }, |
633 | { "MMEA0_MAM_D0MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
634 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), |
635 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), |
636 | }, |
637 | { "MMEA0_MAM_D1MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
638 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT), |
639 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT), |
640 | }, |
641 | { "MMEA0_MAM_D2MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
642 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT), |
643 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT), |
644 | }, |
645 | { "MMEA0_MAM_D3MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), |
646 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT), |
647 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT), |
648 | }, |
649 | { "MMEA0_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), |
650 | 0, 0, |
651 | SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), |
652 | }, |
653 | { "MMEA0_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), |
654 | 0, 0, |
655 | SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), |
656 | }, |
657 | { "MMEA0_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), |
658 | 0, 0, |
659 | SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT), |
660 | }, |
661 | { "MMEA0_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), |
662 | 0, 0, |
663 | SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), |
664 | }, |
665 | { "MMEA0_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), |
666 | 0, 0, |
667 | SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), |
668 | }, |
669 | { "MMEA0_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), |
670 | 0, 0, |
671 | SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), |
672 | }, |
673 | |
674 | /* MMHUB Range 1 */ |
675 | { "MMEA1_DRAMRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
676 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), |
677 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), |
678 | }, |
679 | { "MMEA1_DRAMWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
680 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), |
681 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), |
682 | }, |
683 | { "MMEA1_DRAMWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
684 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), |
685 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), |
686 | }, |
687 | { "MMEA1_RRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
688 | SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT), |
689 | SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT), |
690 | }, |
691 | { "MMEA1_WRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
692 | SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT), |
693 | SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT), |
694 | }, |
695 | { "MMEA1_IOWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
696 | SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), |
697 | SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT), |
698 | }, |
699 | { "MMEA1_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
700 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), |
701 | 0, 0, |
702 | }, |
703 | { "MMEA1_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
704 | SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), |
705 | 0, 0, |
706 | }, |
707 | { "MMEA1_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
708 | SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT), |
709 | 0, 0, |
710 | }, |
711 | { "MMEA1_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), |
712 | SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT), |
713 | 0, 0, |
714 | }, |
715 | { "MMEA1_GMIRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
716 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), |
717 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), |
718 | }, |
719 | { "MMEA1_GMIWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
720 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), |
721 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), |
722 | }, |
723 | { "MMEA1_GMIWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
724 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), |
725 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), |
726 | }, |
727 | { "MMEA1_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
728 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), |
729 | 0, 0, |
730 | }, |
731 | { "MMEA1_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
732 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), |
733 | 0, 0, |
734 | }, |
735 | { "MMEA1_MAM_D0MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
736 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT), |
737 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT), |
738 | }, |
739 | { "MMEA1_MAM_D1MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
740 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT), |
741 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT), |
742 | }, |
743 | { "MMEA1_MAM_D2MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
744 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT), |
745 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT), |
746 | }, |
747 | { "MMEA1_MAM_D3MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), |
748 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT), |
749 | SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT), |
750 | }, |
751 | { "MMEA1_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), |
752 | 0, 0, |
753 | SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), |
754 | }, |
755 | { "MMEA1_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), |
756 | 0, 0, |
757 | SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), |
758 | }, |
759 | { "MMEA1_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), |
760 | 0, 0, |
761 | SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT), |
762 | }, |
763 | { "MMEA1_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), |
764 | 0, 0, |
765 | SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), |
766 | }, |
767 | { "MMEA1_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), |
768 | 0, 0, |
769 | SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), |
770 | }, |
771 | { "MMEA1_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), |
772 | 0, 0, |
773 | SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), |
774 | }, |
775 | |
776 | /* MMHAB Range 2*/ |
777 | { "MMEA2_DRAMRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
778 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), |
779 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), |
780 | }, |
781 | { "MMEA2_DRAMWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
782 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), |
783 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), |
784 | }, |
785 | { "MMEA2_DRAMWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
786 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), |
787 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), |
788 | }, |
789 | { "MMEA2_RRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
790 | SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT), |
791 | SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT), |
792 | }, |
793 | { "MMEA2_WRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
794 | SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT), |
795 | SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT), |
796 | }, |
797 | { "MMEA2_IOWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
798 | SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), |
799 | SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT), |
800 | }, |
801 | { "MMEA2_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
802 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), |
803 | 0, 0, |
804 | }, |
805 | { "MMEA2_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
806 | SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), |
807 | 0, 0, |
808 | }, |
809 | { "MMEA2_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
810 | SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT), |
811 | 0, 0, |
812 | }, |
813 | { "MMEA2_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), |
814 | SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT), |
815 | 0, 0, |
816 | }, |
817 | { "MMEA2_GMIRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
818 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), |
819 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), |
820 | }, |
821 | { "MMEA2_GMIWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
822 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), |
823 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), |
824 | }, |
825 | { "MMEA2_GMIWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
826 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), |
827 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), |
828 | }, |
829 | { "MMEA2_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
830 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), |
831 | 0, 0, |
832 | }, |
833 | { "MMEA2_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
834 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), |
835 | 0, 0, |
836 | }, |
837 | { "MMEA2_MAM_D0MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
838 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), |
839 | SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), |
840 | }, |
841 | { "MMEA2_MAM_D1MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
842 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT), |
843 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT), |
844 | }, |
845 | { "MMEA2_MAM_D2MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
846 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT), |
847 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT), |
848 | }, |
849 | { "MMEA2_MAM_D3MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), |
850 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT), |
851 | SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT), |
852 | }, |
853 | { "MMEA2_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), |
854 | 0, 0, |
855 | SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), |
856 | }, |
857 | { "MMEA2_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), |
858 | 0, 0, |
859 | SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), |
860 | }, |
861 | { "MMEA2_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), |
862 | 0, 0, |
863 | SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT), |
864 | }, |
865 | { "MMEA2_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), |
866 | 0, 0, |
867 | SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), |
868 | }, |
869 | { "MMEA2_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), |
870 | 0, 0, |
871 | SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), |
872 | }, |
873 | { "MMEA2_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), |
874 | 0, 0, |
875 | SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), |
876 | }, |
877 | |
878 | /* MMHUB Rang 3 */ |
879 | { "MMEA3_DRAMRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
880 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), |
881 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), |
882 | }, |
883 | { "MMEA3_DRAMWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
884 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), |
885 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), |
886 | }, |
887 | { "MMEA3_DRAMWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
888 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), |
889 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), |
890 | }, |
891 | { "MMEA3_RRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
892 | SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT), |
893 | SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT), |
894 | }, |
895 | { "MMEA3_WRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
896 | SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT), |
897 | SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT), |
898 | }, |
899 | { "MMEA3_IOWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
900 | SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), |
901 | SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT), |
902 | }, |
903 | { "MMEA3_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
904 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), |
905 | 0, 0, |
906 | }, |
907 | { "MMEA3_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
908 | SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), |
909 | 0, 0, |
910 | }, |
911 | { "MMEA3_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
912 | SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT), |
913 | 0, 0, |
914 | }, |
915 | { "MMEA3_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), |
916 | SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT), |
917 | 0, 0, |
918 | }, |
919 | { "MMEA3_GMIRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
920 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), |
921 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), |
922 | }, |
923 | { "MMEA3_GMIWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
924 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), |
925 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), |
926 | }, |
927 | { "MMEA3_GMIWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
928 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), |
929 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), |
930 | }, |
931 | { "MMEA3_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
932 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), |
933 | 0, 0, |
934 | }, |
935 | { "MMEA3_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
936 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), |
937 | 0, 0, |
938 | }, |
939 | { "MMEA3_MAM_D0MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
940 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT), |
941 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT), |
942 | }, |
943 | { "MMEA3_MAM_D1MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
944 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT), |
945 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT), |
946 | }, |
947 | { "MMEA3_MAM_D2MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
948 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT), |
949 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT), |
950 | }, |
951 | { "MMEA3_MAM_D3MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), |
952 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT), |
953 | SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT), |
954 | }, |
955 | { "MMEA3_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), |
956 | 0, 0, |
957 | SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), |
958 | }, |
959 | { "MMEA3_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), |
960 | 0, 0, |
961 | SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), |
962 | }, |
963 | { "MMEA3_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), |
964 | 0, 0, |
965 | SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT), |
966 | }, |
967 | { "MMEA3_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), |
968 | 0, 0, |
969 | SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), |
970 | }, |
971 | { "MMEA3_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), |
972 | 0, 0, |
973 | SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), |
974 | }, |
975 | { "MMEA3_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), |
976 | 0, 0, |
977 | SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), |
978 | }, |
979 | |
980 | /* MMHUB Range 4 */ |
981 | { "MMEA4_DRAMRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
982 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), |
983 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), |
984 | }, |
985 | { "MMEA4_DRAMWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
986 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), |
987 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), |
988 | }, |
989 | { "MMEA4_DRAMWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
990 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), |
991 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), |
992 | }, |
993 | { "MMEA4_RRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
994 | SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT), |
995 | SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT), |
996 | }, |
997 | { "MMEA4_WRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
998 | SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT), |
999 | SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT), |
1000 | }, |
1001 | { "MMEA4_IOWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
1002 | SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), |
1003 | SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT), |
1004 | }, |
1005 | { "MMEA4_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
1006 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), |
1007 | 0, 0, |
1008 | }, |
1009 | { "MMEA4_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
1010 | SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), |
1011 | 0, 0, |
1012 | }, |
1013 | { "MMEA4_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
1014 | SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT), |
1015 | 0, 0, |
1016 | }, |
1017 | { "MMEA4_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), |
1018 | SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT), |
1019 | 0, 0, |
1020 | }, |
1021 | { "MMEA4_GMIRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1022 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), |
1023 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), |
1024 | }, |
1025 | { "MMEA4_GMIWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1026 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), |
1027 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), |
1028 | }, |
1029 | { "MMEA4_GMIWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1030 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), |
1031 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), |
1032 | }, |
1033 | { "MMEA4_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1034 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), |
1035 | 0, 0, |
1036 | }, |
1037 | { "MMEA4_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1038 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), |
1039 | 0, 0, |
1040 | }, |
1041 | { "MMEA4_MAM_D0MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1042 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT), |
1043 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT), |
1044 | }, |
1045 | { "MMEA4_MAM_D1MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1046 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT), |
1047 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT), |
1048 | }, |
1049 | { "MMEA4_MAM_D2MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1050 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT), |
1051 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT), |
1052 | }, |
1053 | { "MMEA4_MAM_D3MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), |
1054 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT), |
1055 | SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT), |
1056 | }, |
1057 | { "MMEA4_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), |
1058 | 0, 0, |
1059 | SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), |
1060 | }, |
1061 | { "MMEA4_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), |
1062 | 0, 0, |
1063 | SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), |
1064 | }, |
1065 | { "MMEA4_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), |
1066 | 0, 0, |
1067 | SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT), |
1068 | }, |
1069 | { "MMEA4_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), |
1070 | 0, 0, |
1071 | SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), |
1072 | }, |
1073 | { "MMEA4_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), |
1074 | 0, 0, |
1075 | SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), |
1076 | }, |
1077 | { "MMEA4_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), |
1078 | 0, 0, |
1079 | SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), |
1080 | }, |
1081 | |
1082 | /* MMHUAB Range 5 */ |
1083 | { "MMEA5_DRAMRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1084 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), |
1085 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), |
1086 | }, |
1087 | { "MMEA5_DRAMWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1088 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), |
1089 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), |
1090 | }, |
1091 | { "MMEA5_DRAMWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1092 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), |
1093 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), |
1094 | }, |
1095 | { "MMEA5_RRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1096 | SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT), |
1097 | SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT), |
1098 | }, |
1099 | { "MMEA5_WRET_TAGMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1100 | SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT), |
1101 | SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT), |
1102 | }, |
1103 | { "MMEA5_IOWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1104 | SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), |
1105 | SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT), |
1106 | }, |
1107 | { "MMEA5_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1108 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), |
1109 | 0, 0, |
1110 | }, |
1111 | { "MMEA5_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1112 | SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), |
1113 | 0, 0, |
1114 | }, |
1115 | { "MMEA5_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1116 | SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT), |
1117 | 0, 0, |
1118 | }, |
1119 | { "MMEA5_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), |
1120 | SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT), |
1121 | 0, 0, |
1122 | }, |
1123 | { "MMEA5_GMIRD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1124 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), |
1125 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), |
1126 | }, |
1127 | { "MMEA5_GMIWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1128 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), |
1129 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), |
1130 | }, |
1131 | { "MMEA5_GMIWR_DATAMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1132 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), |
1133 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), |
1134 | }, |
1135 | { "MMEA5_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1136 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), |
1137 | 0, 0, |
1138 | }, |
1139 | { "MMEA5_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1140 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), |
1141 | 0, 0, |
1142 | }, |
1143 | { "MMEA5_MAM_D0MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1144 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT), |
1145 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT), |
1146 | }, |
1147 | { "MMEA5_MAM_D1MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1148 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT), |
1149 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT), |
1150 | }, |
1151 | { "MMEA5_MAM_D2MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1152 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT), |
1153 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT), |
1154 | }, |
1155 | { "MMEA5_MAM_D3MEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), |
1156 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT), |
1157 | SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT), |
1158 | }, |
1159 | { "MMEA5_DRAMRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), |
1160 | 0, 0, |
1161 | SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), |
1162 | }, |
1163 | { "MMEA5_DRAMWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), |
1164 | 0, 0, |
1165 | SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), |
1166 | }, |
1167 | { "MMEA5_IORD_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), |
1168 | 0, 0, |
1169 | SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT), |
1170 | }, |
1171 | { "MMEA5_IOWR_CMDMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), |
1172 | 0, 0, |
1173 | SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), |
1174 | }, |
1175 | { "MMEA5_GMIRD_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), |
1176 | 0, 0, |
1177 | SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), |
1178 | }, |
1179 | { "MMEA5_GMIWR_PAGEMEM" , SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), |
1180 | 0, 0, |
1181 | SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), |
1182 | }, |
1183 | }; |
1184 | |
1185 | static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = { |
1186 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 }, |
1187 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 }, |
1188 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 }, |
1189 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 }, |
1190 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 }, |
1191 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 }, |
1192 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 }, |
1193 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 }, |
1194 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 }, |
1195 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 }, |
1196 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 }, |
1197 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 }, |
1198 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 }, |
1199 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 }, |
1200 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 }, |
1201 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 }, |
1202 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 }, |
1203 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 }, |
1204 | }; |
1205 | |
1206 | static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev, |
1207 | const struct soc15_reg_entry *reg, |
1208 | uint32_t value, |
1209 | uint32_t *sec_count, |
1210 | uint32_t *ded_count) |
1211 | { |
1212 | uint32_t i; |
1213 | uint32_t sec_cnt, ded_cnt; |
1214 | |
1215 | for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) { |
1216 | if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset) |
1217 | continue; |
1218 | |
1219 | sec_cnt = (value & |
1220 | mmhub_v1_7_ras_fields[i].sec_count_mask) >> |
1221 | mmhub_v1_7_ras_fields[i].sec_count_shift; |
1222 | if (sec_cnt) { |
1223 | dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n" , |
1224 | mmhub_v1_7_ras_fields[i].name, |
1225 | sec_cnt); |
1226 | *sec_count += sec_cnt; |
1227 | } |
1228 | |
1229 | ded_cnt = (value & |
1230 | mmhub_v1_7_ras_fields[i].ded_count_mask) >> |
1231 | mmhub_v1_7_ras_fields[i].ded_count_shift; |
1232 | if (ded_cnt) { |
1233 | dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n" , |
1234 | mmhub_v1_7_ras_fields[i].name, |
1235 | ded_cnt); |
1236 | *ded_count += ded_cnt; |
1237 | } |
1238 | } |
1239 | |
1240 | return 0; |
1241 | } |
1242 | |
1243 | static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev, |
1244 | void *ras_error_status) |
1245 | { |
1246 | struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; |
1247 | uint32_t sec_count = 0, ded_count = 0; |
1248 | uint32_t i; |
1249 | uint32_t reg_value; |
1250 | |
1251 | err_data->ue_count = 0; |
1252 | err_data->ce_count = 0; |
1253 | |
1254 | for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) { |
1255 | reg_value = |
1256 | RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i])); |
1257 | if (reg_value) |
1258 | mmhub_v1_7_get_ras_error_count(adev, reg: &mmhub_v1_7_edc_cnt_regs[i], |
1259 | value: reg_value, sec_count: &sec_count, ded_count: &ded_count); |
1260 | } |
1261 | |
1262 | err_data->ce_count += sec_count; |
1263 | err_data->ue_count += ded_count; |
1264 | } |
1265 | |
1266 | static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev) |
1267 | { |
1268 | uint32_t i; |
1269 | |
1270 | /* write 0 to reset the edc counters */ |
1271 | if (amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__MMHUB)) { |
1272 | for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) |
1273 | WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0); |
1274 | } |
1275 | } |
1276 | |
1277 | static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = { |
1278 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 }, |
1279 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 }, |
1280 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 }, |
1281 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 }, |
1282 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 }, |
1283 | { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 }, |
1284 | }; |
1285 | |
1286 | static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev) |
1287 | { |
1288 | int i; |
1289 | uint32_t reg_value; |
1290 | |
1291 | if (!amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__MMHUB)) |
1292 | return; |
1293 | |
1294 | for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) { |
1295 | reg_value = |
1296 | RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i])); |
1297 | if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) || |
1298 | REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) || |
1299 | REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { |
1300 | dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n" , |
1301 | i, reg_value); |
1302 | } |
1303 | } |
1304 | } |
1305 | |
1306 | static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev) |
1307 | { |
1308 | int i; |
1309 | uint32_t reg_value; |
1310 | |
1311 | if (!amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__MMHUB)) |
1312 | return; |
1313 | |
1314 | for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) { |
1315 | reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( |
1316 | mmhub_v1_7_ea_err_status_regs[i])); |
1317 | reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS, |
1318 | CLEAR_ERROR_STATUS, 0x01); |
1319 | WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]), |
1320 | reg_value); |
1321 | } |
1322 | } |
1323 | |
1324 | struct amdgpu_ras_block_hw_ops mmhub_v1_7_ras_hw_ops = { |
1325 | .query_ras_error_count = mmhub_v1_7_query_ras_error_count, |
1326 | .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count, |
1327 | .query_ras_error_status = mmhub_v1_7_query_ras_error_status, |
1328 | .reset_ras_error_status = mmhub_v1_7_reset_ras_error_status, |
1329 | }; |
1330 | |
1331 | struct amdgpu_mmhub_ras mmhub_v1_7_ras = { |
1332 | .ras_block = { |
1333 | .hw_ops = &mmhub_v1_7_ras_hw_ops, |
1334 | }, |
1335 | }; |
1336 | |
1337 | const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = { |
1338 | .get_fb_location = mmhub_v1_7_get_fb_location, |
1339 | .init = mmhub_v1_7_init, |
1340 | .gart_enable = mmhub_v1_7_gart_enable, |
1341 | .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default, |
1342 | .gart_disable = mmhub_v1_7_gart_disable, |
1343 | .set_clockgating = mmhub_v1_7_set_clockgating, |
1344 | .get_clockgating = mmhub_v1_7_get_clockgating, |
1345 | .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs, |
1346 | }; |
1347 | |