1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #ifndef __MXGPU_NV_H__ |
25 | #define __MXGPU_NV_H__ |
26 | |
27 | #define NV_MAILBOX_POLL_ACK_TIMEDOUT 500 |
28 | #define NV_MAILBOX_POLL_MSG_TIMEDOUT 6000 |
29 | #define NV_MAILBOX_POLL_FLR_TIMEDOUT 5000 |
30 | #define NV_MAILBOX_POLL_MSG_REP_MAX 11 |
31 | |
32 | enum idh_request { |
33 | IDH_REQ_GPU_INIT_ACCESS = 1, |
34 | IDH_REL_GPU_INIT_ACCESS, |
35 | IDH_REQ_GPU_FINI_ACCESS, |
36 | IDH_REL_GPU_FINI_ACCESS, |
37 | IDH_REQ_GPU_RESET_ACCESS, |
38 | IDH_REQ_GPU_INIT_DATA, |
39 | |
40 | IDH_LOG_VF_ERROR = 200, |
41 | IDH_READY_TO_RESET = 201, |
42 | IDH_RAS_POISON = 202, |
43 | }; |
44 | |
45 | enum idh_event { |
46 | IDH_CLR_MSG_BUF = 0, |
47 | IDH_READY_TO_ACCESS_GPU, |
48 | IDH_FLR_NOTIFICATION, |
49 | IDH_FLR_NOTIFICATION_CMPL, |
50 | IDH_SUCCESS, |
51 | IDH_FAIL, |
52 | IDH_QUERY_ALIVE, |
53 | IDH_REQ_GPU_INIT_DATA_READY, |
54 | IDH_RAS_POISON_READY, |
55 | |
56 | IDH_TEXT_MESSAGE = 255, |
57 | }; |
58 | |
59 | extern const struct amdgpu_virt_ops xgpu_nv_virt_ops; |
60 | |
61 | void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev); |
62 | int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev); |
63 | int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev); |
64 | void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev); |
65 | |
66 | #define mmMAILBOX_CONTROL 0xE5E |
67 | |
68 | #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4) |
69 | #define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE + 1) |
70 | |
71 | #define mmMAILBOX_MSGBUF_TRN_DW0 0xE56 |
72 | #define mmMAILBOX_MSGBUF_TRN_DW1 0xE57 |
73 | #define mmMAILBOX_MSGBUF_TRN_DW2 0xE58 |
74 | #define mmMAILBOX_MSGBUF_TRN_DW3 0xE59 |
75 | |
76 | #define mmMAILBOX_MSGBUF_RCV_DW0 0xE5A |
77 | #define mmMAILBOX_MSGBUF_RCV_DW1 0xE5B |
78 | #define mmMAILBOX_MSGBUF_RCV_DW2 0xE5C |
79 | #define mmMAILBOX_MSGBUF_RCV_DW3 0xE5D |
80 | |
81 | #define mmMAILBOX_INT_CNTL 0xE5F |
82 | |
83 | #endif |
84 | |