1 | /* |
2 | * Copyright 2012-16 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | |
27 | #ifndef _DCE_ABM_H_ |
28 | #define _DCE_ABM_H_ |
29 | |
30 | #include "abm.h" |
31 | |
32 | #define ABM_COMMON_REG_LIST_DCE_BASE() \ |
33 | SR(MASTER_COMM_CNTL_REG), \ |
34 | SR(MASTER_COMM_CMD_REG), \ |
35 | SR(MASTER_COMM_DATA_REG1) |
36 | |
37 | #define ABM_DCE110_COMMON_REG_LIST() \ |
38 | ABM_COMMON_REG_LIST_DCE_BASE(), \ |
39 | SR(DC_ABM1_HG_SAMPLE_RATE), \ |
40 | SR(DC_ABM1_LS_SAMPLE_RATE), \ |
41 | SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ |
42 | SR(DC_ABM1_HG_MISC_CTRL), \ |
43 | SR(DC_ABM1_IPCSC_COEFF_SEL), \ |
44 | SR(BL1_PWM_CURRENT_ABM_LEVEL), \ |
45 | SR(BL1_PWM_TARGET_ABM_LEVEL), \ |
46 | SR(BL1_PWM_USER_LEVEL), \ |
47 | SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ |
48 | SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ |
49 | SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \ |
50 | SR(DC_ABM1_ACE_THRES_12), \ |
51 | SR(BIOS_SCRATCH_2) |
52 | |
53 | #define ABM_DCN10_REG_LIST(id)\ |
54 | ABM_COMMON_REG_LIST_DCE_BASE(), \ |
55 | SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ |
56 | SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ |
57 | SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ |
58 | SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ |
59 | SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ |
60 | SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ |
61 | SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ |
62 | SRI(BL1_PWM_USER_LEVEL, ABM, id), \ |
63 | SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ |
64 | SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ |
65 | SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ |
66 | SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ |
67 | NBIO_SR(BIOS_SCRATCH_2) |
68 | |
69 | #define ABM_DCN20_REG_LIST() \ |
70 | ABM_COMMON_REG_LIST_DCE_BASE(), \ |
71 | SR(DC_ABM1_HG_SAMPLE_RATE), \ |
72 | SR(DC_ABM1_LS_SAMPLE_RATE), \ |
73 | SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ |
74 | SR(DC_ABM1_HG_MISC_CTRL), \ |
75 | SR(DC_ABM1_IPCSC_COEFF_SEL), \ |
76 | SR(BL1_PWM_CURRENT_ABM_LEVEL), \ |
77 | SR(BL1_PWM_TARGET_ABM_LEVEL), \ |
78 | SR(BL1_PWM_USER_LEVEL), \ |
79 | SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ |
80 | SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ |
81 | SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \ |
82 | SR(DC_ABM1_ACE_THRES_12), \ |
83 | NBIO_SR(BIOS_SCRATCH_2) |
84 | |
85 | #define ABM_DCN301_REG_LIST(id)\ |
86 | ABM_COMMON_REG_LIST_DCE_BASE(), \ |
87 | SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ |
88 | SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ |
89 | SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ |
90 | SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ |
91 | SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ |
92 | SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ |
93 | SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ |
94 | SRI(BL1_PWM_USER_LEVEL, ABM, id), \ |
95 | SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ |
96 | SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ |
97 | NBIO_SR(BIOS_SCRATCH_2) |
98 | |
99 | #define ABM_DCN302_REG_LIST(id)\ |
100 | ABM_COMMON_REG_LIST_DCE_BASE(), \ |
101 | SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ |
102 | SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ |
103 | SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ |
104 | SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ |
105 | SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ |
106 | SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ |
107 | SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ |
108 | SRI(BL1_PWM_USER_LEVEL, ABM, id), \ |
109 | SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ |
110 | SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ |
111 | SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ |
112 | SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ |
113 | NBIO_SR(BIOS_SCRATCH_2) |
114 | |
115 | #define ABM_DCN30_REG_LIST(id)\ |
116 | ABM_COMMON_REG_LIST_DCE_BASE(), \ |
117 | SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ |
118 | SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ |
119 | SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ |
120 | SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ |
121 | SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ |
122 | SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ |
123 | SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ |
124 | SRI(BL1_PWM_USER_LEVEL, ABM, id), \ |
125 | SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ |
126 | SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ |
127 | SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ |
128 | SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ |
129 | NBIO_SR(BIOS_SCRATCH_2) |
130 | |
131 | #define ABM_SF(reg_name, field_name, post_fix)\ |
132 | .field_name = reg_name ## __ ## field_name ## post_fix |
133 | |
134 | #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ |
135 | ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ |
136 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ |
137 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ |
138 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) |
139 | |
140 | #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ |
141 | ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ |
142 | ABM_SF(DC_ABM1_HG_MISC_CTRL, \ |
143 | ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ |
144 | ABM_SF(DC_ABM1_HG_MISC_CTRL, \ |
145 | ABM1_HG_VMAX_SEL, mask_sh), \ |
146 | ABM_SF(DC_ABM1_HG_MISC_CTRL, \ |
147 | ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ |
148 | ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ |
149 | ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ |
150 | ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ |
151 | ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ |
152 | ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ |
153 | ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ |
154 | ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \ |
155 | BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ |
156 | ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \ |
157 | BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ |
158 | ABM_SF(BL1_PWM_USER_LEVEL, \ |
159 | BL1_PWM_USER_LEVEL, mask_sh), \ |
160 | ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ |
161 | ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ |
162 | ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ |
163 | ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ |
164 | ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
165 | ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ |
166 | ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
167 | ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ |
168 | ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
169 | ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) |
170 | |
171 | #define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \ |
172 | ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ |
173 | ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ |
174 | ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ |
175 | ABM1_HG_VMAX_SEL, mask_sh), \ |
176 | ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ |
177 | ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ |
178 | ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ |
179 | ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ |
180 | ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ |
181 | ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ |
182 | ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ |
183 | ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ |
184 | ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ |
185 | BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ |
186 | ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ |
187 | BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ |
188 | ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ |
189 | BL1_PWM_USER_LEVEL, mask_sh), \ |
190 | ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ |
191 | ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ |
192 | ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ |
193 | ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ |
194 | ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
195 | ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ |
196 | ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
197 | ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ |
198 | ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
199 | ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) |
200 | |
201 | #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ |
202 | ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ |
203 | ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) |
204 | |
205 | #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) |
206 | #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh) |
207 | #define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) |
208 | |
209 | #define ABM_MASK_SH_LIST_DCN32(mask_sh) \ |
210 | ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ |
211 | ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ |
212 | ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ |
213 | ABM1_HG_VMAX_SEL, mask_sh), \ |
214 | ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ |
215 | ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ |
216 | ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ |
217 | ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ |
218 | ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ |
219 | ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ |
220 | ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ |
221 | ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ |
222 | ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ |
223 | BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ |
224 | ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ |
225 | BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ |
226 | ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ |
227 | BL1_PWM_USER_LEVEL, mask_sh), \ |
228 | ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ |
229 | ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ |
230 | ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ |
231 | ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ |
232 | ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
233 | ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ |
234 | ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
235 | ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ |
236 | ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ |
237 | ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) |
238 | |
239 | #define ABM_REG_FIELD_LIST(type) \ |
240 | type ABM1_HG_NUM_OF_BINS_SEL; \ |
241 | type ABM1_HG_VMAX_SEL; \ |
242 | type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \ |
243 | type ABM1_IPCSC_COEFF_SEL_R; \ |
244 | type ABM1_IPCSC_COEFF_SEL_G; \ |
245 | type ABM1_IPCSC_COEFF_SEL_B; \ |
246 | type BL1_PWM_CURRENT_ABM_LEVEL; \ |
247 | type BL1_PWM_TARGET_ABM_LEVEL; \ |
248 | type BL1_PWM_USER_LEVEL; \ |
249 | type ABM1_LS_MIN_PIXEL_VALUE_THRES; \ |
250 | type ABM1_LS_MAX_PIXEL_VALUE_THRES; \ |
251 | type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \ |
252 | type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \ |
253 | type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \ |
254 | type MASTER_COMM_INTERRUPT; \ |
255 | type MASTER_COMM_CMD_REG_BYTE0; \ |
256 | type MASTER_COMM_CMD_REG_BYTE1; \ |
257 | type MASTER_COMM_CMD_REG_BYTE2; \ |
258 | type ABM1_HG_BIN_33_40_SHIFT_INDEX; \ |
259 | type ABM1_HG_BIN_33_64_SHIFT_FLAG; \ |
260 | type ABM1_HG_BIN_41_48_SHIFT_INDEX; \ |
261 | type ABM1_HG_BIN_49_56_SHIFT_INDEX; \ |
262 | type ABM1_HG_BIN_57_64_SHIFT_INDEX; \ |
263 | type ABM1_HG_RESULT_DATA; \ |
264 | type ABM1_HG_RESULT_INDEX; \ |
265 | type ABM1_ACE_SLOPE_DATA; \ |
266 | type ABM1_ACE_OFFSET_DATA; \ |
267 | type ABM1_ACE_OFFSET_SLOPE_INDEX; \ |
268 | type ABM1_ACE_THRES_INDEX; \ |
269 | type ABM1_ACE_IGNORE_MASTER_LOCK_EN; \ |
270 | type ABM1_ACE_READBACK_DB_REG_VALUE_EN; \ |
271 | type ABM1_ACE_DBUF_REG_UPDATE_PENDING; \ |
272 | type ABM1_ACE_LOCK; \ |
273 | type ABM1_ACE_THRES_DATA_1; \ |
274 | type ABM1_ACE_THRES_DATA_2 |
275 | |
276 | struct dce_abm_shift { |
277 | ABM_REG_FIELD_LIST(uint8_t); |
278 | }; |
279 | |
280 | struct dce_abm_mask { |
281 | ABM_REG_FIELD_LIST(uint32_t); |
282 | }; |
283 | |
284 | struct dce_abm_registers { |
285 | uint32_t DC_ABM1_HG_SAMPLE_RATE; |
286 | uint32_t DC_ABM1_LS_SAMPLE_RATE; |
287 | uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; |
288 | uint32_t DC_ABM1_HG_MISC_CTRL; |
289 | uint32_t DC_ABM1_IPCSC_COEFF_SEL; |
290 | uint32_t BL1_PWM_CURRENT_ABM_LEVEL; |
291 | uint32_t BL1_PWM_TARGET_ABM_LEVEL; |
292 | uint32_t BL1_PWM_USER_LEVEL; |
293 | uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; |
294 | uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; |
295 | uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0; |
296 | uint32_t DC_ABM1_ACE_OFFSET_SLOPE_DATA; |
297 | uint32_t DC_ABM1_ACE_PWL_CNTL; |
298 | uint32_t DC_ABM1_HG_BIN_33_40_SHIFT_INDEX; |
299 | uint32_t DC_ABM1_HG_BIN_33_64_SHIFT_FLAG; |
300 | uint32_t DC_ABM1_HG_BIN_41_48_SHIFT_INDEX; |
301 | uint32_t DC_ABM1_HG_BIN_49_56_SHIFT_INDEX; |
302 | uint32_t DC_ABM1_HG_BIN_57_64_SHIFT_INDEX; |
303 | uint32_t DC_ABM1_HG_RESULT_DATA; |
304 | uint32_t DC_ABM1_HG_RESULT_INDEX; |
305 | uint32_t DC_ABM1_ACE_THRES_DATA; |
306 | uint32_t DC_ABM1_ACE_THRES_12; |
307 | uint32_t MASTER_COMM_CNTL_REG; |
308 | uint32_t MASTER_COMM_CMD_REG; |
309 | uint32_t MASTER_COMM_DATA_REG1; |
310 | uint32_t BIOS_SCRATCH_2; |
311 | }; |
312 | |
313 | struct dce_abm { |
314 | struct abm base; |
315 | const struct dce_abm_registers *regs; |
316 | const struct dce_abm_shift *abm_shift; |
317 | const struct dce_abm_mask *abm_mask; |
318 | }; |
319 | |
320 | struct abm *dce_abm_create( |
321 | struct dc_context *ctx, |
322 | const struct dce_abm_registers *regs, |
323 | const struct dce_abm_shift *abm_shift, |
324 | const struct dce_abm_mask *abm_mask); |
325 | |
326 | void dce_abm_destroy(struct abm **abm); |
327 | |
328 | #endif /* _DCE_ABM_H_ */ |
329 | |