1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "reg_helper.h" |
27 | #include "dce_audio.h" |
28 | #include "dce/dce_11_0_d.h" |
29 | #include "dce/dce_11_0_sh_mask.h" |
30 | |
31 | #define DCE_AUD(audio)\ |
32 | container_of(audio, struct dce_audio, base) |
33 | |
34 | #define CTX \ |
35 | aud->base.ctx |
36 | |
37 | #define DC_LOGGER_INIT() |
38 | |
39 | #define REG(reg)\ |
40 | (aud->regs->reg) |
41 | |
42 | #undef FN |
43 | #define FN(reg_name, field_name) \ |
44 | aud->shifts->field_name, aud->masks->field_name |
45 | |
46 | #define IX_REG(reg)\ |
47 | ix ## reg |
48 | |
49 | #define AZ_REG_READ(reg_name) \ |
50 | read_indirect_azalia_reg(audio, IX_REG(reg_name)) |
51 | |
52 | #define AZ_REG_WRITE(reg_name, value) \ |
53 | write_indirect_azalia_reg(audio, IX_REG(reg_name), value) |
54 | |
55 | static void write_indirect_azalia_reg(struct audio *audio, |
56 | uint32_t reg_index, |
57 | uint32_t reg_data) |
58 | { |
59 | struct dce_audio *aud = DCE_AUD(audio); |
60 | |
61 | /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ |
62 | REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, |
63 | AZALIA_ENDPOINT_REG_INDEX, reg_index); |
64 | |
65 | /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ |
66 | REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, |
67 | AZALIA_ENDPOINT_REG_DATA, reg_data); |
68 | } |
69 | |
70 | static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) |
71 | { |
72 | struct dce_audio *aud = DCE_AUD(audio); |
73 | |
74 | uint32_t value = 0; |
75 | |
76 | /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ |
77 | REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, |
78 | AZALIA_ENDPOINT_REG_INDEX, reg_index); |
79 | |
80 | /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ |
81 | value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); |
82 | |
83 | return value; |
84 | } |
85 | |
86 | static bool is_audio_format_supported( |
87 | const struct audio_info *audio_info, |
88 | enum audio_format_code audio_format_code, |
89 | uint32_t *format_index) |
90 | { |
91 | uint32_t index; |
92 | uint32_t max_channe_index = 0; |
93 | bool found = false; |
94 | |
95 | if (audio_info == NULL) |
96 | return found; |
97 | |
98 | /* pass through whole array */ |
99 | for (index = 0; index < audio_info->mode_count; index++) { |
100 | if (audio_info->modes[index].format_code == audio_format_code) { |
101 | if (found) { |
102 | /* format has multiply entries, choose one with |
103 | * highst number of channels */ |
104 | if (audio_info->modes[index].channel_count > |
105 | audio_info->modes[max_channe_index].channel_count) { |
106 | max_channe_index = index; |
107 | } |
108 | } else { |
109 | /* format found, save it's index */ |
110 | found = true; |
111 | max_channe_index = index; |
112 | } |
113 | } |
114 | } |
115 | |
116 | /* return index */ |
117 | if (found && format_index != NULL) |
118 | *format_index = max_channe_index; |
119 | |
120 | return found; |
121 | } |
122 | |
123 | /*For HDMI, calculate if specified sample rates can fit into a given timing */ |
124 | static void check_audio_bandwidth_hdmi( |
125 | const struct audio_crtc_info *crtc_info, |
126 | uint32_t channel_count, |
127 | union audio_sample_rates *sample_rates) |
128 | { |
129 | uint32_t samples; |
130 | uint32_t h_blank; |
131 | bool limit_freq_to_48_khz = false; |
132 | bool limit_freq_to_88_2_khz = false; |
133 | bool limit_freq_to_96_khz = false; |
134 | bool limit_freq_to_174_4_khz = false; |
135 | if (!crtc_info) |
136 | return; |
137 | |
138 | /* For two channels supported return whatever sink support,unmodified*/ |
139 | if (channel_count > 2) { |
140 | |
141 | /* Based on HDMI spec 1.3 Table 7.5 */ |
142 | if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && |
143 | (crtc_info->v_active <= 576) && |
144 | !(crtc_info->interlaced) && |
145 | !(crtc_info->pixel_repetition == 2 || |
146 | crtc_info->pixel_repetition == 4)) { |
147 | limit_freq_to_48_khz = true; |
148 | |
149 | } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && |
150 | (crtc_info->v_active <= 576) && |
151 | (crtc_info->interlaced) && |
152 | (crtc_info->pixel_repetition == 2)) { |
153 | limit_freq_to_88_2_khz = true; |
154 | |
155 | } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && |
156 | (crtc_info->v_active <= 576) && |
157 | !(crtc_info->interlaced)) { |
158 | limit_freq_to_174_4_khz = true; |
159 | } |
160 | } |
161 | |
162 | /* Also do some calculation for the available Audio Bandwidth for the |
163 | * 8 ch (i.e. for the Layout 1 => ch > 2) |
164 | */ |
165 | h_blank = crtc_info->h_total - crtc_info->h_active; |
166 | |
167 | if (crtc_info->pixel_repetition) |
168 | h_blank *= crtc_info->pixel_repetition; |
169 | |
170 | /*based on HDMI spec 1.3 Table 7.5 */ |
171 | h_blank -= 58; |
172 | /*for Control Period */ |
173 | h_blank -= 16; |
174 | |
175 | samples = h_blank * 10; |
176 | /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number |
177 | * of Audio samples per line multiplied by 10 - Layout 1) |
178 | */ |
179 | samples /= 32; |
180 | samples *= crtc_info->v_active; |
181 | /*Number of samples multiplied by 10, per second */ |
182 | samples *= crtc_info->refresh_rate; |
183 | /*Number of Audio samples per second */ |
184 | samples /= 10; |
185 | |
186 | /* @todo do it after deep color is implemented |
187 | * 8xx - deep color bandwidth scaling |
188 | * Extra bandwidth is avaliable in deep color b/c link runs faster than |
189 | * pixel rate. This has the effect of allowing more tmds characters to |
190 | * be transmitted during blank |
191 | */ |
192 | |
193 | switch (crtc_info->color_depth) { |
194 | case COLOR_DEPTH_888: |
195 | samples *= 4; |
196 | break; |
197 | case COLOR_DEPTH_101010: |
198 | samples *= 5; |
199 | break; |
200 | case COLOR_DEPTH_121212: |
201 | samples *= 6; |
202 | break; |
203 | default: |
204 | samples *= 4; |
205 | break; |
206 | } |
207 | |
208 | samples /= 4; |
209 | |
210 | /*check limitation*/ |
211 | if (samples < 88200) |
212 | limit_freq_to_48_khz = true; |
213 | else if (samples < 96000) |
214 | limit_freq_to_88_2_khz = true; |
215 | else if (samples < 176400) |
216 | limit_freq_to_96_khz = true; |
217 | else if (samples < 192000) |
218 | limit_freq_to_174_4_khz = true; |
219 | |
220 | if (sample_rates != NULL) { |
221 | /* limit frequencies */ |
222 | if (limit_freq_to_174_4_khz) |
223 | sample_rates->rate.RATE_192 = 0; |
224 | |
225 | if (limit_freq_to_96_khz) { |
226 | sample_rates->rate.RATE_192 = 0; |
227 | sample_rates->rate.RATE_176_4 = 0; |
228 | } |
229 | if (limit_freq_to_88_2_khz) { |
230 | sample_rates->rate.RATE_192 = 0; |
231 | sample_rates->rate.RATE_176_4 = 0; |
232 | sample_rates->rate.RATE_96 = 0; |
233 | } |
234 | if (limit_freq_to_48_khz) { |
235 | sample_rates->rate.RATE_192 = 0; |
236 | sample_rates->rate.RATE_176_4 = 0; |
237 | sample_rates->rate.RATE_96 = 0; |
238 | sample_rates->rate.RATE_88_2 = 0; |
239 | } |
240 | } |
241 | } |
242 | static struct fixed31_32 get_link_symbol_clk_freq_mhz(enum dc_link_rate link_rate) |
243 | { |
244 | switch (link_rate) { |
245 | case LINK_RATE_LOW: |
246 | return dc_fixpt_from_int(arg: 162); /* 162 MHz */ |
247 | case LINK_RATE_HIGH: |
248 | return dc_fixpt_from_int(arg: 270); /* 270 MHz */ |
249 | case LINK_RATE_HIGH2: |
250 | return dc_fixpt_from_int(arg: 540); /* 540 MHz */ |
251 | case LINK_RATE_HIGH3: |
252 | return dc_fixpt_from_int(arg: 810); /* 810 MHz */ |
253 | case LINK_RATE_UHBR10: |
254 | return dc_fixpt_from_fraction(numerator: 3125, denominator: 10); /* 312.5 MHz */ |
255 | case LINK_RATE_UHBR13_5: |
256 | return dc_fixpt_from_fraction(numerator: 421875, denominator: 1000); /* 421.875 MHz */ |
257 | case LINK_RATE_UHBR20: |
258 | return dc_fixpt_from_int(arg: 625); /* 625 MHz */ |
259 | default: |
260 | /* Unexpected case, this requires debug if encountered. */ |
261 | ASSERT(0); |
262 | return dc_fixpt_from_int(arg: 0); |
263 | } |
264 | } |
265 | |
266 | struct dp_audio_layout_config { |
267 | uint8_t layouts_per_sample_denom; |
268 | uint8_t symbols_per_layout; |
269 | uint8_t max_layouts_per_audio_sdp; |
270 | }; |
271 | |
272 | static void get_audio_layout_config( |
273 | uint32_t channel_count, |
274 | enum dp_link_encoding encoding, |
275 | struct dp_audio_layout_config *output) |
276 | { |
277 | /* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP, |
278 | * with each layout being the same size (8ch layout). |
279 | */ |
280 | if (encoding == DP_8b_10b_ENCODING) { |
281 | if (channel_count == 2) { |
282 | output->layouts_per_sample_denom = 4; |
283 | output->symbols_per_layout = 40; |
284 | output->max_layouts_per_audio_sdp = 1; |
285 | } else if (channel_count == 8 || channel_count == 6) { |
286 | output->layouts_per_sample_denom = 1; |
287 | output->symbols_per_layout = 40; |
288 | output->max_layouts_per_audio_sdp = 1; |
289 | } |
290 | } else if (encoding == DP_128b_132b_ENCODING) { |
291 | if (channel_count == 2) { |
292 | output->layouts_per_sample_denom = 4; |
293 | output->symbols_per_layout = 10; |
294 | output->max_layouts_per_audio_sdp = 1; |
295 | } else if (channel_count == 8 || channel_count == 6) { |
296 | output->layouts_per_sample_denom = 1; |
297 | output->symbols_per_layout = 10; |
298 | output->max_layouts_per_audio_sdp = 1; |
299 | } |
300 | } |
301 | } |
302 | |
303 | static uint32_t get_av_stream_map_lane_count( |
304 | enum dp_link_encoding encoding, |
305 | enum dc_lane_count lane_count, |
306 | bool is_mst) |
307 | { |
308 | uint32_t av_stream_map_lane_count = 0; |
309 | |
310 | if (encoding == DP_8b_10b_ENCODING) { |
311 | if (!is_mst) |
312 | av_stream_map_lane_count = lane_count; |
313 | else |
314 | av_stream_map_lane_count = 4; |
315 | } else if (encoding == DP_128b_132b_ENCODING) { |
316 | av_stream_map_lane_count = 4; |
317 | } |
318 | |
319 | ASSERT(av_stream_map_lane_count != 0); |
320 | |
321 | return av_stream_map_lane_count; |
322 | } |
323 | |
324 | static uint32_t get_audio_sdp_overhead( |
325 | enum dp_link_encoding encoding, |
326 | enum dc_lane_count lane_count, |
327 | bool is_mst) |
328 | { |
329 | uint32_t audio_sdp_overhead = 0; |
330 | |
331 | if (encoding == DP_8b_10b_ENCODING) { |
332 | if (is_mst) |
333 | audio_sdp_overhead = 16; /* 4 * 2 + 8 */ |
334 | else |
335 | audio_sdp_overhead = lane_count * 2 + 8; |
336 | } else if (encoding == DP_128b_132b_ENCODING) { |
337 | audio_sdp_overhead = 10; /* 4 x 2.5 */ |
338 | } |
339 | |
340 | ASSERT(audio_sdp_overhead != 0); |
341 | |
342 | return audio_sdp_overhead; |
343 | } |
344 | |
345 | static uint32_t calculate_required_audio_bw_in_symbols( |
346 | const struct audio_crtc_info *crtc_info, |
347 | const struct dp_audio_layout_config *layout_config, |
348 | uint32_t channel_count, |
349 | uint32_t sample_rate_hz, |
350 | uint32_t av_stream_map_lane_count, |
351 | uint32_t audio_sdp_overhead) |
352 | { |
353 | /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */ |
354 | struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(numerator: 110, denominator: 100); |
355 | struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction( |
356 | numerator: crtc_info->requested_pixel_clock_100Hz, denominator: crtc_info->h_total * 10); |
357 | struct fixed31_32 samples_per_line; |
358 | struct fixed31_32 layouts_per_line; |
359 | struct fixed31_32 symbols_per_sdp_max_layout; |
360 | struct fixed31_32 remainder; |
361 | uint32_t num_sdp_with_max_layouts; |
362 | uint32_t required_symbols_per_hblank; |
363 | |
364 | samples_per_line = dc_fixpt_from_fraction(numerator: sample_rate_hz, denominator: 1000); |
365 | samples_per_line = dc_fixpt_div(arg1: samples_per_line, arg2: horizontal_line_freq_khz); |
366 | layouts_per_line = dc_fixpt_div_int(arg1: samples_per_line, arg2: layout_config->layouts_per_sample_denom); |
367 | |
368 | num_sdp_with_max_layouts = dc_fixpt_floor( |
369 | arg: dc_fixpt_div_int(arg1: layouts_per_line, arg2: layout_config->max_layouts_per_audio_sdp)); |
370 | symbols_per_sdp_max_layout = dc_fixpt_from_int( |
371 | arg: layout_config->max_layouts_per_audio_sdp * layout_config->symbols_per_layout); |
372 | symbols_per_sdp_max_layout = dc_fixpt_add_int(arg1: symbols_per_sdp_max_layout, arg2: audio_sdp_overhead); |
373 | symbols_per_sdp_max_layout = dc_fixpt_mul(arg1: symbols_per_sdp_max_layout, arg2: audio_sdp_margin); |
374 | required_symbols_per_hblank = num_sdp_with_max_layouts; |
375 | required_symbols_per_hblank *= ((dc_fixpt_ceil(arg: symbols_per_sdp_max_layout) + av_stream_map_lane_count) / |
376 | av_stream_map_lane_count) * av_stream_map_lane_count; |
377 | |
378 | if (num_sdp_with_max_layouts != dc_fixpt_ceil( |
379 | arg: dc_fixpt_div_int(arg1: layouts_per_line, arg2: layout_config->max_layouts_per_audio_sdp))) { |
380 | remainder = dc_fixpt_sub_int(arg1: layouts_per_line, |
381 | arg2: num_sdp_with_max_layouts * layout_config->max_layouts_per_audio_sdp); |
382 | remainder = dc_fixpt_mul_int(arg1: remainder, arg2: layout_config->symbols_per_layout); |
383 | remainder = dc_fixpt_add_int(arg1: remainder, arg2: audio_sdp_overhead); |
384 | remainder = dc_fixpt_mul(arg1: remainder, arg2: audio_sdp_margin); |
385 | required_symbols_per_hblank += ((dc_fixpt_ceil(arg: remainder) + av_stream_map_lane_count) / |
386 | av_stream_map_lane_count) * av_stream_map_lane_count; |
387 | } |
388 | |
389 | return required_symbols_per_hblank; |
390 | } |
391 | |
392 | /* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST. |
393 | */ |
394 | static uint32_t calculate_available_hblank_bw_in_symbols( |
395 | const struct audio_crtc_info *crtc_info, |
396 | const struct audio_dp_link_info *dp_link_info) |
397 | { |
398 | uint64_t hblank = crtc_info->h_total - crtc_info->h_active; |
399 | struct fixed31_32 hblank_time_msec = |
400 | dc_fixpt_from_fraction(numerator: hblank * 10, denominator: crtc_info->requested_pixel_clock_100Hz); |
401 | struct fixed31_32 lsclkfreq_mhz = |
402 | get_link_symbol_clk_freq_mhz(link_rate: dp_link_info->link_rate); |
403 | struct fixed31_32 average_stream_sym_bw_frac; |
404 | struct fixed31_32 peak_stream_bw_kbps; |
405 | struct fixed31_32 bits_per_pixel; |
406 | struct fixed31_32 link_bw_kbps; |
407 | struct fixed31_32 available_stream_sym_count; |
408 | uint32_t available_hblank_bw = 0; /* in stream symbols */ |
409 | |
410 | if (crtc_info->dsc_bits_per_pixel) { |
411 | bits_per_pixel = dc_fixpt_from_fraction(numerator: crtc_info->dsc_bits_per_pixel, denominator: 16); |
412 | } else { |
413 | switch (crtc_info->color_depth) { |
414 | case COLOR_DEPTH_666: |
415 | bits_per_pixel = dc_fixpt_from_int(arg: 6); |
416 | break; |
417 | case COLOR_DEPTH_888: |
418 | bits_per_pixel = dc_fixpt_from_int(arg: 8); |
419 | break; |
420 | case COLOR_DEPTH_101010: |
421 | bits_per_pixel = dc_fixpt_from_int(arg: 10); |
422 | break; |
423 | case COLOR_DEPTH_121212: |
424 | bits_per_pixel = dc_fixpt_from_int(arg: 12); |
425 | break; |
426 | default: |
427 | /* Default to commonly supported color depth. */ |
428 | bits_per_pixel = dc_fixpt_from_int(arg: 8); |
429 | break; |
430 | } |
431 | |
432 | bits_per_pixel = dc_fixpt_mul_int(arg1: bits_per_pixel, arg2: 3); |
433 | |
434 | if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR422) { |
435 | bits_per_pixel = dc_fixpt_div_int(arg1: bits_per_pixel, arg2: 3); |
436 | bits_per_pixel = dc_fixpt_mul_int(arg1: bits_per_pixel, arg2: 2); |
437 | } else if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR420) { |
438 | bits_per_pixel = dc_fixpt_div_int(arg1: bits_per_pixel, arg2: 2); |
439 | } |
440 | } |
441 | |
442 | /* Use simple stream BW calculation because mainlink overhead is |
443 | * accounted for separately in the audio BW calculations. |
444 | */ |
445 | peak_stream_bw_kbps = dc_fixpt_from_fraction(numerator: crtc_info->requested_pixel_clock_100Hz, denominator: 10); |
446 | peak_stream_bw_kbps = dc_fixpt_mul(arg1: peak_stream_bw_kbps, arg2: bits_per_pixel); |
447 | link_bw_kbps = dc_fixpt_from_int(arg: dp_link_info->link_bandwidth_kbps); |
448 | average_stream_sym_bw_frac = dc_fixpt_div(arg1: peak_stream_bw_kbps, arg2: link_bw_kbps); |
449 | |
450 | available_stream_sym_count = dc_fixpt_mul_int(arg1: hblank_time_msec, arg2: 1000); |
451 | available_stream_sym_count = dc_fixpt_mul(arg1: available_stream_sym_count, arg2: lsclkfreq_mhz); |
452 | available_stream_sym_count = dc_fixpt_mul(arg1: available_stream_sym_count, arg2: average_stream_sym_bw_frac); |
453 | available_hblank_bw = dc_fixpt_floor(arg: available_stream_sym_count); |
454 | available_hblank_bw *= dp_link_info->lane_count; |
455 | available_hblank_bw -= crtc_info->dsc_num_slices * 4; /* EOC overhead */ |
456 | |
457 | if (available_hblank_bw < dp_link_info->hblank_min_symbol_width) |
458 | available_hblank_bw = dp_link_info->hblank_min_symbol_width; |
459 | |
460 | if (available_hblank_bw < 12) |
461 | available_hblank_bw = 0; |
462 | else |
463 | available_hblank_bw -= 12; /* Main link overhead */ |
464 | |
465 | return available_hblank_bw; |
466 | } |
467 | |
468 | static void check_audio_bandwidth_dp( |
469 | const struct audio_crtc_info *crtc_info, |
470 | const struct audio_dp_link_info *dp_link_info, |
471 | uint32_t channel_count, |
472 | union audio_sample_rates *sample_rates) |
473 | { |
474 | struct dp_audio_layout_config layout_config = {0}; |
475 | uint32_t available_hblank_bw; |
476 | uint32_t av_stream_map_lane_count; |
477 | uint32_t audio_sdp_overhead; |
478 | |
479 | /* TODO: Add validation for SST 8b/10 case */ |
480 | if (!dp_link_info->is_mst && dp_link_info->encoding == DP_8b_10b_ENCODING) |
481 | return; |
482 | |
483 | available_hblank_bw = calculate_available_hblank_bw_in_symbols( |
484 | crtc_info, dp_link_info); |
485 | av_stream_map_lane_count = get_av_stream_map_lane_count( |
486 | encoding: dp_link_info->encoding, lane_count: dp_link_info->lane_count, is_mst: dp_link_info->is_mst); |
487 | audio_sdp_overhead = get_audio_sdp_overhead( |
488 | encoding: dp_link_info->encoding, lane_count: dp_link_info->lane_count, is_mst: dp_link_info->is_mst); |
489 | get_audio_layout_config( |
490 | channel_count, encoding: dp_link_info->encoding, output: &layout_config); |
491 | |
492 | if (layout_config.max_layouts_per_audio_sdp == 0 || |
493 | layout_config.symbols_per_layout == 0 || |
494 | layout_config.layouts_per_sample_denom == 0) { |
495 | return; |
496 | } |
497 | if (available_hblank_bw < calculate_required_audio_bw_in_symbols( |
498 | crtc_info, layout_config: &layout_config, channel_count, sample_rate_hz: 192000, |
499 | av_stream_map_lane_count, audio_sdp_overhead)) |
500 | sample_rates->rate.RATE_192 = 0; |
501 | if (available_hblank_bw < calculate_required_audio_bw_in_symbols( |
502 | crtc_info, layout_config: &layout_config, channel_count, sample_rate_hz: 176400, |
503 | av_stream_map_lane_count, audio_sdp_overhead)) |
504 | sample_rates->rate.RATE_176_4 = 0; |
505 | if (available_hblank_bw < calculate_required_audio_bw_in_symbols( |
506 | crtc_info, layout_config: &layout_config, channel_count, sample_rate_hz: 96000, |
507 | av_stream_map_lane_count, audio_sdp_overhead)) |
508 | sample_rates->rate.RATE_96 = 0; |
509 | if (available_hblank_bw < calculate_required_audio_bw_in_symbols( |
510 | crtc_info, layout_config: &layout_config, channel_count, sample_rate_hz: 88200, |
511 | av_stream_map_lane_count, audio_sdp_overhead)) |
512 | sample_rates->rate.RATE_88_2 = 0; |
513 | if (available_hblank_bw < calculate_required_audio_bw_in_symbols( |
514 | crtc_info, layout_config: &layout_config, channel_count, sample_rate_hz: 48000, |
515 | av_stream_map_lane_count, audio_sdp_overhead)) |
516 | sample_rates->rate.RATE_48 = 0; |
517 | if (available_hblank_bw < calculate_required_audio_bw_in_symbols( |
518 | crtc_info, layout_config: &layout_config, channel_count, sample_rate_hz: 44100, |
519 | av_stream_map_lane_count, audio_sdp_overhead)) |
520 | sample_rates->rate.RATE_44_1 = 0; |
521 | if (available_hblank_bw < calculate_required_audio_bw_in_symbols( |
522 | crtc_info, layout_config: &layout_config, channel_count, sample_rate_hz: 32000, |
523 | av_stream_map_lane_count, audio_sdp_overhead)) |
524 | sample_rates->rate.RATE_32 = 0; |
525 | } |
526 | |
527 | static void check_audio_bandwidth( |
528 | const struct audio_crtc_info *crtc_info, |
529 | const struct audio_dp_link_info *dp_link_info, |
530 | uint32_t channel_count, |
531 | enum signal_type signal, |
532 | union audio_sample_rates *sample_rates) |
533 | { |
534 | switch (signal) { |
535 | case SIGNAL_TYPE_HDMI_TYPE_A: |
536 | check_audio_bandwidth_hdmi( |
537 | crtc_info, channel_count, sample_rates); |
538 | break; |
539 | case SIGNAL_TYPE_EDP: |
540 | case SIGNAL_TYPE_DISPLAY_PORT: |
541 | case SIGNAL_TYPE_DISPLAY_PORT_MST: |
542 | check_audio_bandwidth_dp( |
543 | crtc_info, dp_link_info, channel_count, sample_rates); |
544 | break; |
545 | default: |
546 | break; |
547 | } |
548 | } |
549 | |
550 | /* expose/not expose HBR capability to Audio driver */ |
551 | static void set_high_bit_rate_capable( |
552 | struct audio *audio, |
553 | bool capable) |
554 | { |
555 | uint32_t value = 0; |
556 | |
557 | /* set high bit rate audio capable*/ |
558 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); |
559 | |
560 | set_reg_field_value(value, capable, |
561 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, |
562 | HBR_CAPABLE); |
563 | |
564 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); |
565 | } |
566 | |
567 | /* set video latency in ms/2+1 */ |
568 | static void set_video_latency( |
569 | struct audio *audio, |
570 | int latency_in_ms) |
571 | { |
572 | uint32_t value = 0; |
573 | |
574 | if ((latency_in_ms < 0) || (latency_in_ms > 255)) |
575 | return; |
576 | |
577 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); |
578 | |
579 | set_reg_field_value(value, latency_in_ms, |
580 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
581 | VIDEO_LIPSYNC); |
582 | |
583 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
584 | value); |
585 | } |
586 | |
587 | /* set audio latency in ms/2+1 */ |
588 | static void set_audio_latency( |
589 | struct audio *audio, |
590 | int latency_in_ms) |
591 | { |
592 | uint32_t value = 0; |
593 | |
594 | if (latency_in_ms < 0) |
595 | latency_in_ms = 0; |
596 | |
597 | if (latency_in_ms > 255) |
598 | latency_in_ms = 255; |
599 | |
600 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); |
601 | |
602 | set_reg_field_value(value, latency_in_ms, |
603 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
604 | AUDIO_LIPSYNC); |
605 | |
606 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
607 | value); |
608 | } |
609 | |
610 | void dce_aud_az_enable(struct audio *audio) |
611 | { |
612 | uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
613 | DC_LOGGER_INIT(); |
614 | |
615 | set_reg_field_value(value, 1, |
616 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
617 | CLOCK_GATING_DISABLE); |
618 | set_reg_field_value(value, 1, |
619 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
620 | AUDIO_ENABLED); |
621 | |
622 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
623 | set_reg_field_value(value, 0, |
624 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
625 | CLOCK_GATING_DISABLE); |
626 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
627 | |
628 | DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n" , |
629 | audio->inst, value); |
630 | } |
631 | |
632 | void dce_aud_az_disable(struct audio *audio) |
633 | { |
634 | uint32_t value; |
635 | DC_LOGGER_INIT(); |
636 | |
637 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
638 | set_reg_field_value(value, 1, |
639 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
640 | CLOCK_GATING_DISABLE); |
641 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
642 | |
643 | set_reg_field_value(value, 0, |
644 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
645 | AUDIO_ENABLED); |
646 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
647 | |
648 | set_reg_field_value(value, 0, |
649 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
650 | CLOCK_GATING_DISABLE); |
651 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
652 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
653 | DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n" , |
654 | audio->inst, value); |
655 | } |
656 | |
657 | void dce_aud_az_configure( |
658 | struct audio *audio, |
659 | enum signal_type signal, |
660 | const struct audio_crtc_info *crtc_info, |
661 | const struct audio_info *audio_info, |
662 | const struct audio_dp_link_info *dp_link_info) |
663 | { |
664 | struct dce_audio *aud = DCE_AUD(audio); |
665 | |
666 | uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; |
667 | uint32_t value; |
668 | uint32_t field = 0; |
669 | enum audio_format_code audio_format_code; |
670 | uint32_t format_index; |
671 | uint32_t index; |
672 | bool is_ac3_supported = false; |
673 | union audio_sample_rates sample_rate; |
674 | uint32_t strlen = 0; |
675 | |
676 | if (signal == SIGNAL_TYPE_VIRTUAL) |
677 | return; |
678 | |
679 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
680 | set_reg_field_value(value, 1, |
681 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
682 | CLOCK_GATING_DISABLE); |
683 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
684 | |
685 | /* Speaker Allocation */ |
686 | /* |
687 | uint32_t value; |
688 | uint32_t field = 0;*/ |
689 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
690 | |
691 | set_reg_field_value(value, |
692 | speakers, |
693 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
694 | SPEAKER_ALLOCATION); |
695 | |
696 | /* LFE_PLAYBACK_LEVEL = LFEPBL |
697 | * LFEPBL = 0 : Unknown or refer to other information |
698 | * LFEPBL = 1 : 0dB playback |
699 | * LFEPBL = 2 : +10dB playback |
700 | * LFE_BL = 3 : Reserved |
701 | */ |
702 | set_reg_field_value(value, |
703 | 0, |
704 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
705 | LFE_PLAYBACK_LEVEL); |
706 | /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. |
707 | * why are we writing to it? DCE8 does not write this */ |
708 | |
709 | |
710 | set_reg_field_value(value, |
711 | 0, |
712 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
713 | HDMI_CONNECTION); |
714 | |
715 | set_reg_field_value(value, |
716 | 0, |
717 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
718 | DP_CONNECTION); |
719 | |
720 | field = get_reg_field_value(value, |
721 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
722 | EXTRA_CONNECTION_INFO); |
723 | |
724 | field &= ~0x1; |
725 | |
726 | set_reg_field_value(value, |
727 | field, |
728 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
729 | EXTRA_CONNECTION_INFO); |
730 | |
731 | /* set audio for output signal */ |
732 | switch (signal) { |
733 | case SIGNAL_TYPE_HDMI_TYPE_A: |
734 | set_reg_field_value(value, |
735 | 1, |
736 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
737 | HDMI_CONNECTION); |
738 | |
739 | break; |
740 | |
741 | case SIGNAL_TYPE_EDP: |
742 | case SIGNAL_TYPE_DISPLAY_PORT: |
743 | case SIGNAL_TYPE_DISPLAY_PORT_MST: |
744 | set_reg_field_value(value, |
745 | 1, |
746 | AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
747 | DP_CONNECTION); |
748 | break; |
749 | default: |
750 | BREAK_TO_DEBUGGER(); |
751 | break; |
752 | } |
753 | |
754 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); |
755 | |
756 | /* ACP Data - Supports AI */ |
757 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA); |
758 | |
759 | set_reg_field_value( |
760 | value, |
761 | audio_info->flags.info.SUPPORT_AI, |
762 | AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, |
763 | SUPPORTS_AI); |
764 | |
765 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value); |
766 | |
767 | /* Audio Descriptors */ |
768 | /* pass through all formats */ |
769 | for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; |
770 | format_index++) { |
771 | audio_format_code = |
772 | (AUDIO_FORMAT_CODE_FIRST + format_index); |
773 | |
774 | /* those are unsupported, skip programming */ |
775 | if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || |
776 | audio_format_code == AUDIO_FORMAT_CODE_DST) |
777 | continue; |
778 | |
779 | value = 0; |
780 | |
781 | /* check if supported */ |
782 | if (is_audio_format_supported( |
783 | audio_info, audio_format_code, format_index: &index)) { |
784 | const struct audio_mode *audio_mode = |
785 | &audio_info->modes[index]; |
786 | union audio_sample_rates sample_rates = |
787 | audio_mode->sample_rates; |
788 | uint8_t byte2 = audio_mode->max_bit_rate; |
789 | uint8_t channel_count = audio_mode->channel_count; |
790 | |
791 | /* adjust specific properties */ |
792 | switch (audio_format_code) { |
793 | case AUDIO_FORMAT_CODE_LINEARPCM: { |
794 | |
795 | check_audio_bandwidth( |
796 | crtc_info, |
797 | dp_link_info, |
798 | channel_count, |
799 | signal, |
800 | sample_rates: &sample_rates); |
801 | |
802 | byte2 = audio_mode->sample_size; |
803 | |
804 | set_reg_field_value(value, |
805 | sample_rates.all, |
806 | AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
807 | SUPPORTED_FREQUENCIES_STEREO); |
808 | } |
809 | break; |
810 | case AUDIO_FORMAT_CODE_AC3: |
811 | is_ac3_supported = true; |
812 | break; |
813 | case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: |
814 | case AUDIO_FORMAT_CODE_DTS_HD: |
815 | case AUDIO_FORMAT_CODE_MAT_MLP: |
816 | case AUDIO_FORMAT_CODE_DST: |
817 | case AUDIO_FORMAT_CODE_WMAPRO: |
818 | byte2 = audio_mode->vendor_specific; |
819 | break; |
820 | default: |
821 | break; |
822 | } |
823 | |
824 | /* fill audio format data */ |
825 | set_reg_field_value(value, |
826 | channel_count - 1, |
827 | AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
828 | MAX_CHANNELS); |
829 | |
830 | set_reg_field_value(value, |
831 | sample_rates.all, |
832 | AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
833 | SUPPORTED_FREQUENCIES); |
834 | |
835 | set_reg_field_value(value, |
836 | byte2, |
837 | AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
838 | DESCRIPTOR_BYTE_2); |
839 | } /* if */ |
840 | |
841 | AZ_REG_WRITE( |
842 | AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, |
843 | value); |
844 | } /* for */ |
845 | |
846 | if (is_ac3_supported) |
847 | /* todo: this reg global. why program global register? */ |
848 | REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, |
849 | 0x05); |
850 | |
851 | /* check for 192khz/8-Ch support for HBR requirements */ |
852 | sample_rate.all = 0; |
853 | sample_rate.rate.RATE_192 = 1; |
854 | |
855 | check_audio_bandwidth( |
856 | crtc_info, |
857 | dp_link_info, |
858 | channel_count: 8, |
859 | signal, |
860 | sample_rates: &sample_rate); |
861 | |
862 | set_high_bit_rate_capable(audio, capable: sample_rate.rate.RATE_192); |
863 | |
864 | /* Audio and Video Lipsync */ |
865 | set_video_latency(audio, latency_in_ms: audio_info->video_latency); |
866 | set_audio_latency(audio, latency_in_ms: audio_info->audio_latency); |
867 | |
868 | value = 0; |
869 | set_reg_field_value(value, audio_info->manufacture_id, |
870 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, |
871 | MANUFACTURER_ID); |
872 | |
873 | set_reg_field_value(value, audio_info->product_id, |
874 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, |
875 | PRODUCT_ID); |
876 | |
877 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, |
878 | value); |
879 | |
880 | value = 0; |
881 | |
882 | /*get display name string length */ |
883 | while (audio_info->display_name[strlen++] != '\0') { |
884 | if (strlen >= |
885 | MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) |
886 | break; |
887 | } |
888 | set_reg_field_value(value, strlen, |
889 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, |
890 | SINK_DESCRIPTION_LEN); |
891 | |
892 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, |
893 | value); |
894 | DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n" , |
895 | audio->inst, value, audio_info->display_name); |
896 | |
897 | /* |
898 | *write the port ID: |
899 | *PORT_ID0 = display index |
900 | *PORT_ID1 = 16bit BDF |
901 | *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) |
902 | */ |
903 | |
904 | value = 0; |
905 | |
906 | set_reg_field_value(value, audio_info->port_id[0], |
907 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, |
908 | PORT_ID0); |
909 | |
910 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); |
911 | |
912 | value = 0; |
913 | set_reg_field_value(value, audio_info->port_id[1], |
914 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, |
915 | PORT_ID1); |
916 | |
917 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); |
918 | |
919 | /*write the 18 char monitor string */ |
920 | |
921 | value = 0; |
922 | set_reg_field_value(value, audio_info->display_name[0], |
923 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, |
924 | DESCRIPTION0); |
925 | |
926 | set_reg_field_value(value, audio_info->display_name[1], |
927 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, |
928 | DESCRIPTION1); |
929 | |
930 | set_reg_field_value(value, audio_info->display_name[2], |
931 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, |
932 | DESCRIPTION2); |
933 | |
934 | set_reg_field_value(value, audio_info->display_name[3], |
935 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, |
936 | DESCRIPTION3); |
937 | |
938 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); |
939 | |
940 | value = 0; |
941 | set_reg_field_value(value, audio_info->display_name[4], |
942 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, |
943 | DESCRIPTION4); |
944 | |
945 | set_reg_field_value(value, audio_info->display_name[5], |
946 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, |
947 | DESCRIPTION5); |
948 | |
949 | set_reg_field_value(value, audio_info->display_name[6], |
950 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, |
951 | DESCRIPTION6); |
952 | |
953 | set_reg_field_value(value, audio_info->display_name[7], |
954 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, |
955 | DESCRIPTION7); |
956 | |
957 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); |
958 | |
959 | value = 0; |
960 | set_reg_field_value(value, audio_info->display_name[8], |
961 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, |
962 | DESCRIPTION8); |
963 | |
964 | set_reg_field_value(value, audio_info->display_name[9], |
965 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, |
966 | DESCRIPTION9); |
967 | |
968 | set_reg_field_value(value, audio_info->display_name[10], |
969 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, |
970 | DESCRIPTION10); |
971 | |
972 | set_reg_field_value(value, audio_info->display_name[11], |
973 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, |
974 | DESCRIPTION11); |
975 | |
976 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); |
977 | |
978 | value = 0; |
979 | set_reg_field_value(value, audio_info->display_name[12], |
980 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, |
981 | DESCRIPTION12); |
982 | |
983 | set_reg_field_value(value, audio_info->display_name[13], |
984 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, |
985 | DESCRIPTION13); |
986 | |
987 | set_reg_field_value(value, audio_info->display_name[14], |
988 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, |
989 | DESCRIPTION14); |
990 | |
991 | set_reg_field_value(value, audio_info->display_name[15], |
992 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, |
993 | DESCRIPTION15); |
994 | |
995 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); |
996 | |
997 | value = 0; |
998 | set_reg_field_value(value, audio_info->display_name[16], |
999 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, |
1000 | DESCRIPTION16); |
1001 | |
1002 | set_reg_field_value(value, audio_info->display_name[17], |
1003 | AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, |
1004 | DESCRIPTION17); |
1005 | |
1006 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); |
1007 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
1008 | set_reg_field_value(value, 0, |
1009 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
1010 | CLOCK_GATING_DISABLE); |
1011 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
1012 | } |
1013 | |
1014 | /* |
1015 | * todo: wall clk related functionality probably belong to clock_src. |
1016 | */ |
1017 | |
1018 | /* search pixel clock value for Azalia HDMI Audio */ |
1019 | static void get_azalia_clock_info_hdmi( |
1020 | uint32_t crtc_pixel_clock_100hz, |
1021 | uint32_t actual_pixel_clock_100Hz, |
1022 | struct azalia_clock_info *azalia_clock_info) |
1023 | { |
1024 | /* audio_dto_phase= 24 * 10,000; |
1025 | * 24MHz in [100Hz] units */ |
1026 | azalia_clock_info->audio_dto_phase = |
1027 | 24 * 10000; |
1028 | |
1029 | /* audio_dto_module = PCLKFrequency * 10,000; |
1030 | * [khz] -> [100Hz] */ |
1031 | azalia_clock_info->audio_dto_module = |
1032 | actual_pixel_clock_100Hz; |
1033 | } |
1034 | |
1035 | static void get_azalia_clock_info_dp( |
1036 | uint32_t requested_pixel_clock_100Hz, |
1037 | const struct audio_pll_info *pll_info, |
1038 | struct azalia_clock_info *azalia_clock_info) |
1039 | { |
1040 | /* Reported dpDtoSourceClockInkhz value for |
1041 | * DCE8 already adjusted for SS, do not need any |
1042 | * adjustment here anymore |
1043 | */ |
1044 | |
1045 | /*audio_dto_phase = 24 * 10,000; |
1046 | * 24MHz in [100Hz] units */ |
1047 | azalia_clock_info->audio_dto_phase = 24 * 10000; |
1048 | |
1049 | /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; |
1050 | * [khz] ->[100Hz] */ |
1051 | azalia_clock_info->audio_dto_module = |
1052 | pll_info->audio_dto_source_clock_in_khz * 10; |
1053 | } |
1054 | |
1055 | void dce_aud_wall_dto_setup( |
1056 | struct audio *audio, |
1057 | enum signal_type signal, |
1058 | const struct audio_crtc_info *crtc_info, |
1059 | const struct audio_pll_info *pll_info) |
1060 | { |
1061 | struct dce_audio *aud = DCE_AUD(audio); |
1062 | |
1063 | struct azalia_clock_info clock_info = { 0 }; |
1064 | |
1065 | if (dc_is_hdmi_tmds_signal(signal)) { |
1066 | uint32_t src_sel; |
1067 | |
1068 | /*DTO0 Programming goal: |
1069 | -generate 24MHz, 128*Fs from 24MHz |
1070 | -use DTO0 when an active HDMI port is connected |
1071 | (optionally a DP is connected) */ |
1072 | |
1073 | /* calculate DTO settings */ |
1074 | get_azalia_clock_info_hdmi( |
1075 | crtc_pixel_clock_100hz: crtc_info->requested_pixel_clock_100Hz, |
1076 | actual_pixel_clock_100Hz: crtc_info->calculated_pixel_clock_100Hz, |
1077 | azalia_clock_info: &clock_info); |
1078 | |
1079 | DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d" \ |
1080 | "calculated_pixel_clock_100Hz =%d\n" \ |
1081 | "audio_dto_module = %d audio_dto_phase =%d \n\n" , __func__,\ |
1082 | crtc_info->requested_pixel_clock_100Hz,\ |
1083 | crtc_info->calculated_pixel_clock_100Hz,\ |
1084 | clock_info.audio_dto_module,\ |
1085 | clock_info.audio_dto_phase); |
1086 | |
1087 | /* On TN/SI, Program DTO source select and DTO select before |
1088 | programming DTO modulo and DTO phase. These bits must be |
1089 | programmed first, otherwise there will be no HDMI audio at boot |
1090 | up. This is a HW sequence change (different from old ASICs). |
1091 | Caution when changing this programming sequence. |
1092 | |
1093 | HDMI enabled, using DTO0 |
1094 | program master CRTC for DTO0 */ |
1095 | src_sel = pll_info->dto_source - DTO_SOURCE_ID0; |
1096 | REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, |
1097 | DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, |
1098 | DCCG_AUDIO_DTO_SEL, 0); |
1099 | |
1100 | /* module */ |
1101 | REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, |
1102 | DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); |
1103 | |
1104 | /* phase */ |
1105 | REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, |
1106 | DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); |
1107 | } else { |
1108 | /*DTO1 Programming goal: |
1109 | -generate 24MHz, 512*Fs, 128*Fs from 24MHz |
1110 | -default is to used DTO1, and switch to DTO0 when an audio |
1111 | master HDMI port is connected |
1112 | -use as default for DP |
1113 | |
1114 | calculate DTO settings */ |
1115 | get_azalia_clock_info_dp( |
1116 | requested_pixel_clock_100Hz: crtc_info->requested_pixel_clock_100Hz, |
1117 | pll_info, |
1118 | azalia_clock_info: &clock_info); |
1119 | |
1120 | /* Program DTO select before programming DTO modulo and DTO |
1121 | phase. default to use DTO1 */ |
1122 | |
1123 | REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, |
1124 | DCCG_AUDIO_DTO_SEL, 1); |
1125 | |
1126 | /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) |
1127 | * Select 512fs for DP TODO: web register definition |
1128 | * does not match register header file |
1129 | * DCE11 version it's commented out while DCE8 it's set to 1 |
1130 | */ |
1131 | |
1132 | /* module */ |
1133 | REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, |
1134 | DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); |
1135 | |
1136 | /* phase */ |
1137 | REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, |
1138 | DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); |
1139 | |
1140 | REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, |
1141 | DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); |
1142 | |
1143 | } |
1144 | } |
1145 | |
1146 | #if defined(CONFIG_DRM_AMD_DC_SI) |
1147 | static void dce60_aud_wall_dto_setup( |
1148 | struct audio *audio, |
1149 | enum signal_type signal, |
1150 | const struct audio_crtc_info *crtc_info, |
1151 | const struct audio_pll_info *pll_info) |
1152 | { |
1153 | struct dce_audio *aud = DCE_AUD(audio); |
1154 | |
1155 | struct azalia_clock_info clock_info = { 0 }; |
1156 | |
1157 | if (dc_is_hdmi_signal(signal)) { |
1158 | uint32_t src_sel; |
1159 | |
1160 | /*DTO0 Programming goal: |
1161 | -generate 24MHz, 128*Fs from 24MHz |
1162 | -use DTO0 when an active HDMI port is connected |
1163 | (optionally a DP is connected) */ |
1164 | |
1165 | /* calculate DTO settings */ |
1166 | get_azalia_clock_info_hdmi( |
1167 | crtc_pixel_clock_100hz: crtc_info->requested_pixel_clock_100Hz, |
1168 | actual_pixel_clock_100Hz: crtc_info->calculated_pixel_clock_100Hz, |
1169 | azalia_clock_info: &clock_info); |
1170 | |
1171 | DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d" \ |
1172 | "calculated_pixel_clock_100Hz =%d\n" \ |
1173 | "audio_dto_module = %d audio_dto_phase =%d \n\n" , __func__,\ |
1174 | crtc_info->requested_pixel_clock_100Hz,\ |
1175 | crtc_info->calculated_pixel_clock_100Hz,\ |
1176 | clock_info.audio_dto_module,\ |
1177 | clock_info.audio_dto_phase); |
1178 | |
1179 | /* On TN/SI, Program DTO source select and DTO select before |
1180 | programming DTO modulo and DTO phase. These bits must be |
1181 | programmed first, otherwise there will be no HDMI audio at boot |
1182 | up. This is a HW sequence change (different from old ASICs). |
1183 | Caution when changing this programming sequence. |
1184 | |
1185 | HDMI enabled, using DTO0 |
1186 | program master CRTC for DTO0 */ |
1187 | src_sel = pll_info->dto_source - DTO_SOURCE_ID0; |
1188 | REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, |
1189 | DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, |
1190 | DCCG_AUDIO_DTO_SEL, 0); |
1191 | |
1192 | /* module */ |
1193 | REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, |
1194 | DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); |
1195 | |
1196 | /* phase */ |
1197 | REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, |
1198 | DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); |
1199 | } else { |
1200 | /*DTO1 Programming goal: |
1201 | -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs) |
1202 | -default is to used DTO1, and switch to DTO0 when an audio |
1203 | master HDMI port is connected |
1204 | -use as default for DP |
1205 | |
1206 | calculate DTO settings */ |
1207 | get_azalia_clock_info_dp( |
1208 | requested_pixel_clock_100Hz: crtc_info->requested_pixel_clock_100Hz, |
1209 | pll_info, |
1210 | azalia_clock_info: &clock_info); |
1211 | |
1212 | /* Program DTO select before programming DTO modulo and DTO |
1213 | phase. default to use DTO1 */ |
1214 | |
1215 | REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, |
1216 | DCCG_AUDIO_DTO_SEL, 1); |
1217 | |
1218 | /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) |
1219 | * Cannot select 512fs for DP |
1220 | * |
1221 | * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask |
1222 | */ |
1223 | |
1224 | /* module */ |
1225 | REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, |
1226 | DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); |
1227 | |
1228 | /* phase */ |
1229 | REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, |
1230 | DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); |
1231 | |
1232 | /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */ |
1233 | |
1234 | } |
1235 | } |
1236 | #endif |
1237 | |
1238 | static bool dce_aud_endpoint_valid(struct audio *audio) |
1239 | { |
1240 | uint32_t value; |
1241 | uint32_t port_connectivity; |
1242 | |
1243 | value = AZ_REG_READ( |
1244 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); |
1245 | |
1246 | port_connectivity = get_reg_field_value(value, |
1247 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, |
1248 | PORT_CONNECTIVITY); |
1249 | |
1250 | return !(port_connectivity == 1); |
1251 | } |
1252 | |
1253 | /* initialize HW state */ |
1254 | void dce_aud_hw_init( |
1255 | struct audio *audio) |
1256 | { |
1257 | uint32_t value; |
1258 | struct dce_audio *aud = DCE_AUD(audio); |
1259 | |
1260 | /* we only need to program the following registers once, so we only do |
1261 | it for the inst 0*/ |
1262 | if (audio->inst != 0) |
1263 | return; |
1264 | |
1265 | /* Suport R5 - 32khz |
1266 | * Suport R6 - 44.1khz |
1267 | * Suport R7 - 48khz |
1268 | */ |
1269 | /*disable clock gating before write to endpoint register*/ |
1270 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
1271 | set_reg_field_value(value, 1, |
1272 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
1273 | CLOCK_GATING_DISABLE); |
1274 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
1275 | REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, |
1276 | AUDIO_RATE_CAPABILITIES, 0x70); |
1277 | |
1278 | /*Keep alive bit to verify HW block in BU. */ |
1279 | REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, |
1280 | CLKSTOP, 1, |
1281 | EPSS, 1); |
1282 | set_reg_field_value(value, 0, |
1283 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
1284 | CLOCK_GATING_DISABLE); |
1285 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
1286 | } |
1287 | |
1288 | static const struct audio_funcs funcs = { |
1289 | .endpoint_valid = dce_aud_endpoint_valid, |
1290 | .hw_init = dce_aud_hw_init, |
1291 | .wall_dto_setup = dce_aud_wall_dto_setup, |
1292 | .az_enable = dce_aud_az_enable, |
1293 | .az_disable = dce_aud_az_disable, |
1294 | .az_configure = dce_aud_az_configure, |
1295 | .destroy = dce_aud_destroy, |
1296 | }; |
1297 | |
1298 | #if defined(CONFIG_DRM_AMD_DC_SI) |
1299 | static const struct audio_funcs dce60_funcs = { |
1300 | .endpoint_valid = dce_aud_endpoint_valid, |
1301 | .hw_init = dce_aud_hw_init, |
1302 | .wall_dto_setup = dce60_aud_wall_dto_setup, |
1303 | .az_enable = dce_aud_az_enable, |
1304 | .az_disable = dce_aud_az_disable, |
1305 | .az_configure = dce_aud_az_configure, |
1306 | .destroy = dce_aud_destroy, |
1307 | }; |
1308 | #endif |
1309 | |
1310 | void dce_aud_destroy(struct audio **audio) |
1311 | { |
1312 | struct dce_audio *aud = DCE_AUD(*audio); |
1313 | |
1314 | kfree(objp: aud); |
1315 | *audio = NULL; |
1316 | } |
1317 | |
1318 | struct audio *dce_audio_create( |
1319 | struct dc_context *ctx, |
1320 | unsigned int inst, |
1321 | const struct dce_audio_registers *reg, |
1322 | const struct dce_audio_shift *shifts, |
1323 | const struct dce_audio_mask *masks |
1324 | ) |
1325 | { |
1326 | struct dce_audio *audio = kzalloc(size: sizeof(*audio), GFP_KERNEL); |
1327 | |
1328 | if (audio == NULL) { |
1329 | ASSERT_CRITICAL(audio); |
1330 | return NULL; |
1331 | } |
1332 | |
1333 | audio->base.ctx = ctx; |
1334 | audio->base.inst = inst; |
1335 | audio->base.funcs = &funcs; |
1336 | |
1337 | audio->regs = reg; |
1338 | audio->shifts = shifts; |
1339 | audio->masks = masks; |
1340 | return &audio->base; |
1341 | } |
1342 | |
1343 | #if defined(CONFIG_DRM_AMD_DC_SI) |
1344 | struct audio *dce60_audio_create( |
1345 | struct dc_context *ctx, |
1346 | unsigned int inst, |
1347 | const struct dce_audio_registers *reg, |
1348 | const struct dce_audio_shift *shifts, |
1349 | const struct dce_audio_mask *masks |
1350 | ) |
1351 | { |
1352 | struct dce_audio *audio = kzalloc(size: sizeof(*audio), GFP_KERNEL); |
1353 | |
1354 | if (audio == NULL) { |
1355 | ASSERT_CRITICAL(audio); |
1356 | return NULL; |
1357 | } |
1358 | |
1359 | audio->base.ctx = ctx; |
1360 | audio->base.inst = inst; |
1361 | audio->base.funcs = &dce60_funcs; |
1362 | |
1363 | audio->regs = reg; |
1364 | audio->shifts = shifts; |
1365 | audio->masks = masks; |
1366 | return &audio->base; |
1367 | } |
1368 | #endif |
1369 | |