1 | /* |
2 | * Copyright 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef _DCE_IPP_H_ |
27 | #define _DCE_IPP_H_ |
28 | |
29 | #include "ipp.h" |
30 | |
31 | #define TO_DCE_IPP(ipp)\ |
32 | container_of(ipp, struct dce_ipp, base) |
33 | |
34 | #define IPP_COMMON_REG_LIST_DCE_BASE(id) \ |
35 | SRI(CUR_UPDATE, DCP, id), \ |
36 | SRI(CUR_CONTROL, DCP, id), \ |
37 | SRI(CUR_POSITION, DCP, id), \ |
38 | SRI(CUR_HOT_SPOT, DCP, id), \ |
39 | SRI(CUR_COLOR1, DCP, id), \ |
40 | SRI(CUR_COLOR2, DCP, id), \ |
41 | SRI(CUR_SIZE, DCP, id), \ |
42 | SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \ |
43 | SRI(CUR_SURFACE_ADDRESS, DCP, id), \ |
44 | SRI(PRESCALE_GRPH_CONTROL, DCP, id), \ |
45 | SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \ |
46 | SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \ |
47 | SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \ |
48 | SRI(INPUT_GAMMA_CONTROL, DCP, id), \ |
49 | SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \ |
50 | SRI(DC_LUT_RW_MODE, DCP, id), \ |
51 | SRI(DC_LUT_CONTROL, DCP, id), \ |
52 | SRI(DC_LUT_RW_INDEX, DCP, id), \ |
53 | SRI(DC_LUT_SEQ_COLOR, DCP, id), \ |
54 | SRI(DEGAMMA_CONTROL, DCP, id) |
55 | |
56 | #define IPP_DCE100_REG_LIST_DCE_BASE(id) \ |
57 | IPP_COMMON_REG_LIST_DCE_BASE(id), \ |
58 | SRI(DCFE_MEM_PWR_CTRL, CRTC, id) |
59 | |
60 | #define IPP_DCE110_REG_LIST_DCE_BASE(id) \ |
61 | IPP_COMMON_REG_LIST_DCE_BASE(id), \ |
62 | SRI(DCFE_MEM_PWR_CTRL, DCFE, id) |
63 | |
64 | #define IPP_SF(reg_name, field_name, post_fix)\ |
65 | .field_name = reg_name ## __ ## field_name ## post_fix |
66 | |
67 | #define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ |
68 | IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ |
69 | IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \ |
70 | IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \ |
71 | IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ |
72 | IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ |
73 | IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ |
74 | IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ |
75 | IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ |
76 | IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ |
77 | IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ |
78 | IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ |
79 | IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ |
80 | IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ |
81 | IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ |
82 | IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ |
83 | IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \ |
84 | IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ |
85 | IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ |
86 | IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ |
87 | IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ |
88 | IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ |
89 | IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ |
90 | IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ |
91 | IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ |
92 | IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ |
93 | IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ |
94 | IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ |
95 | IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ |
96 | IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ |
97 | IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ |
98 | IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ |
99 | IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ |
100 | IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ |
101 | IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ |
102 | IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ |
103 | IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ |
104 | IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) |
105 | |
106 | #define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ |
107 | IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ |
108 | IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh) |
109 | |
110 | #define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \ |
111 | IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ |
112 | IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \ |
113 | IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \ |
114 | IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ |
115 | IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ |
116 | IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ |
117 | IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ |
118 | IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ |
119 | IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ |
120 | IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ |
121 | IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ |
122 | IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ |
123 | IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ |
124 | IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ |
125 | IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ |
126 | IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \ |
127 | IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ |
128 | IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ |
129 | IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ |
130 | IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ |
131 | IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ |
132 | IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ |
133 | IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ |
134 | IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ |
135 | IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ |
136 | IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ |
137 | IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ |
138 | IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ |
139 | IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ |
140 | IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ |
141 | IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ |
142 | IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ |
143 | IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ |
144 | IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ |
145 | IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ |
146 | IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ |
147 | IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ |
148 | IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) |
149 | |
150 | #if defined(CONFIG_DRM_AMD_DC_SI) |
151 | #define IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ |
152 | IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ |
153 | IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \ |
154 | IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \ |
155 | IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ |
156 | IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \ |
157 | IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \ |
158 | IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \ |
159 | IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ |
160 | IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ |
161 | IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \ |
162 | IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \ |
163 | IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \ |
164 | IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \ |
165 | IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \ |
166 | IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \ |
167 | IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \ |
168 | IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \ |
169 | IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ |
170 | IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ |
171 | IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ |
172 | IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \ |
173 | IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \ |
174 | IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \ |
175 | IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \ |
176 | IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ |
177 | IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ |
178 | IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ |
179 | IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ |
180 | IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ |
181 | IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ |
182 | IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \ |
183 | IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \ |
184 | IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \ |
185 | IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \ |
186 | IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ |
187 | IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh) |
188 | #endif |
189 | |
190 | #define IPP_REG_FIELD_LIST(type) \ |
191 | type CURSOR_UPDATE_LOCK; \ |
192 | type CURSOR_EN; \ |
193 | type CURSOR_X_POSITION; \ |
194 | type CURSOR_Y_POSITION; \ |
195 | type CURSOR_HOT_SPOT_X; \ |
196 | type CURSOR_HOT_SPOT_Y; \ |
197 | type CURSOR_MODE; \ |
198 | type CURSOR_2X_MAGNIFY; \ |
199 | type CUR_INV_TRANS_CLAMP; \ |
200 | type CUR_COLOR1_BLUE; \ |
201 | type CUR_COLOR1_GREEN; \ |
202 | type CUR_COLOR1_RED; \ |
203 | type CUR_COLOR2_BLUE; \ |
204 | type CUR_COLOR2_GREEN; \ |
205 | type CUR_COLOR2_RED; \ |
206 | type CURSOR_WIDTH; \ |
207 | type CURSOR_HEIGHT; \ |
208 | type CURSOR_SURFACE_ADDRESS_HIGH; \ |
209 | type CURSOR_SURFACE_ADDRESS; \ |
210 | type GRPH_PRESCALE_BYPASS; \ |
211 | type GRPH_PRESCALE_SCALE_R; \ |
212 | type GRPH_PRESCALE_BIAS_R; \ |
213 | type GRPH_PRESCALE_SCALE_G; \ |
214 | type GRPH_PRESCALE_BIAS_G; \ |
215 | type GRPH_PRESCALE_SCALE_B; \ |
216 | type GRPH_PRESCALE_BIAS_B; \ |
217 | type GRPH_INPUT_GAMMA_MODE; \ |
218 | type DCP_LUT_MEM_PWR_DIS; \ |
219 | type DC_LUT_WRITE_EN_MASK; \ |
220 | type DC_LUT_RW_MODE; \ |
221 | type DC_LUT_DATA_R_FORMAT; \ |
222 | type DC_LUT_DATA_G_FORMAT; \ |
223 | type DC_LUT_DATA_B_FORMAT; \ |
224 | type DC_LUT_RW_INDEX; \ |
225 | type DC_LUT_SEQ_COLOR; \ |
226 | type GRPH_DEGAMMA_MODE; \ |
227 | type CURSOR_DEGAMMA_MODE; \ |
228 | type CURSOR2_DEGAMMA_MODE |
229 | |
230 | struct dce_ipp_shift { |
231 | IPP_REG_FIELD_LIST(uint8_t); |
232 | }; |
233 | |
234 | struct dce_ipp_mask { |
235 | IPP_REG_FIELD_LIST(uint32_t); |
236 | }; |
237 | |
238 | struct dce_ipp_registers { |
239 | uint32_t CUR_UPDATE; |
240 | uint32_t CUR_CONTROL; |
241 | uint32_t CUR_POSITION; |
242 | uint32_t CUR_HOT_SPOT; |
243 | uint32_t CUR_COLOR1; |
244 | uint32_t CUR_COLOR2; |
245 | uint32_t CUR_SIZE; |
246 | uint32_t CUR_SURFACE_ADDRESS_HIGH; |
247 | uint32_t CUR_SURFACE_ADDRESS; |
248 | uint32_t PRESCALE_GRPH_CONTROL; |
249 | uint32_t PRESCALE_VALUES_GRPH_R; |
250 | uint32_t PRESCALE_VALUES_GRPH_G; |
251 | uint32_t PRESCALE_VALUES_GRPH_B; |
252 | uint32_t INPUT_GAMMA_CONTROL; |
253 | uint32_t DCFE_MEM_PWR_CTRL; |
254 | uint32_t DC_LUT_WRITE_EN_MASK; |
255 | uint32_t DC_LUT_RW_MODE; |
256 | uint32_t DC_LUT_CONTROL; |
257 | uint32_t DC_LUT_RW_INDEX; |
258 | uint32_t DC_LUT_SEQ_COLOR; |
259 | uint32_t DEGAMMA_CONTROL; |
260 | }; |
261 | |
262 | struct dce_ipp { |
263 | struct input_pixel_processor base; |
264 | const struct dce_ipp_registers *regs; |
265 | const struct dce_ipp_shift *ipp_shift; |
266 | const struct dce_ipp_mask *ipp_mask; |
267 | }; |
268 | |
269 | void dce_ipp_construct(struct dce_ipp *ipp_dce, |
270 | struct dc_context *ctx, |
271 | int inst, |
272 | const struct dce_ipp_registers *regs, |
273 | const struct dce_ipp_shift *ipp_shift, |
274 | const struct dce_ipp_mask *ipp_mask); |
275 | |
276 | #if defined(CONFIG_DRM_AMD_DC_SI) |
277 | void dce60_ipp_construct(struct dce_ipp *ipp_dce, |
278 | struct dc_context *ctx, |
279 | int inst, |
280 | const struct dce_ipp_registers *regs, |
281 | const struct dce_ipp_shift *ipp_shift, |
282 | const struct dce_ipp_mask *ipp_mask); |
283 | #endif |
284 | |
285 | void dce_ipp_destroy(struct input_pixel_processor **ipp); |
286 | |
287 | #endif /* _DCE_IPP_H_ */ |
288 | |