1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | #ifndef __DCE_MEM_INPUT_H__ |
26 | #define __DCE_MEM_INPUT_H__ |
27 | |
28 | #include "dc_hw_types.h" |
29 | #include "mem_input.h" |
30 | |
31 | #define TO_DCE_MEM_INPUT(mem_input)\ |
32 | container_of(mem_input, struct dce_mem_input, base) |
33 | |
34 | #define MI_DCE_BASE_REG_LIST(id)\ |
35 | SRI(GRPH_ENABLE, DCP, id),\ |
36 | SRI(GRPH_CONTROL, DCP, id),\ |
37 | SRI(GRPH_X_START, DCP, id),\ |
38 | SRI(GRPH_Y_START, DCP, id),\ |
39 | SRI(GRPH_X_END, DCP, id),\ |
40 | SRI(GRPH_Y_END, DCP, id),\ |
41 | SRI(GRPH_PITCH, DCP, id),\ |
42 | SRI(HW_ROTATION, DCP, id),\ |
43 | SRI(GRPH_SWAP_CNTL, DCP, id),\ |
44 | SRI(PRESCALE_GRPH_CONTROL, DCP, id),\ |
45 | SRI(GRPH_UPDATE, DCP, id),\ |
46 | SRI(GRPH_FLIP_CONTROL, DCP, id),\ |
47 | SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\ |
48 | SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\ |
49 | SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\ |
50 | SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\ |
51 | SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\ |
52 | SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\ |
53 | SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\ |
54 | SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\ |
55 | SRI(DMIF_BUFFER_CONTROL, PIPE, id) |
56 | |
57 | #define MI_DCE_PTE_REG_LIST(id)\ |
58 | SRI(DVMM_PTE_CONTROL, DCP, id),\ |
59 | SRI(DVMM_PTE_ARB_CONTROL, DCP, id) |
60 | |
61 | #if defined(CONFIG_DRM_AMD_DC_SI) |
62 | #define MI_DCE6_REG_LIST(id)\ |
63 | SRI(GRPH_ENABLE, DCP, id),\ |
64 | SRI(GRPH_CONTROL, DCP, id),\ |
65 | SRI(GRPH_X_START, DCP, id),\ |
66 | SRI(GRPH_Y_START, DCP, id),\ |
67 | SRI(GRPH_X_END, DCP, id),\ |
68 | SRI(GRPH_Y_END, DCP, id),\ |
69 | SRI(GRPH_PITCH, DCP, id),\ |
70 | SRI(GRPH_SWAP_CNTL, DCP, id),\ |
71 | SRI(PRESCALE_GRPH_CONTROL, DCP, id),\ |
72 | SRI(GRPH_UPDATE, DCP, id),\ |
73 | SRI(GRPH_FLIP_CONTROL, DCP, id),\ |
74 | SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\ |
75 | SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\ |
76 | SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\ |
77 | SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\ |
78 | SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\ |
79 | SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\ |
80 | SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id),\ |
81 | SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\ |
82 | SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\ |
83 | SRI(DMIF_BUFFER_CONTROL, PIPE, id) |
84 | #endif |
85 | |
86 | #define MI_DCE8_REG_LIST(id)\ |
87 | MI_DCE_BASE_REG_LIST(id),\ |
88 | SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id) |
89 | |
90 | #define MI_DCE11_2_REG_LIST(id)\ |
91 | MI_DCE8_REG_LIST(id),\ |
92 | SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id) |
93 | |
94 | #define MI_DCE11_REG_LIST(id)\ |
95 | MI_DCE11_2_REG_LIST(id),\ |
96 | MI_DCE_PTE_REG_LIST(id) |
97 | |
98 | #define MI_DCE12_REG_LIST(id)\ |
99 | MI_DCE_BASE_REG_LIST(id),\ |
100 | MI_DCE_PTE_REG_LIST(id),\ |
101 | SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ |
102 | SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ |
103 | SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\ |
104 | SR(DCHUB_FB_LOCATION),\ |
105 | SR(DCHUB_AGP_BASE),\ |
106 | SR(DCHUB_AGP_BOT),\ |
107 | SR(DCHUB_AGP_TOP) |
108 | |
109 | struct dce_mem_input_registers { |
110 | /* DCP */ |
111 | uint32_t GRPH_ENABLE; |
112 | uint32_t GRPH_CONTROL; |
113 | uint32_t GRPH_X_START; |
114 | uint32_t GRPH_Y_START; |
115 | uint32_t GRPH_X_END; |
116 | uint32_t GRPH_Y_END; |
117 | uint32_t GRPH_PITCH; |
118 | uint32_t HW_ROTATION; |
119 | uint32_t GRPH_SWAP_CNTL; |
120 | uint32_t PRESCALE_GRPH_CONTROL; |
121 | uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; |
122 | uint32_t DVMM_PTE_CONTROL; |
123 | uint32_t DVMM_PTE_ARB_CONTROL; |
124 | uint32_t GRPH_UPDATE; |
125 | uint32_t GRPH_FLIP_CONTROL; |
126 | uint32_t GRPH_PRIMARY_SURFACE_ADDRESS; |
127 | uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; |
128 | uint32_t GRPH_SECONDARY_SURFACE_ADDRESS; |
129 | uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; |
130 | /* DMIF_PG */ |
131 | uint32_t DPG_PIPE_ARBITRATION_CONTROL1; |
132 | #if defined(CONFIG_DRM_AMD_DC_SI) |
133 | uint32_t DPG_PIPE_ARBITRATION_CONTROL3; |
134 | #endif |
135 | uint32_t DPG_WATERMARK_MASK_CONTROL; |
136 | uint32_t DPG_PIPE_URGENCY_CONTROL; |
137 | uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL; |
138 | uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL; |
139 | uint32_t DPG_PIPE_LOW_POWER_CONTROL; |
140 | uint32_t DPG_PIPE_STUTTER_CONTROL; |
141 | uint32_t DPG_PIPE_STUTTER_CONTROL2; |
142 | /* DCI */ |
143 | uint32_t DMIF_BUFFER_CONTROL; |
144 | /* MC_HUB */ |
145 | uint32_t MC_HUB_RDREQ_DMIF_LIMIT; |
146 | /*DCHUB*/ |
147 | uint32_t DCHUB_FB_LOCATION; |
148 | uint32_t DCHUB_AGP_BASE; |
149 | uint32_t DCHUB_AGP_BOT; |
150 | uint32_t DCHUB_AGP_TOP; |
151 | }; |
152 | |
153 | /* Set_Filed_for_Block */ |
154 | #define SFB(blk_name, reg_name, field_name, post_fix)\ |
155 | .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix |
156 | |
157 | #if defined(CONFIG_DRM_AMD_DC_SI) |
158 | #define MI_GFX6_TILE_MASK_SH_LIST(mask_sh, blk)\ |
159 | SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ |
160 | SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\ |
161 | SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\ |
162 | SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\ |
163 | SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\ |
164 | SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\ |
165 | SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\ |
166 | SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) |
167 | #endif |
168 | |
169 | #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\ |
170 | SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ |
171 | SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\ |
172 | SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\ |
173 | SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\ |
174 | SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\ |
175 | SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\ |
176 | SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\ |
177 | SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\ |
178 | SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) |
179 | |
180 | #define MI_DCP_MASK_SH_LIST(mask_sh, blk)\ |
181 | SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\ |
182 | SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\ |
183 | SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\ |
184 | SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\ |
185 | SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\ |
186 | SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\ |
187 | SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\ |
188 | SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\ |
189 | SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\ |
190 | SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\ |
191 | SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\ |
192 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\ |
193 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\ |
194 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ |
195 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\ |
196 | SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ |
197 | SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\ |
198 | SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ |
199 | SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\ |
200 | SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\ |
201 | SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\ |
202 | SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh) |
203 | |
204 | #if defined(CONFIG_DRM_AMD_DC_SI) |
205 | #define MI_DCP_MASK_SH_LIST_DCE6(mask_sh, blk)\ |
206 | SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\ |
207 | SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\ |
208 | SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\ |
209 | SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\ |
210 | SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\ |
211 | SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\ |
212 | SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\ |
213 | SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\ |
214 | SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\ |
215 | SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\ |
216 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\ |
217 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\ |
218 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ |
219 | SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\ |
220 | SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ |
221 | SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\ |
222 | SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ |
223 | SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\ |
224 | SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\ |
225 | SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\ |
226 | SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh) |
227 | #endif |
228 | |
229 | #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\ |
230 | SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh) |
231 | |
232 | #define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\ |
233 | SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\ |
234 | SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\ |
235 | SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\ |
236 | SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\ |
237 | SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh) |
238 | |
239 | #if defined(CONFIG_DRM_AMD_DC_SI) |
240 | #define MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, blk)\ |
241 | SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\ |
242 | SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ |
243 | SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ |
244 | SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\ |
245 | SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\ |
246 | SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\ |
247 | SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh) |
248 | |
249 | #define MI_DMIF_PG_MASK_SH_DCE6(mask_sh, blk)\ |
250 | SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\ |
251 | SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\ |
252 | SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ |
253 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ |
254 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\ |
255 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ |
256 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ |
257 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh) |
258 | |
259 | #define MI_DCE6_MASK_SH_LIST(mask_sh)\ |
260 | MI_DCP_MASK_SH_LIST_DCE6(mask_sh, ),\ |
261 | MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, ),\ |
262 | MI_DMIF_PG_MASK_SH_DCE6(mask_sh, ),\ |
263 | MI_GFX6_TILE_MASK_SH_LIST(mask_sh, ) |
264 | #endif |
265 | |
266 | #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ |
267 | SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\ |
268 | SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\ |
269 | SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\ |
270 | SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ |
271 | SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ |
272 | SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\ |
273 | SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\ |
274 | SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\ |
275 | SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh) |
276 | |
277 | #define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk)\ |
278 | SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ |
279 | SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ |
280 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\ |
281 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ |
282 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ |
283 | SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh) |
284 | |
285 | #define MI_DCE8_MASK_SH_LIST(mask_sh)\ |
286 | MI_DCP_MASK_SH_LIST(mask_sh, ),\ |
287 | MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\ |
288 | MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\ |
289 | MI_GFX8_TILE_MASK_SH_LIST(mask_sh, ) |
290 | |
291 | #define MI_DCE11_2_MASK_SH_LIST(mask_sh)\ |
292 | MI_DCE8_MASK_SH_LIST(mask_sh),\ |
293 | MI_DCP_DCE11_MASK_SH_LIST(mask_sh, ) |
294 | |
295 | #define MI_DCE11_MASK_SH_LIST(mask_sh)\ |
296 | MI_DCE11_2_MASK_SH_LIST(mask_sh),\ |
297 | MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) |
298 | |
299 | #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ |
300 | SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ |
301 | SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ |
302 | SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ |
303 | SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ |
304 | SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\ |
305 | SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) |
306 | |
307 | #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ |
308 | SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ |
309 | SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\ |
310 | SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\ |
311 | SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\ |
312 | SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ |
313 | SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ |
314 | SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ |
315 | SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ |
316 | SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ |
317 | SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ |
318 | SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh) |
319 | |
320 | #define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ |
321 | SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ |
322 | SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ |
323 | SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ |
324 | SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ |
325 | SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) |
326 | |
327 | #define MI_DCE12_MASK_SH_LIST(mask_sh)\ |
328 | MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\ |
329 | SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\ |
330 | MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\ |
331 | MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\ |
332 | MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ |
333 | MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ |
334 | MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\ |
335 | MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh) |
336 | |
337 | #define MI_REG_FIELD_LIST(type) \ |
338 | type GRPH_ENABLE; \ |
339 | type GRPH_X_START; \ |
340 | type GRPH_Y_START; \ |
341 | type GRPH_X_END; \ |
342 | type GRPH_Y_END; \ |
343 | type GRPH_PITCH; \ |
344 | type GRPH_ROTATION_ANGLE; \ |
345 | type GRPH_RED_CROSSBAR; \ |
346 | type GRPH_BLUE_CROSSBAR; \ |
347 | type GRPH_PRESCALE_SELECT; \ |
348 | type GRPH_PRESCALE_R_SIGN; \ |
349 | type GRPH_PRESCALE_G_SIGN; \ |
350 | type GRPH_PRESCALE_B_SIGN; \ |
351 | type GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; \ |
352 | type DVMM_PAGE_WIDTH; \ |
353 | type DVMM_PAGE_HEIGHT; \ |
354 | type DVMM_MIN_PTE_BEFORE_FLIP; \ |
355 | type DVMM_PTE_REQ_PER_CHUNK; \ |
356 | type DVMM_MAX_PTE_REQ_OUTSTANDING; \ |
357 | type GRPH_DEPTH; \ |
358 | type GRPH_FORMAT; \ |
359 | type GRPH_NUM_BANKS; \ |
360 | type GRPH_BANK_WIDTH;\ |
361 | type GRPH_BANK_HEIGHT;\ |
362 | type GRPH_MACRO_TILE_ASPECT;\ |
363 | type GRPH_TILE_SPLIT;\ |
364 | type GRPH_MICRO_TILE_MODE;\ |
365 | type GRPH_PIPE_CONFIG;\ |
366 | type GRPH_ARRAY_MODE;\ |
367 | type GRPH_COLOR_EXPANSION_MODE;\ |
368 | type GRPH_SW_MODE; \ |
369 | type GRPH_SE_ENABLE; \ |
370 | type GRPH_NUM_SHADER_ENGINES; \ |
371 | type GRPH_NUM_PIPES; \ |
372 | type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \ |
373 | type GRPH_SECONDARY_SURFACE_ADDRESS; \ |
374 | type GRPH_SECONDARY_DFQ_ENABLE; \ |
375 | type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \ |
376 | type GRPH_PRIMARY_SURFACE_ADDRESS; \ |
377 | type GRPH_SURFACE_UPDATE_PENDING; \ |
378 | type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \ |
379 | type GRPH_UPDATE_LOCK; \ |
380 | type PIXEL_DURATION; \ |
381 | type URGENCY_WATERMARK_MASK; \ |
382 | type PSTATE_CHANGE_WATERMARK_MASK; \ |
383 | type NB_PSTATE_CHANGE_WATERMARK_MASK; \ |
384 | type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \ |
385 | type URGENCY_LOW_WATERMARK; \ |
386 | type URGENCY_HIGH_WATERMARK; \ |
387 | type URGENT_LEVEL_LOW_WATERMARK;\ |
388 | type URGENT_LEVEL_HIGH_WATERMARK;\ |
389 | type NB_PSTATE_CHANGE_ENABLE; \ |
390 | type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \ |
391 | type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \ |
392 | type NB_PSTATE_CHANGE_WATERMARK; \ |
393 | type PSTATE_CHANGE_ENABLE; \ |
394 | type PSTATE_CHANGE_URGENT_DURING_REQUEST; \ |
395 | type PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \ |
396 | type PSTATE_CHANGE_WATERMARK; \ |
397 | type STUTTER_ENABLE; \ |
398 | type STUTTER_IGNORE_FBC; \ |
399 | type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \ |
400 | type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \ |
401 | type DMIF_BUFFERS_ALLOCATED; \ |
402 | type DMIF_BUFFERS_ALLOCATION_COMPLETED; \ |
403 | type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\ |
404 | type FB_BASE; \ |
405 | type FB_TOP; \ |
406 | type AGP_BASE; \ |
407 | type AGP_TOP; \ |
408 | type AGP_BOT; \ |
409 | |
410 | struct dce_mem_input_shift { |
411 | MI_REG_FIELD_LIST(uint8_t) |
412 | }; |
413 | |
414 | struct dce_mem_input_mask { |
415 | MI_REG_FIELD_LIST(uint32_t) |
416 | }; |
417 | |
418 | struct dce_mem_input_wa { |
419 | uint8_t single_head_rdreq_dmif_limit; |
420 | }; |
421 | |
422 | struct dce_mem_input { |
423 | struct mem_input base; |
424 | |
425 | const struct dce_mem_input_registers *regs; |
426 | const struct dce_mem_input_shift *shifts; |
427 | const struct dce_mem_input_mask *masks; |
428 | |
429 | struct dce_mem_input_wa wa; |
430 | }; |
431 | |
432 | void dce_mem_input_construct( |
433 | struct dce_mem_input *dce_mi, |
434 | struct dc_context *ctx, |
435 | int inst, |
436 | const struct dce_mem_input_registers *regs, |
437 | const struct dce_mem_input_shift *mi_shift, |
438 | const struct dce_mem_input_mask *mi_mask); |
439 | |
440 | #if defined(CONFIG_DRM_AMD_DC_SI) |
441 | void dce60_mem_input_construct( |
442 | struct dce_mem_input *dce_mi, |
443 | struct dc_context *ctx, |
444 | int inst, |
445 | const struct dce_mem_input_registers *regs, |
446 | const struct dce_mem_input_shift *mi_shift, |
447 | const struct dce_mem_input_mask *mi_mask); |
448 | #endif |
449 | |
450 | void dce112_mem_input_construct( |
451 | struct dce_mem_input *dce_mi, |
452 | struct dc_context *ctx, |
453 | int inst, |
454 | const struct dce_mem_input_registers *regs, |
455 | const struct dce_mem_input_shift *mi_shift, |
456 | const struct dce_mem_input_mask *mi_mask); |
457 | |
458 | void dce120_mem_input_construct( |
459 | struct dce_mem_input *dce_mi, |
460 | struct dc_context *ctx, |
461 | int inst, |
462 | const struct dce_mem_input_registers *regs, |
463 | const struct dce_mem_input_shift *mi_shift, |
464 | const struct dce_mem_input_mask *mi_mask); |
465 | |
466 | #endif /*__DCE_MEM_INPUT_H__*/ |
467 | |