1 | /* Copyright 2012-15 Advanced Micro Devices, Inc. |
2 | * |
3 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * copy of this software and associated documentation files (the "Software"), |
5 | * to deal in the Software without restriction, including without limitation |
6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * Software is furnished to do so, subject to the following conditions: |
9 | * |
10 | * The above copyright notice and this permission notice shall be included in |
11 | * all copies or substantial portions of the Software. |
12 | * |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * |
21 | * Authors: AMD |
22 | * |
23 | */ |
24 | |
25 | #ifndef __DC_MEM_INPUT_DCN10_H__ |
26 | #define __DC_MEM_INPUT_DCN10_H__ |
27 | |
28 | #include "hubp.h" |
29 | |
30 | #define TO_DCN10_HUBP(hubp)\ |
31 | container_of(hubp, struct dcn10_hubp, base) |
32 | |
33 | /* Register address initialization macro for all ASICs (including those with reduced functionality) */ |
34 | #define HUBP_REG_LIST_DCN(id)\ |
35 | SRI(DCHUBP_CNTL, HUBP, id),\ |
36 | SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ |
37 | SRI(HUBPREQ_DEBUG, HUBP, id),\ |
38 | SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ |
39 | SRI(DCSURF_TILING_CONFIG, HUBP, id),\ |
40 | SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ |
41 | SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ |
42 | SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ |
43 | SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ |
44 | SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ |
45 | SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ |
46 | SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ |
47 | SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ |
48 | SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ |
49 | SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ |
50 | SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \ |
51 | SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \ |
52 | SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ |
53 | SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\ |
54 | SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ |
55 | SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\ |
56 | SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ |
57 | SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ |
58 | SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ |
59 | SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ |
60 | SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ |
61 | SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\ |
62 | SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ |
63 | SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\ |
64 | SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ |
65 | SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\ |
66 | SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ |
67 | SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\ |
68 | SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\ |
69 | SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\ |
70 | SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\ |
71 | SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\ |
72 | SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\ |
73 | SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\ |
74 | SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\ |
75 | SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\ |
76 | SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\ |
77 | SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\ |
78 | SRI(HUBPRET_CONTROL, HUBPRET, id),\ |
79 | SRI(HUBPRET_READ_LINE_STATUS, HUBPRET, id),\ |
80 | SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\ |
81 | SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\ |
82 | SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\ |
83 | SRI(BLANK_OFFSET_0, HUBPREQ, id),\ |
84 | SRI(BLANK_OFFSET_1, HUBPREQ, id),\ |
85 | SRI(DST_DIMENSIONS, HUBPREQ, id),\ |
86 | SRI(DST_AFTER_SCALER, HUBPREQ, id),\ |
87 | SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\ |
88 | SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\ |
89 | SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\ |
90 | SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\ |
91 | SRI(NOM_PARAMETERS_4, HUBPREQ, id),\ |
92 | SRI(NOM_PARAMETERS_5, HUBPREQ, id),\ |
93 | SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\ |
94 | SRI(PER_LINE_DELIVERY, HUBPREQ, id),\ |
95 | SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\ |
96 | SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\ |
97 | SRI(NOM_PARAMETERS_6, HUBPREQ, id),\ |
98 | SRI(NOM_PARAMETERS_7, HUBPREQ, id),\ |
99 | SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\ |
100 | SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\ |
101 | SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\ |
102 | SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ |
103 | SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ |
104 | SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ |
105 | SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ |
106 | SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ |
107 | SRI(HUBP_CLK_CNTL, HUBP, id) |
108 | |
109 | /* Register address initialization macro for ASICs with VM */ |
110 | #define HUBP_REG_LIST_DCN_VM(id)\ |
111 | SRI(NOM_PARAMETERS_0, HUBPREQ, id),\ |
112 | SRI(NOM_PARAMETERS_1, HUBPREQ, id),\ |
113 | SRI(NOM_PARAMETERS_2, HUBPREQ, id),\ |
114 | SRI(NOM_PARAMETERS_3, HUBPREQ, id),\ |
115 | SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) |
116 | |
117 | #define HUBP_REG_LIST_DCN10(id)\ |
118 | HUBP_REG_LIST_DCN(id),\ |
119 | HUBP_REG_LIST_DCN_VM(id),\ |
120 | SRI(PREFETCH_SETTINS, HUBPREQ, id),\ |
121 | SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\ |
122 | SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ |
123 | SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\ |
124 | SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\ |
125 | SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\ |
126 | SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\ |
127 | SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\ |
128 | SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\ |
129 | SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\ |
130 | SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\ |
131 | SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\ |
132 | SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\ |
133 | SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ |
134 | SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ |
135 | SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ |
136 | SRI(CURSOR_SETTINS, HUBPREQ, id), \ |
137 | SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ |
138 | SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ |
139 | SRI(CURSOR_SIZE, CURSOR, id), \ |
140 | SRI(CURSOR_CONTROL, CURSOR, id), \ |
141 | SRI(CURSOR_POSITION, CURSOR, id), \ |
142 | SRI(CURSOR_HOT_SPOT, CURSOR, id), \ |
143 | SRI(CURSOR_DST_OFFSET, CURSOR, id) |
144 | |
145 | #define HUBP_COMMON_REG_VARIABLE_LIST \ |
146 | uint32_t DCHUBP_CNTL; \ |
147 | uint32_t HUBPREQ_DEBUG_DB; \ |
148 | uint32_t HUBPREQ_DEBUG; \ |
149 | uint32_t DCSURF_ADDR_CONFIG; \ |
150 | uint32_t DCSURF_TILING_CONFIG; \ |
151 | uint32_t DCSURF_SURFACE_PITCH; \ |
152 | uint32_t DCSURF_SURFACE_PITCH_C; \ |
153 | uint32_t DCSURF_SURFACE_CONFIG; \ |
154 | uint32_t DCSURF_FLIP_CONTROL; \ |
155 | uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \ |
156 | uint32_t DCSURF_PRI_VIEWPORT_START; \ |
157 | uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \ |
158 | uint32_t DCSURF_SEC_VIEWPORT_START; \ |
159 | uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \ |
160 | uint32_t DCSURF_PRI_VIEWPORT_START_C; \ |
161 | uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \ |
162 | uint32_t DCSURF_SEC_VIEWPORT_START_C; \ |
163 | uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \ |
164 | uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \ |
165 | uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \ |
166 | uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \ |
167 | uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \ |
168 | uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \ |
169 | uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \ |
170 | uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \ |
171 | uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \ |
172 | uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \ |
173 | uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \ |
174 | uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \ |
175 | uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \ |
176 | uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \ |
177 | uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \ |
178 | uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \ |
179 | uint32_t DCSURF_SURFACE_INUSE; \ |
180 | uint32_t DCSURF_SURFACE_INUSE_HIGH; \ |
181 | uint32_t DCSURF_SURFACE_INUSE_C; \ |
182 | uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \ |
183 | uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \ |
184 | uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \ |
185 | uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \ |
186 | uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \ |
187 | uint32_t DCSURF_SURFACE_CONTROL; \ |
188 | uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \ |
189 | uint32_t HUBPRET_CONTROL; \ |
190 | uint32_t HUBPRET_READ_LINE_STATUS; \ |
191 | uint32_t DCN_EXPANSION_MODE; \ |
192 | uint32_t DCHUBP_REQ_SIZE_CONFIG; \ |
193 | uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \ |
194 | uint32_t BLANK_OFFSET_0; \ |
195 | uint32_t BLANK_OFFSET_1; \ |
196 | uint32_t DST_DIMENSIONS; \ |
197 | uint32_t DST_AFTER_SCALER; \ |
198 | uint32_t PREFETCH_SETTINS; \ |
199 | uint32_t PREFETCH_SETTINGS; \ |
200 | uint32_t VBLANK_PARAMETERS_0; \ |
201 | uint32_t REF_FREQ_TO_PIX_FREQ; \ |
202 | uint32_t VBLANK_PARAMETERS_1; \ |
203 | uint32_t VBLANK_PARAMETERS_3; \ |
204 | uint32_t NOM_PARAMETERS_0; \ |
205 | uint32_t NOM_PARAMETERS_1; \ |
206 | uint32_t NOM_PARAMETERS_4; \ |
207 | uint32_t NOM_PARAMETERS_5; \ |
208 | uint32_t PER_LINE_DELIVERY_PRE; \ |
209 | uint32_t PER_LINE_DELIVERY; \ |
210 | uint32_t PREFETCH_SETTINS_C; \ |
211 | uint32_t PREFETCH_SETTINGS_C; \ |
212 | uint32_t VBLANK_PARAMETERS_2; \ |
213 | uint32_t VBLANK_PARAMETERS_4; \ |
214 | uint32_t NOM_PARAMETERS_2; \ |
215 | uint32_t NOM_PARAMETERS_3; \ |
216 | uint32_t NOM_PARAMETERS_6; \ |
217 | uint32_t NOM_PARAMETERS_7; \ |
218 | uint32_t DCN_TTU_QOS_WM; \ |
219 | uint32_t DCN_GLOBAL_TTU_CNTL; \ |
220 | uint32_t DCN_SURF0_TTU_CNTL0; \ |
221 | uint32_t DCN_SURF0_TTU_CNTL1; \ |
222 | uint32_t DCN_SURF1_TTU_CNTL0; \ |
223 | uint32_t DCN_SURF1_TTU_CNTL1; \ |
224 | uint32_t DCN_CUR0_TTU_CNTL0; \ |
225 | uint32_t DCN_CUR0_TTU_CNTL1; \ |
226 | uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \ |
227 | uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \ |
228 | uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \ |
229 | uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \ |
230 | uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \ |
231 | uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \ |
232 | uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \ |
233 | uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \ |
234 | uint32_t DCN_VM_MX_L1_TLB_CNTL; \ |
235 | uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \ |
236 | uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \ |
237 | uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \ |
238 | uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \ |
239 | uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \ |
240 | uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \ |
241 | uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \ |
242 | uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \ |
243 | uint32_t CURSOR_SETTINS; \ |
244 | uint32_t CURSOR_SETTINGS; \ |
245 | uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \ |
246 | uint32_t CURSOR_SURFACE_ADDRESS; \ |
247 | uint32_t CURSOR_SIZE; \ |
248 | uint32_t CURSOR_CONTROL; \ |
249 | uint32_t CURSOR_POSITION; \ |
250 | uint32_t CURSOR_HOT_SPOT; \ |
251 | uint32_t CURSOR_DST_OFFSET; \ |
252 | uint32_t HUBP_CLK_CNTL |
253 | |
254 | #define HUBP_SF(reg_name, field_name, post_fix)\ |
255 | .field_name = reg_name ## __ ## field_name ## post_fix |
256 | |
257 | /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */ |
258 | /*1.x, 2.x, and 3.x*/ |
259 | #define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\ |
260 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ |
261 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ |
262 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ |
263 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\ |
264 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ |
265 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ |
266 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\ |
267 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\ |
268 | HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ |
269 | HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ |
270 | HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ |
271 | HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ |
272 | HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ |
273 | HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ |
274 | HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ |
275 | HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ |
276 | HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ |
277 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ |
278 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ |
279 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ |
280 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ |
281 | HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ |
282 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ |
283 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\ |
284 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\ |
285 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ |
286 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ |
287 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ |
288 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ |
289 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ |
290 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ |
291 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ |
292 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ |
293 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ |
294 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ |
295 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ |
296 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ |
297 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ |
298 | HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ |
299 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\ |
300 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\ |
301 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\ |
302 | HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\ |
303 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ |
304 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ |
305 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ |
306 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ |
307 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ |
308 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ |
309 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ |
310 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ |
311 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ |
312 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ |
313 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ |
314 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\ |
315 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ |
316 | HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ |
317 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ |
318 | HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\ |
319 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ |
320 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ |
321 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ |
322 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ |
323 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ |
324 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ |
325 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ |
326 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ |
327 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ |
328 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\ |
329 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\ |
330 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\ |
331 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ |
332 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ |
333 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\ |
334 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\ |
335 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\ |
336 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ |
337 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ |
338 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ |
339 | HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\ |
340 | HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ |
341 | HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ |
342 | HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ |
343 | HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_STATUS, PIPE_READ_VBLANK, mask_sh),\ |
344 | HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ |
345 | HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ |
346 | HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ |
347 | HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ |
348 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ |
349 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ |
350 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ |
351 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ |
352 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ |
353 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ |
354 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ |
355 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ |
356 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ |
357 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ |
358 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ |
359 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ |
360 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ |
361 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ |
362 | HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ |
363 | HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ |
364 | HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ |
365 | HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ |
366 | HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ |
367 | HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ |
368 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ |
369 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ |
370 | HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ |
371 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ |
372 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ |
373 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ |
374 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ |
375 | HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ |
376 | HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ |
377 | HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ |
378 | HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ |
379 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ |
380 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ |
381 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ |
382 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ |
383 | HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ |
384 | HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ |
385 | HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ |
386 | HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ |
387 | HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ |
388 | HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ |
389 | HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ |
390 | HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ |
391 | HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) |
392 | /*2.x and 1.x only*/ |
393 | #define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ |
394 | HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ |
395 | HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ |
396 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ |
397 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) |
398 | |
399 | /*2.x and 1.x only*/ |
400 | #define HUBP_MASK_SH_LIST_DCN(mask_sh)\ |
401 | HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh) |
402 | |
403 | /* Mask/shift struct generation macro for ASICs with VM */ |
404 | #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ |
405 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ |
406 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ |
407 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ |
408 | HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ |
409 | HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ |
410 | HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ |
411 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ |
412 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ |
413 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ |
414 | HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) |
415 | |
416 | #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ |
417 | HUBP_MASK_SH_LIST_DCN(mask_sh),\ |
418 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ |
419 | HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ |
420 | HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ |
421 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ |
422 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ |
423 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ |
424 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ |
425 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ |
426 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ |
427 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ |
428 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ |
429 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ |
430 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ |
431 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ |
432 | HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ |
433 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ |
434 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ |
435 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ |
436 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ |
437 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ |
438 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ |
439 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ |
440 | HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ |
441 | HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ |
442 | HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ |
443 | HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ |
444 | HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ |
445 | HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ |
446 | HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ |
447 | HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ |
448 | HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ |
449 | HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ |
450 | HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ |
451 | HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ |
452 | HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ |
453 | HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ |
454 | HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ |
455 | HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) |
456 | |
457 | #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ |
458 | type HUBP_BLANK_EN;\ |
459 | type HUBP_DISABLE;\ |
460 | type HUBP_TTU_DISABLE;\ |
461 | type HUBP_NO_OUTSTANDING_REQ;\ |
462 | type HUBP_VTG_SEL;\ |
463 | type HUBP_UNDERFLOW_STATUS;\ |
464 | type HUBP_UNDERFLOW_CLEAR;\ |
465 | type HUBP_IN_BLANK;\ |
466 | type NUM_PIPES;\ |
467 | type NUM_BANKS;\ |
468 | type PIPE_INTERLEAVE;\ |
469 | type NUM_SE;\ |
470 | type NUM_RB_PER_SE;\ |
471 | type MAX_COMPRESSED_FRAGS;\ |
472 | type SW_MODE;\ |
473 | type META_LINEAR;\ |
474 | type RB_ALIGNED;\ |
475 | type PIPE_ALIGNED;\ |
476 | type PITCH;\ |
477 | type META_PITCH;\ |
478 | type PITCH_C;\ |
479 | type META_PITCH_C;\ |
480 | type ROTATION_ANGLE;\ |
481 | type H_MIRROR_EN;\ |
482 | type SURFACE_PIXEL_FORMAT;\ |
483 | type SURFACE_FLIP_TYPE;\ |
484 | type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\ |
485 | type SURFACE_FLIP_IN_STEREOSYNC;\ |
486 | type SURFACE_UPDATE_LOCK;\ |
487 | type SURFACE_FLIP_PENDING;\ |
488 | type PRI_VIEWPORT_WIDTH; \ |
489 | type PRI_VIEWPORT_HEIGHT; \ |
490 | type PRI_VIEWPORT_X_START; \ |
491 | type PRI_VIEWPORT_Y_START; \ |
492 | type SEC_VIEWPORT_WIDTH; \ |
493 | type SEC_VIEWPORT_HEIGHT; \ |
494 | type SEC_VIEWPORT_X_START; \ |
495 | type SEC_VIEWPORT_Y_START; \ |
496 | type PRI_VIEWPORT_WIDTH_C; \ |
497 | type PRI_VIEWPORT_HEIGHT_C; \ |
498 | type PRI_VIEWPORT_X_START_C; \ |
499 | type PRI_VIEWPORT_Y_START_C; \ |
500 | type SEC_VIEWPORT_WIDTH_C; \ |
501 | type SEC_VIEWPORT_HEIGHT_C; \ |
502 | type SEC_VIEWPORT_X_START_C; \ |
503 | type SEC_VIEWPORT_Y_START_C; \ |
504 | type PRIMARY_SURFACE_ADDRESS_HIGH;\ |
505 | type PRIMARY_SURFACE_ADDRESS;\ |
506 | type SECONDARY_SURFACE_ADDRESS_HIGH;\ |
507 | type SECONDARY_SURFACE_ADDRESS;\ |
508 | type PRIMARY_META_SURFACE_ADDRESS_HIGH;\ |
509 | type PRIMARY_META_SURFACE_ADDRESS;\ |
510 | type SECONDARY_META_SURFACE_ADDRESS_HIGH;\ |
511 | type SECONDARY_META_SURFACE_ADDRESS;\ |
512 | type PRIMARY_SURFACE_ADDRESS_HIGH_C;\ |
513 | type PRIMARY_SURFACE_ADDRESS_C;\ |
514 | type SECONDARY_SURFACE_ADDRESS_HIGH_C;\ |
515 | type SECONDARY_SURFACE_ADDRESS_C;\ |
516 | type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\ |
517 | type PRIMARY_META_SURFACE_ADDRESS_C;\ |
518 | type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\ |
519 | type SECONDARY_META_SURFACE_ADDRESS_C;\ |
520 | type SURFACE_INUSE_ADDRESS;\ |
521 | type SURFACE_INUSE_ADDRESS_HIGH;\ |
522 | type SURFACE_INUSE_ADDRESS_C;\ |
523 | type SURFACE_INUSE_ADDRESS_HIGH_C;\ |
524 | type SURFACE_EARLIEST_INUSE_ADDRESS;\ |
525 | type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\ |
526 | type SURFACE_EARLIEST_INUSE_ADDRESS_C;\ |
527 | type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\ |
528 | type PRIMARY_SURFACE_TMZ;\ |
529 | type PRIMARY_SURFACE_TMZ_C;\ |
530 | type SECONDARY_SURFACE_TMZ;\ |
531 | type SECONDARY_SURFACE_TMZ_C;\ |
532 | type PRIMARY_META_SURFACE_TMZ;\ |
533 | type PRIMARY_META_SURFACE_TMZ_C;\ |
534 | type SECONDARY_META_SURFACE_TMZ;\ |
535 | type SECONDARY_META_SURFACE_TMZ_C;\ |
536 | type PRIMARY_SURFACE_DCC_EN;\ |
537 | type PRIMARY_SURFACE_DCC_IND_64B_BLK;\ |
538 | type SECONDARY_SURFACE_DCC_EN;\ |
539 | type SECONDARY_SURFACE_DCC_IND_64B_BLK;\ |
540 | type SURFACE_FLIP_INT_MASK;\ |
541 | type DET_BUF_PLANE1_BASE_ADDRESS;\ |
542 | type CROSSBAR_SRC_CB_B;\ |
543 | type CROSSBAR_SRC_CR_R;\ |
544 | type PIPE_READ_VBLANK;\ |
545 | type DRQ_EXPANSION_MODE;\ |
546 | type PRQ_EXPANSION_MODE;\ |
547 | type MRQ_EXPANSION_MODE;\ |
548 | type CRQ_EXPANSION_MODE;\ |
549 | type CHUNK_SIZE;\ |
550 | type MIN_CHUNK_SIZE;\ |
551 | type META_CHUNK_SIZE;\ |
552 | type MIN_META_CHUNK_SIZE;\ |
553 | type DPTE_GROUP_SIZE;\ |
554 | type MPTE_GROUP_SIZE;\ |
555 | type SWATH_HEIGHT;\ |
556 | type PTE_ROW_HEIGHT_LINEAR;\ |
557 | type CHUNK_SIZE_C;\ |
558 | type MIN_CHUNK_SIZE_C;\ |
559 | type META_CHUNK_SIZE_C;\ |
560 | type MIN_META_CHUNK_SIZE_C;\ |
561 | type DPTE_GROUP_SIZE_C;\ |
562 | type MPTE_GROUP_SIZE_C;\ |
563 | type SWATH_HEIGHT_C;\ |
564 | type PTE_ROW_HEIGHT_LINEAR_C;\ |
565 | type REFCYC_H_BLANK_END;\ |
566 | type DLG_V_BLANK_END;\ |
567 | type MIN_DST_Y_NEXT_START;\ |
568 | type REFCYC_PER_HTOTAL;\ |
569 | type REFCYC_X_AFTER_SCALER;\ |
570 | type DST_Y_AFTER_SCALER;\ |
571 | type DST_Y_PREFETCH;\ |
572 | type VRATIO_PREFETCH;\ |
573 | type DST_Y_PER_VM_VBLANK;\ |
574 | type DST_Y_PER_ROW_VBLANK;\ |
575 | type REF_FREQ_TO_PIX_FREQ;\ |
576 | type REFCYC_PER_PTE_GROUP_VBLANK_L;\ |
577 | type REFCYC_PER_META_CHUNK_VBLANK_L;\ |
578 | type DST_Y_PER_PTE_ROW_NOM_L;\ |
579 | type REFCYC_PER_PTE_GROUP_NOM_L;\ |
580 | type DST_Y_PER_META_ROW_NOM_L;\ |
581 | type REFCYC_PER_META_CHUNK_NOM_L;\ |
582 | type REFCYC_PER_LINE_DELIVERY_PRE_L;\ |
583 | type REFCYC_PER_LINE_DELIVERY_PRE_C;\ |
584 | type REFCYC_PER_LINE_DELIVERY_L;\ |
585 | type REFCYC_PER_LINE_DELIVERY_C;\ |
586 | type VRATIO_PREFETCH_C;\ |
587 | type REFCYC_PER_PTE_GROUP_VBLANK_C;\ |
588 | type REFCYC_PER_META_CHUNK_VBLANK_C;\ |
589 | type DST_Y_PER_PTE_ROW_NOM_C;\ |
590 | type REFCYC_PER_PTE_GROUP_NOM_C;\ |
591 | type DST_Y_PER_META_ROW_NOM_C;\ |
592 | type REFCYC_PER_META_CHUNK_NOM_C;\ |
593 | type QoS_LEVEL_LOW_WM;\ |
594 | type QoS_LEVEL_HIGH_WM;\ |
595 | type MIN_TTU_VBLANK;\ |
596 | type QoS_LEVEL_FLIP;\ |
597 | type REFCYC_PER_REQ_DELIVERY;\ |
598 | type QoS_LEVEL_FIXED;\ |
599 | type QoS_RAMP_DISABLE;\ |
600 | type REFCYC_PER_REQ_DELIVERY_PRE;\ |
601 | type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\ |
602 | type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\ |
603 | type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\ |
604 | type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\ |
605 | type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\ |
606 | type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\ |
607 | type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ |
608 | type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\ |
609 | type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ |
610 | type ENABLE_L1_TLB;\ |
611 | type SYSTEM_ACCESS_MODE;\ |
612 | type HUBP_CLOCK_ENABLE;\ |
613 | type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ |
614 | type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ |
615 | type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ |
616 | type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\ |
617 | type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\ |
618 | type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\ |
619 | type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\ |
620 | type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\ |
621 | type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\ |
622 | type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ |
623 | type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ |
624 | type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ |
625 | /* todo: get these from GVM instead of reading registers ourselves */\ |
626 | type PAGE_DIRECTORY_ENTRY_HI32;\ |
627 | type PAGE_DIRECTORY_ENTRY_LO32;\ |
628 | type LOGICAL_PAGE_NUMBER_HI4;\ |
629 | type LOGICAL_PAGE_NUMBER_LO32;\ |
630 | type PHYSICAL_PAGE_ADDR_HI4;\ |
631 | type PHYSICAL_PAGE_ADDR_LO32;\ |
632 | type PHYSICAL_PAGE_NUMBER_MSB;\ |
633 | type PHYSICAL_PAGE_NUMBER_LSB;\ |
634 | type LOGICAL_ADDR;\ |
635 | type CURSOR0_DST_Y_OFFSET; \ |
636 | type CURSOR0_CHUNK_HDL_ADJUST; \ |
637 | type CURSOR_SURFACE_ADDRESS_HIGH; \ |
638 | type CURSOR_SURFACE_ADDRESS; \ |
639 | type CURSOR_WIDTH; \ |
640 | type CURSOR_HEIGHT; \ |
641 | type CURSOR_MODE; \ |
642 | type CURSOR_2X_MAGNIFY; \ |
643 | type CURSOR_PITCH; \ |
644 | type CURSOR_LINES_PER_CHUNK; \ |
645 | type CURSOR_ENABLE; \ |
646 | type CURSOR_X_POSITION; \ |
647 | type CURSOR_Y_POSITION; \ |
648 | type CURSOR_HOT_SPOT_X; \ |
649 | type CURSOR_HOT_SPOT_Y; \ |
650 | type CURSOR_DST_X_OFFSET; \ |
651 | type OUTPUT_FP |
652 | |
653 | #define DCN_HUBP_REG_FIELD_LIST(type) \ |
654 | DCN_HUBP_REG_FIELD_BASE_LIST(type);\ |
655 | type ALPHA_PLANE_EN |
656 | |
657 | struct dcn_mi_registers { |
658 | HUBP_COMMON_REG_VARIABLE_LIST; |
659 | }; |
660 | |
661 | struct dcn_mi_shift { |
662 | DCN_HUBP_REG_FIELD_LIST(uint8_t); |
663 | }; |
664 | |
665 | struct dcn_mi_mask { |
666 | DCN_HUBP_REG_FIELD_LIST(uint32_t); |
667 | }; |
668 | |
669 | struct dcn_hubp_state { |
670 | struct _vcs_dpi_display_dlg_regs_st dlg_attr; |
671 | struct _vcs_dpi_display_ttu_regs_st ttu_attr; |
672 | struct _vcs_dpi_display_rq_regs_st rq_regs; |
673 | uint32_t pixel_format; |
674 | uint32_t inuse_addr_hi; |
675 | uint32_t inuse_addr_lo; |
676 | uint32_t viewport_width; |
677 | uint32_t viewport_height; |
678 | uint32_t rotation_angle; |
679 | uint32_t h_mirror_en; |
680 | uint32_t sw_mode; |
681 | uint32_t dcc_en; |
682 | uint32_t blank_en; |
683 | uint32_t clock_en; |
684 | uint32_t underflow_status; |
685 | uint32_t ttu_disable; |
686 | uint32_t min_ttu_vblank; |
687 | uint32_t qos_level_low_wm; |
688 | uint32_t qos_level_high_wm; |
689 | uint32_t primary_surface_addr_lo; |
690 | uint32_t primary_surface_addr_hi; |
691 | uint32_t primary_meta_addr_lo; |
692 | uint32_t primary_meta_addr_hi; |
693 | uint32_t uclk_pstate_force; |
694 | uint32_t hubp_cntl; |
695 | }; |
696 | |
697 | struct dcn10_hubp { |
698 | struct hubp base; |
699 | struct dcn_hubp_state state; |
700 | const struct dcn_mi_registers *hubp_regs; |
701 | const struct dcn_mi_shift *hubp_shift; |
702 | const struct dcn_mi_mask *hubp_mask; |
703 | }; |
704 | |
705 | void hubp1_program_surface_config( |
706 | struct hubp *hubp, |
707 | enum surface_pixel_format format, |
708 | union dc_tiling_info *tiling_info, |
709 | struct plane_size *plane_size, |
710 | enum dc_rotation_angle rotation, |
711 | struct dc_plane_dcc_param *dcc, |
712 | bool horizontal_mirror, |
713 | unsigned int compat_level); |
714 | |
715 | void hubp1_program_deadline( |
716 | struct hubp *hubp, |
717 | struct _vcs_dpi_display_dlg_regs_st *dlg_attr, |
718 | struct _vcs_dpi_display_ttu_regs_st *ttu_attr); |
719 | |
720 | void hubp1_program_requestor( |
721 | struct hubp *hubp, |
722 | struct _vcs_dpi_display_rq_regs_st *rq_regs); |
723 | |
724 | void hubp1_program_pixel_format( |
725 | struct hubp *hubp, |
726 | enum surface_pixel_format format); |
727 | |
728 | void hubp1_program_size( |
729 | struct hubp *hubp, |
730 | enum surface_pixel_format format, |
731 | const struct plane_size *plane_size, |
732 | struct dc_plane_dcc_param *dcc); |
733 | |
734 | void hubp1_program_rotation( |
735 | struct hubp *hubp, |
736 | enum dc_rotation_angle rotation, |
737 | bool horizontal_mirror); |
738 | |
739 | void hubp1_program_tiling( |
740 | struct hubp *hubp, |
741 | const union dc_tiling_info *info, |
742 | const enum surface_pixel_format pixel_format); |
743 | |
744 | void hubp1_dcc_control(struct hubp *hubp, |
745 | bool enable, |
746 | enum hubp_ind_block_size independent_64b_blks); |
747 | |
748 | bool hubp1_program_surface_flip_and_addr( |
749 | struct hubp *hubp, |
750 | const struct dc_plane_address *address, |
751 | bool flip_immediate); |
752 | |
753 | bool hubp1_is_flip_pending(struct hubp *hubp); |
754 | |
755 | void hubp1_cursor_set_attributes( |
756 | struct hubp *hubp, |
757 | const struct dc_cursor_attributes *attr); |
758 | |
759 | void hubp1_cursor_set_position( |
760 | struct hubp *hubp, |
761 | const struct dc_cursor_position *pos, |
762 | const struct dc_cursor_mi_param *param); |
763 | |
764 | void hubp1_set_blank(struct hubp *hubp, bool blank); |
765 | |
766 | void min_set_viewport(struct hubp *hubp, |
767 | const struct rect *viewport, |
768 | const struct rect *viewport_c); |
769 | |
770 | void hubp1_clk_cntl(struct hubp *hubp, bool enable); |
771 | void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst); |
772 | |
773 | void dcn10_hubp_construct( |
774 | struct dcn10_hubp *hubp1, |
775 | struct dc_context *ctx, |
776 | uint32_t inst, |
777 | const struct dcn_mi_registers *hubp_regs, |
778 | const struct dcn_mi_shift *hubp_shift, |
779 | const struct dcn_mi_mask *hubp_mask); |
780 | |
781 | void hubp1_read_state(struct hubp *hubp); |
782 | void hubp1_clear_underflow(struct hubp *hubp); |
783 | |
784 | enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch); |
785 | |
786 | void hubp1_vready_workaround(struct hubp *hubp, |
787 | struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); |
788 | |
789 | void hubp1_init(struct hubp *hubp); |
790 | void hubp1_read_state_common(struct hubp *hubp); |
791 | bool hubp1_in_blank(struct hubp *hubp); |
792 | void hubp1_soft_reset(struct hubp *hubp, bool reset); |
793 | |
794 | void hubp1_set_flip_int(struct hubp *hubp); |
795 | |
796 | #endif |
797 | |