1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DC_TIMING_GENERATOR_DCN10_H__ |
27 | #define __DC_TIMING_GENERATOR_DCN10_H__ |
28 | |
29 | #include "timing_generator.h" |
30 | |
31 | #define DCN10TG_FROM_TG(tg)\ |
32 | container_of(tg, struct optc, base) |
33 | |
34 | #define TG_COMMON_REG_LIST_DCN(inst) \ |
35 | SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ |
36 | SRI(OTG_VUPDATE_PARAM, OTG, inst),\ |
37 | SRI(OTG_VREADY_PARAM, OTG, inst),\ |
38 | SRI(OTG_BLANK_CONTROL, OTG, inst),\ |
39 | SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ |
40 | SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ |
41 | SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ |
42 | SRI(OTG_H_TOTAL, OTG, inst),\ |
43 | SRI(OTG_H_BLANK_START_END, OTG, inst),\ |
44 | SRI(OTG_H_SYNC_A, OTG, inst),\ |
45 | SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ |
46 | SRI(OTG_H_TIMING_CNTL, OTG, inst),\ |
47 | SRI(OTG_V_TOTAL, OTG, inst),\ |
48 | SRI(OTG_V_BLANK_START_END, OTG, inst),\ |
49 | SRI(OTG_V_SYNC_A, OTG, inst),\ |
50 | SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ |
51 | SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ |
52 | SRI(OTG_CONTROL, OTG, inst),\ |
53 | SRI(OTG_STEREO_CONTROL, OTG, inst),\ |
54 | SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ |
55 | SRI(OTG_STEREO_STATUS, OTG, inst),\ |
56 | SRI(OTG_V_TOTAL_MAX, OTG, inst),\ |
57 | SRI(OTG_V_TOTAL_MID, OTG, inst),\ |
58 | SRI(OTG_V_TOTAL_MIN, OTG, inst),\ |
59 | SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ |
60 | SRI(OTG_TRIGA_CNTL, OTG, inst),\ |
61 | SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ |
62 | SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ |
63 | SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ |
64 | SRI(OTG_STATUS, OTG, inst),\ |
65 | SRI(OTG_STATUS_POSITION, OTG, inst),\ |
66 | SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ |
67 | SRI(OTG_BLACK_COLOR, OTG, inst),\ |
68 | SRI(OTG_CLOCK_CONTROL, OTG, inst),\ |
69 | SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ |
70 | SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ |
71 | SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ |
72 | SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ |
73 | SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ |
74 | SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ |
75 | SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ |
76 | SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ |
77 | SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ |
78 | SRI(CONTROL, VTG, inst),\ |
79 | SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ |
80 | SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ |
81 | SRI(OTG_GSL_CONTROL, OTG, inst),\ |
82 | SRI(OTG_CRC_CNTL, OTG, inst),\ |
83 | SRI(OTG_CRC0_DATA_RG, OTG, inst),\ |
84 | SRI(OTG_CRC0_DATA_B, OTG, inst),\ |
85 | SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ |
86 | SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ |
87 | SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ |
88 | SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ |
89 | SR(GSL_SOURCE_SELECT),\ |
90 | SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ |
91 | SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) |
92 | |
93 | #define TG_COMMON_REG_LIST_DCN1_0(inst) \ |
94 | TG_COMMON_REG_LIST_DCN(inst),\ |
95 | SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ |
96 | SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ |
97 | SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ |
98 | SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) |
99 | |
100 | |
101 | struct dcn_optc_registers { |
102 | uint32_t OTG_GLOBAL_CONTROL1; |
103 | uint32_t OTG_GLOBAL_CONTROL2; |
104 | uint32_t OTG_VERT_SYNC_CONTROL; |
105 | uint32_t OTG_MASTER_UPDATE_MODE; |
106 | uint32_t OTG_GSL_CONTROL; |
107 | uint32_t OTG_VSTARTUP_PARAM; |
108 | uint32_t OTG_VUPDATE_PARAM; |
109 | uint32_t OTG_VREADY_PARAM; |
110 | uint32_t OTG_BLANK_CONTROL; |
111 | uint32_t OTG_MASTER_UPDATE_LOCK; |
112 | uint32_t OTG_GLOBAL_CONTROL0; |
113 | uint32_t OTG_DOUBLE_BUFFER_CONTROL; |
114 | uint32_t OTG_H_TOTAL; |
115 | uint32_t OTG_H_BLANK_START_END; |
116 | uint32_t OTG_H_SYNC_A; |
117 | uint32_t OTG_H_SYNC_A_CNTL; |
118 | uint32_t OTG_H_TIMING_CNTL; |
119 | uint32_t OTG_V_TOTAL; |
120 | uint32_t OTG_V_BLANK_START_END; |
121 | uint32_t OTG_V_SYNC_A; |
122 | uint32_t OTG_V_SYNC_A_CNTL; |
123 | uint32_t OTG_INTERLACE_CONTROL; |
124 | uint32_t OTG_CONTROL; |
125 | uint32_t OTG_STEREO_CONTROL; |
126 | uint32_t OTG_3D_STRUCTURE_CONTROL; |
127 | uint32_t OTG_STEREO_STATUS; |
128 | uint32_t OTG_V_TOTAL_MAX; |
129 | uint32_t OTG_V_TOTAL_MID; |
130 | uint32_t OTG_V_TOTAL_MIN; |
131 | uint32_t OTG_V_TOTAL_CONTROL; |
132 | uint32_t OTG_TRIGA_CNTL; |
133 | uint32_t OTG_TRIGA_MANUAL_TRIG; |
134 | uint32_t OTG_MANUAL_FLOW_CONTROL; |
135 | uint32_t OTG_FORCE_COUNT_NOW_CNTL; |
136 | uint32_t OTG_STATIC_SCREEN_CONTROL; |
137 | uint32_t OTG_STATUS_FRAME_COUNT; |
138 | uint32_t OTG_STATUS; |
139 | uint32_t OTG_STATUS_POSITION; |
140 | uint32_t OTG_NOM_VERT_POSITION; |
141 | uint32_t OTG_BLACK_COLOR; |
142 | uint32_t OTG_TEST_PATTERN_PARAMETERS; |
143 | uint32_t OTG_TEST_PATTERN_CONTROL; |
144 | uint32_t OTG_TEST_PATTERN_COLOR; |
145 | uint32_t OTG_CLOCK_CONTROL; |
146 | uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; |
147 | uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; |
148 | uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; |
149 | uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; |
150 | uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; |
151 | uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; |
152 | uint32_t OPTC_INPUT_CLOCK_CONTROL; |
153 | uint32_t OPTC_DATA_SOURCE_SELECT; |
154 | uint32_t OPTC_MEMORY_CONFIG; |
155 | uint32_t OPTC_INPUT_GLOBAL_CONTROL; |
156 | uint32_t CONTROL; |
157 | uint32_t OTG_GSL_WINDOW_X; |
158 | uint32_t OTG_GSL_WINDOW_Y; |
159 | uint32_t OTG_VUPDATE_KEEPOUT; |
160 | uint32_t OTG_CRC_CNTL; |
161 | uint32_t OTG_CRC_CNTL2; |
162 | uint32_t OTG_CRC0_DATA_RG; |
163 | uint32_t OTG_CRC0_DATA_B; |
164 | uint32_t OTG_CRC1_DATA_B; |
165 | uint32_t OTG_CRC2_DATA_B; |
166 | uint32_t OTG_CRC3_DATA_B; |
167 | uint32_t OTG_CRC1_DATA_RG; |
168 | uint32_t OTG_CRC2_DATA_RG; |
169 | uint32_t OTG_CRC3_DATA_RG; |
170 | uint32_t OTG_CRC0_WINDOWA_X_CONTROL; |
171 | uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; |
172 | uint32_t OTG_CRC0_WINDOWB_X_CONTROL; |
173 | uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; |
174 | uint32_t OTG_CRC1_WINDOWA_X_CONTROL; |
175 | uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; |
176 | uint32_t OTG_CRC1_WINDOWB_X_CONTROL; |
177 | uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; |
178 | uint32_t GSL_SOURCE_SELECT; |
179 | uint32_t DWB_SOURCE_SELECT; |
180 | uint32_t OTG_DSC_START_POSITION; |
181 | uint32_t OPTC_DATA_FORMAT_CONTROL; |
182 | uint32_t OPTC_BYTES_PER_PIXEL; |
183 | uint32_t OPTC_WIDTH_CONTROL; |
184 | uint32_t OTG_DRR_CONTROL; |
185 | uint32_t OTG_BLANK_DATA_COLOR; |
186 | uint32_t OTG_BLANK_DATA_COLOR_EXT; |
187 | uint32_t OTG_DRR_TRIGGER_WINDOW; |
188 | uint32_t OTG_M_CONST_DTO0; |
189 | uint32_t OTG_M_CONST_DTO1; |
190 | uint32_t OTG_DRR_V_TOTAL_CHANGE; |
191 | uint32_t OTG_GLOBAL_CONTROL4; |
192 | uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK; |
193 | uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK; |
194 | uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK; |
195 | uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK; |
196 | uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK; |
197 | uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK; |
198 | uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; |
199 | uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; |
200 | uint32_t OPTC_CLOCK_CONTROL; |
201 | }; |
202 | |
203 | #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ |
204 | SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ |
205 | SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ |
206 | SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ |
207 | SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ |
208 | SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ |
209 | SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ |
210 | SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ |
211 | SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ |
212 | SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ |
213 | SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ |
214 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ |
215 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ |
216 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ |
217 | SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ |
218 | SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ |
219 | SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ |
220 | SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ |
221 | SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ |
222 | SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ |
223 | SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ |
224 | SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ |
225 | SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ |
226 | SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ |
227 | SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ |
228 | SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ |
229 | SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ |
230 | SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ |
231 | SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ |
232 | SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ |
233 | SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ |
234 | SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ |
235 | SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ |
236 | SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ |
237 | SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ |
238 | SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ |
239 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ |
240 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ |
241 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ |
242 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ |
243 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ |
244 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ |
245 | SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ |
246 | SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ |
247 | SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ |
248 | SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ |
249 | SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ |
250 | SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ |
251 | SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ |
252 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ |
253 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ |
254 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ |
255 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ |
256 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ |
257 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ |
258 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ |
259 | SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ |
260 | SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ |
261 | SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ |
262 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ |
263 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ |
264 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ |
265 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ |
266 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ |
267 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ |
268 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ |
269 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ |
270 | SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ |
271 | SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ |
272 | SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ |
273 | SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ |
274 | SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ |
275 | SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ |
276 | SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ |
277 | SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ |
278 | SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ |
279 | SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ |
280 | SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ |
281 | SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ |
282 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ |
283 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ |
284 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ |
285 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ |
286 | SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ |
287 | SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ |
288 | SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ |
289 | SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ |
290 | SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ |
291 | SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ |
292 | SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ |
293 | SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ |
294 | SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ |
295 | SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ |
296 | SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ |
297 | SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ |
298 | SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ |
299 | SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ |
300 | SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ |
301 | SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ |
302 | SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ |
303 | SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ |
304 | SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ |
305 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ |
306 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ |
307 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ |
308 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ |
309 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ |
310 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ |
311 | SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ |
312 | SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ |
313 | SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ |
314 | SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ |
315 | SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ |
316 | SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ |
317 | SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ |
318 | SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ |
319 | SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ |
320 | SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ |
321 | SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ |
322 | SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ |
323 | SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ |
324 | SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ |
325 | SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ |
326 | SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ |
327 | SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ |
328 | SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) |
329 | |
330 | |
331 | |
332 | #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ |
333 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ |
334 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ |
335 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ |
336 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ |
337 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ |
338 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ |
339 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ |
340 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ |
341 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ |
342 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ |
343 | SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ |
344 | SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ |
345 | SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ |
346 | SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ |
347 | |
348 | #define TG_REG_FIELD_LIST_DCN1_0(type) \ |
349 | type VSTARTUP_START;\ |
350 | type VUPDATE_OFFSET;\ |
351 | type VUPDATE_WIDTH;\ |
352 | type VREADY_OFFSET;\ |
353 | type OTG_BLANK_DATA_EN;\ |
354 | type OTG_BLANK_DE_MODE;\ |
355 | type OTG_CURRENT_BLANK_STATE;\ |
356 | type OTG_MASTER_UPDATE_LOCK;\ |
357 | type UPDATE_LOCK_STATUS;\ |
358 | type OTG_UPDATE_PENDING;\ |
359 | type OTG_MASTER_UPDATE_LOCK_SEL;\ |
360 | type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ |
361 | type OTG_H_TOTAL;\ |
362 | type OTG_H_BLANK_START;\ |
363 | type OTG_H_BLANK_END;\ |
364 | type OTG_H_SYNC_A_START;\ |
365 | type OTG_H_SYNC_A_END;\ |
366 | type OTG_H_SYNC_A_POL;\ |
367 | type OTG_H_TIMING_DIV_BY2;\ |
368 | type OTG_V_TOTAL;\ |
369 | type OTG_V_BLANK_START;\ |
370 | type OTG_V_BLANK_END;\ |
371 | type OTG_V_SYNC_A_START;\ |
372 | type OTG_V_SYNC_A_END;\ |
373 | type OTG_V_SYNC_A_POL;\ |
374 | type OTG_INTERLACE_ENABLE;\ |
375 | type OTG_MASTER_EN;\ |
376 | type OTG_START_POINT_CNTL;\ |
377 | type OTG_DISABLE_POINT_CNTL;\ |
378 | type OTG_FIELD_NUMBER_CNTL;\ |
379 | type OTG_CURRENT_MASTER_EN_STATE;\ |
380 | type OTG_STEREO_EN;\ |
381 | type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ |
382 | type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ |
383 | type OTG_STEREO_EYE_FLAG_POLARITY;\ |
384 | type OTG_STEREO_CURRENT_EYE;\ |
385 | type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\ |
386 | type OTG_3D_STRUCTURE_EN;\ |
387 | type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ |
388 | type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ |
389 | type OTG_V_TOTAL_MAX;\ |
390 | type OTG_V_TOTAL_MID;\ |
391 | type OTG_V_TOTAL_MIN;\ |
392 | type OTG_V_TOTAL_MIN_SEL;\ |
393 | type OTG_V_TOTAL_MAX_SEL;\ |
394 | type OTG_VTOTAL_MID_REPLACING_MAX_EN;\ |
395 | type OTG_VTOTAL_MID_FRAME_NUM;\ |
396 | type OTG_FORCE_LOCK_ON_EVENT;\ |
397 | type OTG_SET_V_TOTAL_MIN_MASK_EN;\ |
398 | type OTG_SET_V_TOTAL_MIN_MASK;\ |
399 | type OTG_FORCE_COUNT_NOW_CLEAR;\ |
400 | type OTG_FORCE_COUNT_NOW_MODE;\ |
401 | type OTG_FORCE_COUNT_NOW_OCCURRED;\ |
402 | type OTG_TRIGA_SOURCE_SELECT;\ |
403 | type OTG_TRIGA_SOURCE_PIPE_SELECT;\ |
404 | type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ |
405 | type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ |
406 | type OTG_TRIGA_POLARITY_SELECT;\ |
407 | type OTG_TRIGA_FREQUENCY_SELECT;\ |
408 | type OTG_TRIGA_DELAY;\ |
409 | type OTG_TRIGA_CLEAR;\ |
410 | type OTG_TRIGA_MANUAL_TRIG;\ |
411 | type OTG_STATIC_SCREEN_EVENT_MASK;\ |
412 | type OTG_STATIC_SCREEN_FRAME_COUNT;\ |
413 | type OTG_FRAME_COUNT;\ |
414 | type OTG_V_BLANK;\ |
415 | type OTG_V_ACTIVE_DISP;\ |
416 | type OTG_HORZ_COUNT;\ |
417 | type OTG_VERT_COUNT;\ |
418 | type OTG_VERT_COUNT_NOM;\ |
419 | type OTG_BLACK_COLOR_B_CB;\ |
420 | type OTG_BLACK_COLOR_G_Y;\ |
421 | type OTG_BLACK_COLOR_R_CR;\ |
422 | type OTG_BLANK_DATA_COLOR_BLUE_CB;\ |
423 | type OTG_BLANK_DATA_COLOR_GREEN_Y;\ |
424 | type OTG_BLANK_DATA_COLOR_RED_CR;\ |
425 | type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\ |
426 | type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\ |
427 | type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\ |
428 | type OTG_VTOTAL_MID_REPLACING_MIN_EN;\ |
429 | type OTG_TEST_PATTERN_INC0;\ |
430 | type OTG_TEST_PATTERN_INC1;\ |
431 | type OTG_TEST_PATTERN_VRES;\ |
432 | type OTG_TEST_PATTERN_HRES;\ |
433 | type OTG_TEST_PATTERN_RAMP0_OFFSET;\ |
434 | type OTG_TEST_PATTERN_EN;\ |
435 | type OTG_TEST_PATTERN_MODE;\ |
436 | type OTG_TEST_PATTERN_DYNAMIC_RANGE;\ |
437 | type OTG_TEST_PATTERN_COLOR_FORMAT;\ |
438 | type OTG_TEST_PATTERN_MASK;\ |
439 | type OTG_TEST_PATTERN_DATA;\ |
440 | type OTG_BUSY;\ |
441 | type OTG_CLOCK_EN;\ |
442 | type OTG_CLOCK_ON;\ |
443 | type OTG_CLOCK_GATE_DIS;\ |
444 | type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\ |
445 | type OTG_VERTICAL_INTERRUPT0_LINE_START;\ |
446 | type OTG_VERTICAL_INTERRUPT0_LINE_END;\ |
447 | type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\ |
448 | type OTG_VERTICAL_INTERRUPT1_LINE_START;\ |
449 | type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\ |
450 | type OTG_VERTICAL_INTERRUPT2_LINE_START;\ |
451 | type OPTC_INPUT_CLK_EN;\ |
452 | type OPTC_INPUT_CLK_ON;\ |
453 | type OPTC_INPUT_CLK_GATE_DIS;\ |
454 | type OPTC_UNDERFLOW_OCCURRED_STATUS;\ |
455 | type OPTC_UNDERFLOW_CLEAR;\ |
456 | type OPTC_SRC_SEL;\ |
457 | type VTG0_ENABLE;\ |
458 | type VTG0_FP2;\ |
459 | type VTG0_VCOUNT_INIT;\ |
460 | type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ |
461 | type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ |
462 | type OTG_AUTO_FORCE_VSYNC_MODE;\ |
463 | type MASTER_UPDATE_INTERLACED_MODE;\ |
464 | type OTG_GSL0_EN;\ |
465 | type OTG_GSL1_EN;\ |
466 | type OTG_GSL2_EN;\ |
467 | type OTG_GSL_MASTER_EN;\ |
468 | type OTG_GSL_FORCE_DELAY;\ |
469 | type OTG_GSL_CHECK_ALL_FIELDS;\ |
470 | type OTG_GSL_WINDOW_START_X;\ |
471 | type OTG_GSL_WINDOW_END_X;\ |
472 | type OTG_GSL_WINDOW_START_Y;\ |
473 | type OTG_GSL_WINDOW_END_Y;\ |
474 | type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ |
475 | type OTG_GSL_MASTER_MODE;\ |
476 | type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ |
477 | type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ |
478 | type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ |
479 | type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\ |
480 | type OTG_CRC_CONT_EN;\ |
481 | type OTG_CRC0_SELECT;\ |
482 | type OTG_CRC_EN;\ |
483 | type CRC0_R_CR;\ |
484 | type CRC0_G_Y;\ |
485 | type CRC0_B_CB;\ |
486 | type CRC1_R_CR;\ |
487 | type CRC1_G_Y;\ |
488 | type CRC1_B_CB;\ |
489 | type CRC2_R_CR;\ |
490 | type CRC2_G_Y;\ |
491 | type CRC2_B_CB;\ |
492 | type CRC3_R_CR;\ |
493 | type CRC3_G_Y;\ |
494 | type CRC3_B_CB;\ |
495 | type OTG_CRC0_WINDOWA_X_START;\ |
496 | type OTG_CRC0_WINDOWA_X_END;\ |
497 | type OTG_CRC0_WINDOWA_Y_START;\ |
498 | type OTG_CRC0_WINDOWA_Y_END;\ |
499 | type OTG_CRC0_WINDOWB_X_START;\ |
500 | type OTG_CRC0_WINDOWB_X_END;\ |
501 | type OTG_CRC0_WINDOWB_Y_START;\ |
502 | type OTG_CRC0_WINDOWB_Y_END;\ |
503 | type OTG_CRC_WINDOW_DB_EN;\ |
504 | type OTG_CRC1_WINDOWA_X_START;\ |
505 | type OTG_CRC1_WINDOWA_X_END;\ |
506 | type OTG_CRC1_WINDOWA_Y_START;\ |
507 | type OTG_CRC1_WINDOWA_Y_END;\ |
508 | type OTG_CRC1_WINDOWB_X_START;\ |
509 | type OTG_CRC1_WINDOWB_X_END;\ |
510 | type OTG_CRC1_WINDOWB_Y_START;\ |
511 | type OTG_CRC1_WINDOWB_Y_END;\ |
512 | type GSL0_READY_SOURCE_SEL;\ |
513 | type GSL1_READY_SOURCE_SEL;\ |
514 | type GSL2_READY_SOURCE_SEL;\ |
515 | type MANUAL_FLOW_CONTROL;\ |
516 | type MANUAL_FLOW_CONTROL_SEL; |
517 | |
518 | #define TG_REG_FIELD_LIST(type) \ |
519 | TG_REG_FIELD_LIST_DCN1_0(type)\ |
520 | type OTG_V_SYNC_MODE;\ |
521 | type OTG_DRR_TRIGGER_WINDOW_START_X;\ |
522 | type OTG_DRR_TRIGGER_WINDOW_END_X;\ |
523 | type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\ |
524 | type OTG_OUT_MUX;\ |
525 | type OTG_M_CONST_DTO_PHASE;\ |
526 | type OTG_M_CONST_DTO_MODULO;\ |
527 | type MASTER_UPDATE_LOCK_DB_X;\ |
528 | type MASTER_UPDATE_LOCK_DB_Y;\ |
529 | type MASTER_UPDATE_LOCK_DB_EN;\ |
530 | type GLOBAL_UPDATE_LOCK_EN;\ |
531 | type DIG_UPDATE_LOCATION;\ |
532 | type OTG_DSC_START_POSITION_X;\ |
533 | type OTG_DSC_START_POSITION_LINE_NUM;\ |
534 | type OPTC_NUM_OF_INPUT_SEGMENT;\ |
535 | type OPTC_SEG0_SRC_SEL;\ |
536 | type OPTC_SEG1_SRC_SEL;\ |
537 | type OPTC_SEG2_SRC_SEL;\ |
538 | type OPTC_SEG3_SRC_SEL;\ |
539 | type OPTC_MEM_SEL;\ |
540 | type OPTC_DATA_FORMAT;\ |
541 | type OPTC_DSC_MODE;\ |
542 | type OPTC_DSC_BYTES_PER_PIXEL;\ |
543 | type OPTC_DSC_SLICE_WIDTH;\ |
544 | type OPTC_SEGMENT_WIDTH;\ |
545 | type OPTC_DWB0_SOURCE_SELECT;\ |
546 | type OPTC_DWB1_SOURCE_SELECT;\ |
547 | type MASTER_UPDATE_LOCK_DB_START_X;\ |
548 | type MASTER_UPDATE_LOCK_DB_END_X;\ |
549 | type MASTER_UPDATE_LOCK_DB_START_Y;\ |
550 | type MASTER_UPDATE_LOCK_DB_END_Y;\ |
551 | type DIG_UPDATE_POSITION_X;\ |
552 | type DIG_UPDATE_POSITION_Y;\ |
553 | type OTG_H_TIMING_DIV_MODE;\ |
554 | type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ |
555 | type OTG_CRC_DSC_MODE;\ |
556 | type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ |
557 | type OTG_CRC_DATA_STREAM_SPLIT_MODE;\ |
558 | type OTG_CRC_DATA_FORMAT;\ |
559 | type OTG_V_TOTAL_LAST_USED_BY_DRR;\ |
560 | type OTG_DRR_TIMING_DBUF_UPDATE_PENDING; |
561 | |
562 | #define TG_REG_FIELD_LIST_DCN3_2(type) \ |
563 | type OTG_H_TIMING_DIV_MODE_MANUAL; |
564 | |
565 | |
566 | #define TG_REG_FIELD_LIST_DCN3_5(type) \ |
567 | type OTG_CRC0_WINDOWA_X_START_READBACK;\ |
568 | type OTG_CRC0_WINDOWA_X_END_READBACK;\ |
569 | type OTG_CRC0_WINDOWA_Y_START_READBACK;\ |
570 | type OTG_CRC0_WINDOWA_Y_END_READBACK;\ |
571 | type OTG_CRC0_WINDOWB_X_START_READBACK;\ |
572 | type OTG_CRC0_WINDOWB_X_END_READBACK;\ |
573 | type OTG_CRC0_WINDOWB_Y_START_READBACK;\ |
574 | type OTG_CRC0_WINDOWB_Y_END_READBACK; \ |
575 | type OTG_CRC1_WINDOWA_X_START_READBACK;\ |
576 | type OTG_CRC1_WINDOWA_X_END_READBACK;\ |
577 | type OTG_CRC1_WINDOWA_Y_START_READBACK;\ |
578 | type OTG_CRC1_WINDOWA_Y_END_READBACK;\ |
579 | type OTG_CRC1_WINDOWB_X_START_READBACK;\ |
580 | type OTG_CRC1_WINDOWB_X_END_READBACK;\ |
581 | type OTG_CRC1_WINDOWB_Y_START_READBACK;\ |
582 | type OTG_CRC1_WINDOWB_Y_END_READBACK;\ |
583 | type OPTC_FGCG_REP_DIS; |
584 | |
585 | struct dcn_optc_shift { |
586 | TG_REG_FIELD_LIST(uint8_t) |
587 | TG_REG_FIELD_LIST_DCN3_2(uint8_t) |
588 | TG_REG_FIELD_LIST_DCN3_5(uint8_t) |
589 | }; |
590 | |
591 | struct dcn_optc_mask { |
592 | TG_REG_FIELD_LIST(uint32_t) |
593 | TG_REG_FIELD_LIST_DCN3_2(uint32_t) |
594 | TG_REG_FIELD_LIST_DCN3_5(uint32_t) |
595 | }; |
596 | |
597 | struct optc { |
598 | struct timing_generator base; |
599 | |
600 | const struct dcn_optc_registers *tg_regs; |
601 | const struct dcn_optc_shift *tg_shift; |
602 | const struct dcn_optc_mask *tg_mask; |
603 | |
604 | int opp_count; |
605 | |
606 | uint32_t max_h_total; |
607 | uint32_t max_v_total; |
608 | |
609 | uint32_t min_h_blank; |
610 | |
611 | uint32_t min_h_sync_width; |
612 | uint32_t min_v_sync_width; |
613 | uint32_t min_v_blank; |
614 | uint32_t min_v_blank_interlace; |
615 | |
616 | int vstartup_start; |
617 | int vupdate_offset; |
618 | int vupdate_width; |
619 | int vready_offset; |
620 | struct dc_crtc_timing orginal_patched_timing; |
621 | enum signal_type signal; |
622 | }; |
623 | |
624 | void dcn10_timing_generator_init(struct optc *optc); |
625 | |
626 | struct dcn_otg_state { |
627 | uint32_t v_blank_start; |
628 | uint32_t v_blank_end; |
629 | uint32_t v_sync_a_pol; |
630 | uint32_t v_total; |
631 | uint32_t v_total_max; |
632 | uint32_t v_total_min; |
633 | uint32_t v_total_min_sel; |
634 | uint32_t v_total_max_sel; |
635 | uint32_t v_sync_a_start; |
636 | uint32_t v_sync_a_end; |
637 | uint32_t h_blank_start; |
638 | uint32_t h_blank_end; |
639 | uint32_t h_sync_a_start; |
640 | uint32_t h_sync_a_end; |
641 | uint32_t h_sync_a_pol; |
642 | uint32_t h_total; |
643 | uint32_t underflow_occurred_status; |
644 | uint32_t otg_enabled; |
645 | uint32_t blank_enabled; |
646 | uint32_t vertical_interrupt1_en; |
647 | uint32_t vertical_interrupt1_line; |
648 | uint32_t vertical_interrupt2_en; |
649 | uint32_t vertical_interrupt2_line; |
650 | }; |
651 | |
652 | void optc1_read_otg_state(struct optc *optc1, |
653 | struct dcn_otg_state *s); |
654 | |
655 | bool optc1_get_hw_timing(struct timing_generator *tg, |
656 | struct dc_crtc_timing *hw_crtc_timing); |
657 | |
658 | bool optc1_validate_timing( |
659 | struct timing_generator *optc, |
660 | const struct dc_crtc_timing *timing); |
661 | |
662 | void optc1_program_timing( |
663 | struct timing_generator *optc, |
664 | const struct dc_crtc_timing *dc_crtc_timing, |
665 | int vready_offset, |
666 | int vstartup_start, |
667 | int vupdate_offset, |
668 | int vupdate_width, |
669 | const enum signal_type signal, |
670 | bool use_vbios); |
671 | |
672 | void optc1_setup_vertical_interrupt0( |
673 | struct timing_generator *optc, |
674 | uint32_t start_line, |
675 | uint32_t end_line); |
676 | void optc1_setup_vertical_interrupt1( |
677 | struct timing_generator *optc, |
678 | uint32_t start_line); |
679 | void optc1_setup_vertical_interrupt2( |
680 | struct timing_generator *optc, |
681 | uint32_t start_line); |
682 | |
683 | void optc1_program_global_sync( |
684 | struct timing_generator *optc, |
685 | int vready_offset, |
686 | int vstartup_start, |
687 | int vupdate_offset, |
688 | int vupdate_width); |
689 | |
690 | bool optc1_disable_crtc(struct timing_generator *optc); |
691 | |
692 | bool optc1_is_counter_moving(struct timing_generator *optc); |
693 | |
694 | void optc1_get_position(struct timing_generator *optc, |
695 | struct crtc_position *position); |
696 | |
697 | uint32_t optc1_get_vblank_counter(struct timing_generator *optc); |
698 | |
699 | void optc1_get_crtc_scanoutpos( |
700 | struct timing_generator *optc, |
701 | uint32_t *v_blank_start, |
702 | uint32_t *v_blank_end, |
703 | uint32_t *h_position, |
704 | uint32_t *v_position); |
705 | |
706 | void optc1_set_early_control( |
707 | struct timing_generator *optc, |
708 | uint32_t early_cntl); |
709 | |
710 | void optc1_wait_for_state(struct timing_generator *optc, |
711 | enum crtc_state state); |
712 | |
713 | void optc1_set_blank(struct timing_generator *optc, |
714 | bool enable_blanking); |
715 | |
716 | bool optc1_is_blanked(struct timing_generator *optc); |
717 | |
718 | void optc1_program_blank_color( |
719 | struct timing_generator *optc, |
720 | const struct tg_color *black_color); |
721 | |
722 | bool optc1_did_triggered_reset_occur( |
723 | struct timing_generator *optc); |
724 | |
725 | void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); |
726 | |
727 | void optc1_disable_reset_trigger(struct timing_generator *optc); |
728 | |
729 | void optc1_lock(struct timing_generator *optc); |
730 | |
731 | void optc1_unlock(struct timing_generator *optc); |
732 | |
733 | void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); |
734 | |
735 | void optc1_set_drr( |
736 | struct timing_generator *optc, |
737 | const struct drr_params *params); |
738 | |
739 | void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); |
740 | |
741 | void optc1_set_static_screen_control( |
742 | struct timing_generator *optc, |
743 | uint32_t event_triggers, |
744 | uint32_t num_frames); |
745 | |
746 | void optc1_program_stereo(struct timing_generator *optc, |
747 | const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); |
748 | |
749 | bool optc1_is_stereo_left_eye(struct timing_generator *optc); |
750 | |
751 | void optc1_clear_optc_underflow(struct timing_generator *optc); |
752 | |
753 | void optc1_tg_init(struct timing_generator *optc); |
754 | |
755 | bool optc1_is_tg_enabled(struct timing_generator *optc); |
756 | |
757 | bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); |
758 | |
759 | void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); |
760 | |
761 | void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable); |
762 | |
763 | bool optc1_get_otg_active_size(struct timing_generator *optc, |
764 | uint32_t *otg_active_width, |
765 | uint32_t *otg_active_height); |
766 | |
767 | void optc1_enable_crtc_reset( |
768 | struct timing_generator *optc, |
769 | int source_tg_inst, |
770 | struct crtc_trigger_info *crtc_tp); |
771 | |
772 | bool optc1_configure_crc(struct timing_generator *optc, |
773 | const struct crc_params *params); |
774 | |
775 | bool optc1_get_crc(struct timing_generator *optc, |
776 | uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); |
777 | |
778 | bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); |
779 | |
780 | void optc1_set_vtg_params(struct timing_generator *optc, |
781 | const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); |
782 | |
783 | #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ |
784 | |