1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
27#define __DAL_TIMING_GENERATOR_TYPES_H__
28
29#include "hw_shared.h"
30
31struct dc_bios;
32
33/* Contains CRTC vertical/horizontal pixel counters */
34struct crtc_position {
35 int32_t vertical_count;
36 int32_t horizontal_count;
37 int32_t nominal_vcount;
38};
39
40struct dcp_gsl_params {
41 int gsl_group;
42 int gsl_master;
43};
44
45struct gsl_params {
46 int gsl0_en;
47 int gsl1_en;
48 int gsl2_en;
49 int gsl_master_en;
50 int gsl_master_mode;
51 int master_update_lock_gsl_en;
52 int gsl_window_start_x;
53 int gsl_window_end_x;
54 int gsl_window_start_y;
55 int gsl_window_end_y;
56};
57
58/* define the structure of Dynamic Refresh Mode */
59struct drr_params {
60 uint32_t vertical_total_min;
61 uint32_t vertical_total_max;
62 uint32_t vertical_total_mid;
63 uint32_t vertical_total_mid_frame_num;
64 bool immediate_flip;
65};
66
67#define LEFT_EYE_3D_PRIMARY_SURFACE 1
68#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
69
70enum crtc_state {
71 CRTC_STATE_VBLANK = 0,
72 CRTC_STATE_VACTIVE
73};
74
75struct vupdate_keepout_params {
76 int start_offset;
77 int end_offset;
78 int enable;
79};
80
81struct crtc_stereo_flags {
82 uint8_t PROGRAM_STEREO : 1;
83 uint8_t PROGRAM_POLARITY : 1;
84 uint8_t RIGHT_EYE_POLARITY : 1;
85 uint8_t FRAME_PACKED : 1;
86 uint8_t DISABLE_STEREO_DP_SYNC : 1;
87};
88
89enum crc_selection {
90 /* Order must match values expected by hardware */
91 UNION_WINDOW_A_B = 0,
92 UNION_WINDOW_A_NOT_B,
93 UNION_WINDOW_NOT_A_B,
94 UNION_WINDOW_NOT_A_NOT_B,
95 INTERSECT_WINDOW_A_B,
96 INTERSECT_WINDOW_A_NOT_B,
97 INTERSECT_WINDOW_NOT_A_B,
98 INTERSECT_WINDOW_NOT_A_NOT_B,
99};
100
101enum otg_out_mux_dest {
102 OUT_MUX_DIO = 0,
103 OUT_MUX_HPO_DP = 2,
104};
105
106enum h_timing_div_mode {
107 H_TIMING_NO_DIV,
108 H_TIMING_DIV_BY2,
109 H_TIMING_RESERVED,
110 H_TIMING_DIV_BY4,
111};
112
113enum timing_synchronization_type {
114 NOT_SYNCHRONIZABLE,
115 TIMING_SYNCHRONIZABLE,
116 VBLANK_SYNCHRONIZABLE
117};
118
119struct crc_params {
120 /* Regions used to calculate CRC*/
121 uint16_t windowa_x_start;
122 uint16_t windowa_x_end;
123 uint16_t windowa_y_start;
124 uint16_t windowa_y_end;
125
126 uint16_t windowb_x_start;
127 uint16_t windowb_x_end;
128 uint16_t windowb_y_start;
129 uint16_t windowb_y_end;
130
131 enum crc_selection selection;
132
133 uint8_t dsc_mode;
134 uint8_t odm_mode;
135
136 bool continuous_mode;
137 bool enable;
138};
139
140/**
141 * struct timing_generator - Entry point to Output Timing Generator feature.
142 */
143struct timing_generator {
144 /**
145 * @funcs: Timing generator control functions
146 */
147 const struct timing_generator_funcs *funcs;
148 struct dc_bios *bp;
149 struct dc_context *ctx;
150 int inst;
151};
152
153struct dc_crtc_timing;
154
155struct drr_params;
156
157/**
158 * struct timing_generator_funcs - Control timing generator on a given device.
159 */
160struct timing_generator_funcs {
161 bool (*validate_timing)(struct timing_generator *tg,
162 const struct dc_crtc_timing *timing);
163 void (*program_timing)(struct timing_generator *tg,
164 const struct dc_crtc_timing *timing,
165 int vready_offset,
166 int vstartup_start,
167 int vupdate_offset,
168 int vupdate_width,
169 const enum signal_type signal,
170 bool use_vbios
171 );
172 void (*setup_vertical_interrupt0)(
173 struct timing_generator *optc,
174 uint32_t start_line,
175 uint32_t end_line);
176 void (*setup_vertical_interrupt1)(
177 struct timing_generator *optc,
178 uint32_t start_line);
179 void (*setup_vertical_interrupt2)(
180 struct timing_generator *optc,
181 uint32_t start_line);
182
183 bool (*enable_crtc)(struct timing_generator *tg);
184 bool (*disable_crtc)(struct timing_generator *tg);
185#ifdef CONFIG_DRM_AMD_DC_FP
186 void (*phantom_crtc_post_enable)(struct timing_generator *tg);
187#endif
188 void (*disable_phantom_crtc)(struct timing_generator *tg);
189 bool (*immediate_disable_crtc)(struct timing_generator *tg);
190 bool (*is_counter_moving)(struct timing_generator *tg);
191 void (*get_position)(struct timing_generator *tg,
192 struct crtc_position *position);
193
194 uint32_t (*get_frame_count)(struct timing_generator *tg);
195 void (*get_scanoutpos)(
196 struct timing_generator *tg,
197 uint32_t *v_blank_start,
198 uint32_t *v_blank_end,
199 uint32_t *h_position,
200 uint32_t *v_position);
201 bool (*get_otg_active_size)(struct timing_generator *optc,
202 uint32_t *otg_active_width,
203 uint32_t *otg_active_height);
204 bool (*is_matching_timing)(struct timing_generator *tg,
205 const struct dc_crtc_timing *otg_timing);
206 void (*set_early_control)(struct timing_generator *tg,
207 uint32_t early_cntl);
208 void (*wait_for_state)(struct timing_generator *tg,
209 enum crtc_state state);
210 void (*set_blank)(struct timing_generator *tg,
211 bool enable_blanking);
212 bool (*is_blanked)(struct timing_generator *tg);
213 void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
214 void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
215 void (*set_colors)(struct timing_generator *tg,
216 const struct tg_color *blank_color,
217 const struct tg_color *overscan_color);
218
219 void (*disable_vga)(struct timing_generator *tg);
220 bool (*did_triggered_reset_occur)(struct timing_generator *tg);
221 void (*setup_global_swap_lock)(struct timing_generator *tg,
222 const struct dcp_gsl_params *gsl_params);
223 void (*unlock)(struct timing_generator *tg);
224 void (*lock)(struct timing_generator *tg);
225 void (*lock_doublebuffer_disable)(struct timing_generator *tg);
226 void (*lock_doublebuffer_enable)(struct timing_generator *tg);
227 void(*triplebuffer_unlock)(struct timing_generator *tg);
228 void(*triplebuffer_lock)(struct timing_generator *tg);
229 void (*enable_reset_trigger)(struct timing_generator *tg,
230 int source_tg_inst);
231 void (*enable_crtc_reset)(struct timing_generator *tg,
232 int source_tg_inst,
233 struct crtc_trigger_info *crtc_tp);
234 void (*disable_reset_trigger)(struct timing_generator *tg);
235 void (*tear_down_global_swap_lock)(struct timing_generator *tg);
236 void (*enable_advanced_request)(struct timing_generator *tg,
237 bool enable, const struct dc_crtc_timing *timing);
238 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
239 void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
240 void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
241 void (*set_static_screen_control)(struct timing_generator *tg,
242 uint32_t event_triggers,
243 uint32_t num_frames);
244 void (*set_test_pattern)(
245 struct timing_generator *tg,
246 enum controller_dp_test_pattern test_pattern,
247 enum dc_color_depth color_depth);
248
249 bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
250
251 void (*program_global_sync)(struct timing_generator *tg,
252 int vready_offset,
253 int vstartup_start,
254 int vupdate_offset,
255 int vupdate_width);
256 void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
257 void (*program_stereo)(struct timing_generator *tg,
258 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
259 bool (*is_stereo_left_eye)(struct timing_generator *tg);
260
261 void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
262
263 void (*tg_init)(struct timing_generator *tg);
264 bool (*is_tg_enabled)(struct timing_generator *tg);
265 bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
266 void (*clear_optc_underflow)(struct timing_generator *tg);
267
268 void (*set_dwb_source)(struct timing_generator *optc,
269 uint32_t dwb_pipe_inst);
270
271 void (*get_optc_source)(struct timing_generator *optc,
272 uint32_t *num_of_input_segments,
273 uint32_t *seg0_src_sel,
274 uint32_t *seg1_src_sel);
275
276 /**
277 * Configure CRCs for the given timing generator. Return false if TG is
278 * not on.
279 */
280 bool (*configure_crc)(struct timing_generator *tg,
281 const struct crc_params *params);
282
283 /**
284 * @get_crc: Get CRCs for the given timing generator. Return false if
285 * CRCs are not enabled (via configure_crc).
286 */
287 bool (*get_crc)(struct timing_generator *tg,
288 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
289
290 void (*program_manual_trigger)(struct timing_generator *optc);
291 void (*setup_manual_trigger)(struct timing_generator *optc);
292 bool (*get_hw_timing)(struct timing_generator *optc,
293 struct dc_crtc_timing *hw_crtc_timing);
294
295 void (*set_vtg_params)(struct timing_generator *optc,
296 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
297
298 void (*set_dsc_config)(struct timing_generator *optc,
299 enum optc_dsc_mode dsc_mode,
300 uint32_t dsc_bytes_per_pixel,
301 uint32_t dsc_slice_width);
302 void (*get_dsc_status)(struct timing_generator *optc,
303 uint32_t *dsc_mode);
304 void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
305
306 /**
307 * @set_odm_combine: Set up the ODM block to read from the correct
308 * OPP(s) and turn on/off ODM memory.
309 */
310 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
311 struct dc_crtc_timing *timing);
312 void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments);
313 void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
314 void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
315 void (*set_gsl_source_select)(struct timing_generator *optc,
316 int group_idx,
317 uint32_t gsl_ready_signal);
318 void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
319 void (*set_drr_trigger_window)(struct timing_generator *optc,
320 uint32_t window_start, uint32_t window_end);
321 void (*set_vtotal_change_limit)(struct timing_generator *optc,
322 uint32_t limit);
323 void (*align_vblanks)(struct timing_generator *master_optc,
324 struct timing_generator *slave_optc,
325 uint32_t master_pixel_clock_100Hz,
326 uint32_t slave_pixel_clock_100Hz,
327 uint8_t master_clock_divider,
328 uint8_t slave_clock_divider);
329 bool (*validate_vmin_vmax)(struct timing_generator *optc,
330 int vmin, int vmax);
331 bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
332 uint32_t vtotal_change_limit);
333
334 void (*init_odm)(struct timing_generator *tg);
335 void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg);
336};
337
338#endif
339

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h