1 | /* Copyright 2012-17 Advanced Micro Devices, Inc. |
2 | * |
3 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * copy of this software and associated documentation files (the "Software"), |
5 | * to deal in the Software without restriction, including without limitation |
6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * Software is furnished to do so, subject to the following conditions: |
9 | * |
10 | * The above copyright notice and this permission notice shall be included in |
11 | * all copies or substantial portions of the Software. |
12 | * |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * |
21 | * Authors: AMD |
22 | * |
23 | */ |
24 | #ifndef __DC_DWBC_DCN20_H__ |
25 | #define __DC_DWBC_DCN20_H__ |
26 | |
27 | #define TO_DCN20_DWBC(dwbc_base) \ |
28 | container_of(dwbc_base, struct dcn20_dwbc, base) |
29 | |
30 | #define DWBC_COMMON_REG_LIST_DCN2_0(inst) \ |
31 | SRI2_DWB(WB_ENABLE, CNV, inst),\ |
32 | SRI2_DWB(WB_EC_CONFIG, CNV, inst),\ |
33 | SRI2_DWB(CNV_MODE, CNV, inst),\ |
34 | SRI2_DWB(CNV_WINDOW_START, CNV, inst),\ |
35 | SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\ |
36 | SRI2_DWB(CNV_UPDATE, CNV, inst),\ |
37 | SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\ |
38 | SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\ |
39 | SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\ |
40 | SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\ |
41 | SRI2_DWB(CNV_TEST_CRC_BLUE, CNV, inst),\ |
42 | SRI2_DWB(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\ |
43 | SRI2_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\ |
44 | SRI2_DWB(WBSCL_MODE, WBSCL, inst),\ |
45 | SRI2_DWB(WBSCL_TAP_CONTROL, WBSCL, inst),\ |
46 | SRI2_DWB(WBSCL_DEST_SIZE, WBSCL, inst),\ |
47 | SRI2_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\ |
48 | SRI2_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\ |
49 | SRI2_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\ |
50 | SRI2_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\ |
51 | SRI2_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\ |
52 | SRI2_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\ |
53 | SRI2_DWB(WBSCL_ROUND_OFFSET, WBSCL, inst),\ |
54 | SRI2_DWB(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\ |
55 | SRI2_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\ |
56 | SRI2_DWB(WBSCL_TEST_CNTL, WBSCL, inst),\ |
57 | SRI2_DWB(WBSCL_TEST_CRC_RED, WBSCL, inst),\ |
58 | SRI2_DWB(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\ |
59 | SRI2_DWB(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\ |
60 | SRI2_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\ |
61 | SRI2_DWB(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\ |
62 | SRI2_DWB(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\ |
63 | SRI2_DWB(WBSCL_CLAMP_CBCR, WBSCL, inst),\ |
64 | SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\ |
65 | SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\ |
66 | SRI2_DWB(WBSCL_DEBUG, WBSCL, inst),\ |
67 | SRI2_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\ |
68 | SRI2_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\ |
69 | SRI2_DWB(WB_DEBUG_CTRL, CNV, inst),\ |
70 | SRI2_DWB(WB_DBG_MODE, CNV, inst),\ |
71 | SRI2_DWB(WB_HW_DEBUG, CNV, inst),\ |
72 | SRI2_DWB(CNV_TEST_DEBUG_INDEX, CNV, inst),\ |
73 | SRI2_DWB(CNV_TEST_DEBUG_DATA, CNV, inst),\ |
74 | SRI2_DWB(WB_SOFT_RESET, CNV, inst),\ |
75 | SRI2_DWB(WB_WARM_UP_MODE_CTL1, CNV, inst),\ |
76 | SRI2_DWB(WB_WARM_UP_MODE_CTL2, CNV, inst) |
77 | |
78 | #define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ |
79 | SF_DWB(WB_ENABLE, WB_ENABLE, mask_sh),\ |
80 | SF_DWB(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ |
81 | SF_DWB(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ |
82 | SF_DWB(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ |
83 | SF_DWB(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\ |
84 | SF_DWB(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ |
85 | SF_DWB(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\ |
86 | SF_DWB(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ |
87 | SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\ |
88 | SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\ |
89 | SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\ |
90 | SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\ |
91 | SF_DWB(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\ |
92 | SF_DWB(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\ |
93 | SF_DWB(CNV_MODE, CNV_OUT_BPC, mask_sh),\ |
94 | SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\ |
95 | SF_DWB(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ |
96 | SF_DWB(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ |
97 | SF_DWB(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ |
98 | SF_DWB(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ |
99 | SF_DWB(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ |
100 | SF_DWB(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ |
101 | SF_DWB(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ |
102 | SF_DWB(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ |
103 | SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\ |
104 | SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ |
105 | SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\ |
106 | SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\ |
107 | SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\ |
108 | SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\ |
109 | SF_DWB(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\ |
110 | SF_DWB(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\ |
111 | SF_DWB(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\ |
112 | SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\ |
113 | SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\ |
114 | SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\ |
115 | SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\ |
116 | SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\ |
117 | SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\ |
118 | SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\ |
119 | SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\ |
120 | SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\ |
121 | SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\ |
122 | SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\ |
123 | SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\ |
124 | SF_DWB(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\ |
125 | SF_DWB(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\ |
126 | SF_DWB(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\ |
127 | SF_DWB(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\ |
128 | SF_DWB(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\ |
129 | SF_DWB(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\ |
130 | SF_DWB(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\ |
131 | SF_DWB(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ |
132 | SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\ |
133 | SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\ |
134 | SF_DWB(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\ |
135 | SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ |
136 | SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\ |
137 | SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\ |
138 | SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ |
139 | SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ |
140 | SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ |
141 | SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ |
142 | SF_DWB(WBSCL_MODE, WBSCL_MODE, mask_sh),\ |
143 | SF_DWB(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\ |
144 | SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\ |
145 | SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\ |
146 | SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\ |
147 | SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\ |
148 | SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\ |
149 | SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\ |
150 | SF_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\ |
151 | SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\ |
152 | SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\ |
153 | SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\ |
154 | SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\ |
155 | SF_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\ |
156 | SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\ |
157 | SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\ |
158 | SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\ |
159 | SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\ |
160 | SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\ |
161 | SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\ |
162 | SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\ |
163 | SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\ |
164 | SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\ |
165 | SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\ |
166 | SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\ |
167 | SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\ |
168 | SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\ |
169 | SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\ |
170 | SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\ |
171 | SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\ |
172 | SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\ |
173 | SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\ |
174 | SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\ |
175 | SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\ |
176 | SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\ |
177 | SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\ |
178 | SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\ |
179 | SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\ |
180 | SF_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\ |
181 | SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\ |
182 | SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\ |
183 | SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\ |
184 | SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\ |
185 | SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ |
186 | SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ |
187 | SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\ |
188 | SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\ |
189 | SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\ |
190 | SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\ |
191 | SF_DWB(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\ |
192 | SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\ |
193 | SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\ |
194 | SF_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\ |
195 | SF_DWB(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\ |
196 | SF_DWB(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\ |
197 | SF_DWB(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\ |
198 | SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\ |
199 | SF_DWB(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\ |
200 | SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh) |
201 | |
202 | #define DWBC_REG_FIELD_LIST_DCN2_0(type) \ |
203 | type WB_ENABLE;\ |
204 | type DISPCLK_R_WB_GATE_DIS;\ |
205 | type DISPCLK_G_WB_GATE_DIS;\ |
206 | type DISPCLK_G_WBSCL_GATE_DIS;\ |
207 | type WB_TEST_CLK_SEL;\ |
208 | type WB_LB_LS_DIS;\ |
209 | type WB_LB_SD_DIS;\ |
210 | type WB_LUT_LS_DIS;\ |
211 | type WBSCL_LB_MEM_PWR_MODE_SEL;\ |
212 | type WBSCL_LB_MEM_PWR_DIS;\ |
213 | type WBSCL_LB_MEM_PWR_FORCE;\ |
214 | type WBSCL_LB_MEM_PWR_STATE;\ |
215 | type WB_RAM_PW_SAVE_MODE;\ |
216 | type WBSCL_LUT_MEM_PWR_STATE;\ |
217 | type CNV_OUT_BPC;\ |
218 | type CNV_FRAME_CAPTURE_RATE;\ |
219 | type CNV_WINDOW_CROP_EN;\ |
220 | type CNV_STEREO_TYPE;\ |
221 | type CNV_INTERLACED_MODE;\ |
222 | type CNV_EYE_SELECTION;\ |
223 | type CNV_STEREO_POLARITY;\ |
224 | type CNV_INTERLACED_FIELD_ORDER;\ |
225 | type CNV_STEREO_SPLIT;\ |
226 | type CNV_NEW_CONTENT;\ |
227 | type CNV_FRAME_CAPTURE_EN_CURRENT;\ |
228 | type CNV_FRAME_CAPTURE_EN;\ |
229 | type CNV_WINDOW_START_X;\ |
230 | type CNV_WINDOW_START_Y;\ |
231 | type CNV_WINDOW_WIDTH;\ |
232 | type CNV_WINDOW_HEIGHT;\ |
233 | type CNV_UPDATE_PENDING;\ |
234 | type CNV_UPDATE_TAKEN;\ |
235 | type CNV_UPDATE_LOCK;\ |
236 | type CNV_SOURCE_WIDTH;\ |
237 | type CNV_SOURCE_HEIGHT;\ |
238 | type CNV_TEST_CRC_EN;\ |
239 | type CNV_TEST_CRC_CONT_EN;\ |
240 | type CNV_TEST_CRC_RED_MASK;\ |
241 | type CNV_TEST_CRC_SIG_RED;\ |
242 | type CNV_TEST_CRC_GREEN_MASK;\ |
243 | type CNV_TEST_CRC_SIG_GREEN;\ |
244 | type CNV_TEST_CRC_BLUE_MASK;\ |
245 | type CNV_TEST_CRC_SIG_BLUE;\ |
246 | type WB_DEBUG_EN;\ |
247 | type WB_DEBUG_SEL;\ |
248 | type WB_DBG_MODE_EN;\ |
249 | type WB_DBG_DIN_FMT;\ |
250 | type WB_DBG_36MODE;\ |
251 | type WB_DBG_CMAP;\ |
252 | type WB_DBG_PXLRATE_ERROR;\ |
253 | type WB_DBG_SOURCE_WIDTH;\ |
254 | type WB_HW_DEBUG;\ |
255 | type CNV_TEST_DEBUG_INDEX;\ |
256 | type CNV_TEST_DEBUG_WRITE_EN;\ |
257 | type CNV_TEST_DEBUG_DATA;\ |
258 | type WB_SOFT_RESET;\ |
259 | type WBSCL_COEF_RAM_TAP_PAIR_IDX;\ |
260 | type WBSCL_COEF_RAM_PHASE;\ |
261 | type WBSCL_COEF_RAM_FILTER_TYPE;\ |
262 | type WBSCL_COEF_RAM_SEL;\ |
263 | type WBSCL_COEF_RAM_SEL_CURRENT;\ |
264 | type WBSCL_COEF_RAM_RD_SEL;\ |
265 | type WBSCL_COEF_RAM_EVEN_TAP_COEF;\ |
266 | type WBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\ |
267 | type WBSCL_COEF_RAM_ODD_TAP_COEF;\ |
268 | type WBSCL_COEF_RAM_ODD_TAP_COEF_EN;\ |
269 | type WBSCL_MODE;\ |
270 | type WBSCL_OUT_BIT_DEPTH;\ |
271 | type WBSCL_V_NUM_OF_TAPS_Y_RGB;\ |
272 | type WBSCL_V_NUM_OF_TAPS_CBCR;\ |
273 | type WBSCL_H_NUM_OF_TAPS_Y_RGB;\ |
274 | type WBSCL_H_NUM_OF_TAPS_CBCR;\ |
275 | type WBSCL_DEST_HEIGHT;\ |
276 | type WBSCL_DEST_WIDTH;\ |
277 | type WBSCL_H_SCALE_RATIO;\ |
278 | type WBSCL_H_INIT_FRAC_Y_RGB;\ |
279 | type WBSCL_H_INIT_INT_Y_RGB;\ |
280 | type WBSCL_H_INIT_FRAC_CBCR;\ |
281 | type WBSCL_H_INIT_INT_CBCR;\ |
282 | type WBSCL_V_SCALE_RATIO;\ |
283 | type WBSCL_V_INIT_FRAC_Y_RGB;\ |
284 | type WBSCL_V_INIT_INT_Y_RGB;\ |
285 | type WBSCL_V_INIT_FRAC_CBCR;\ |
286 | type WBSCL_V_INIT_INT_CBCR;\ |
287 | type WBSCL_ROUND_OFFSET_Y_RGB;\ |
288 | type WBSCL_ROUND_OFFSET_CBCR;\ |
289 | type WBSCL_DATA_OVERFLOW_FLAG;\ |
290 | type WBSCL_DATA_OVERFLOW_ACK;\ |
291 | type WBSCL_DATA_OVERFLOW_MASK;\ |
292 | type WBSCL_DATA_OVERFLOW_INT_STATUS;\ |
293 | type WBSCL_DATA_OVERFLOW_INT_TYPE;\ |
294 | type WBSCL_HOST_CONFLICT_FLAG;\ |
295 | type WBSCL_HOST_CONFLICT_ACK;\ |
296 | type WBSCL_HOST_CONFLICT_MASK;\ |
297 | type WBSCL_HOST_CONFLICT_INT_STATUS;\ |
298 | type WBSCL_HOST_CONFLICT_INT_TYPE;\ |
299 | type WBSCL_TEST_CRC_EN;\ |
300 | type WBSCL_TEST_CRC_CONT_EN;\ |
301 | type WBSCL_TEST_CRC_RED_MASK;\ |
302 | type WBSCL_TEST_CRC_SIG_RED;\ |
303 | type WBSCL_TEST_CRC_GREEN_MASK;\ |
304 | type WBSCL_TEST_CRC_SIG_GREEN;\ |
305 | type WBSCL_TEST_CRC_BLUE_MASK;\ |
306 | type WBSCL_TEST_CRC_SIG_BLUE;\ |
307 | type WBSCL_BACKPRESSURE_CNT_EN;\ |
308 | type WB_MCIF_Y_MAX_BACKPRESSURE;\ |
309 | type WB_MCIF_C_MAX_BACKPRESSURE;\ |
310 | type WBSCL_CLAMP_UPPER_Y_RGB;\ |
311 | type WBSCL_CLAMP_LOWER_Y_RGB;\ |
312 | type WBSCL_CLAMP_UPPER_CBCR;\ |
313 | type WBSCL_CLAMP_LOWER_CBCR;\ |
314 | type WBSCL_OUTSIDE_PIX_STRATEGY;\ |
315 | type WBSCL_BLACK_COLOR_G_Y;\ |
316 | type WBSCL_BLACK_COLOR_B_CB;\ |
317 | type WBSCL_BLACK_COLOR_R_CR;\ |
318 | type WBSCL_DEBUG;\ |
319 | type WBSCL_TEST_DEBUG_INDEX;\ |
320 | type WBSCL_TEST_DEBUG_WRITE_EN;\ |
321 | type WBSCL_TEST_DEBUG_DATA;\ |
322 | type WIDTH_WARMUP;\ |
323 | type HEIGHT_WARMUP;\ |
324 | type GMC_WARM_UP_ENABLE;\ |
325 | type DATA_VALUE_WARMUP;\ |
326 | type MODE_WARMUP;\ |
327 | type DATA_DEPTH_WARMUP; \ |
328 | |
329 | struct dcn20_dwbc_registers { |
330 | /* DCN2.0 */ |
331 | uint32_t WB_ENABLE; |
332 | uint32_t WB_EC_CONFIG; |
333 | uint32_t CNV_MODE; |
334 | uint32_t CNV_WINDOW_START; |
335 | uint32_t CNV_WINDOW_SIZE; |
336 | uint32_t CNV_UPDATE; |
337 | uint32_t CNV_SOURCE_SIZE; |
338 | uint32_t CNV_TEST_CNTL; |
339 | uint32_t CNV_TEST_CRC_RED; |
340 | uint32_t CNV_TEST_CRC_GREEN; |
341 | uint32_t CNV_TEST_CRC_BLUE; |
342 | uint32_t WB_DEBUG_CTRL; |
343 | uint32_t WB_DBG_MODE; |
344 | uint32_t WB_HW_DEBUG; |
345 | uint32_t CNV_TEST_DEBUG_INDEX; |
346 | uint32_t CNV_TEST_DEBUG_DATA; |
347 | uint32_t WB_SOFT_RESET; |
348 | uint32_t WBSCL_COEF_RAM_SELECT; |
349 | uint32_t WBSCL_COEF_RAM_TAP_DATA; |
350 | uint32_t WBSCL_MODE; |
351 | uint32_t WBSCL_TAP_CONTROL; |
352 | uint32_t WBSCL_DEST_SIZE; |
353 | uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO; |
354 | uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB; |
355 | uint32_t WBSCL_HORZ_FILTER_INIT_CBCR; |
356 | uint32_t WBSCL_VERT_FILTER_SCALE_RATIO; |
357 | uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB; |
358 | uint32_t WBSCL_VERT_FILTER_INIT_CBCR; |
359 | uint32_t WBSCL_ROUND_OFFSET; |
360 | uint32_t WBSCL_OVERFLOW_STATUS; |
361 | uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS; |
362 | uint32_t WBSCL_TEST_CNTL; |
363 | uint32_t WBSCL_TEST_CRC_RED; |
364 | uint32_t WBSCL_TEST_CRC_GREEN; |
365 | uint32_t WBSCL_TEST_CRC_BLUE; |
366 | uint32_t WBSCL_BACKPRESSURE_CNT_EN; |
367 | uint32_t WB_MCIF_BACKPRESSURE_CNT; |
368 | uint32_t WBSCL_CLAMP_Y_RGB; |
369 | uint32_t WBSCL_CLAMP_CBCR; |
370 | uint32_t WBSCL_OUTSIDE_PIX_STRATEGY; |
371 | uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR; |
372 | uint32_t WBSCL_DEBUG; |
373 | uint32_t WBSCL_TEST_DEBUG_INDEX; |
374 | uint32_t WBSCL_TEST_DEBUG_DATA; |
375 | uint32_t WB_WARM_UP_MODE_CTL1; |
376 | uint32_t WB_WARM_UP_MODE_CTL2; |
377 | }; |
378 | |
379 | |
380 | struct dcn20_dwbc_mask { |
381 | DWBC_REG_FIELD_LIST_DCN2_0(uint32_t) |
382 | }; |
383 | |
384 | struct dcn20_dwbc_shift { |
385 | DWBC_REG_FIELD_LIST_DCN2_0(uint8_t) |
386 | }; |
387 | |
388 | struct dcn20_dwbc { |
389 | struct dwbc base; |
390 | const struct dcn20_dwbc_registers *dwbc_regs; |
391 | const struct dcn20_dwbc_shift *dwbc_shift; |
392 | const struct dcn20_dwbc_mask *dwbc_mask; |
393 | }; |
394 | |
395 | void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20, |
396 | struct dc_context *ctx, |
397 | const struct dcn20_dwbc_registers *dwbc_regs, |
398 | const struct dcn20_dwbc_shift *dwbc_shift, |
399 | const struct dcn20_dwbc_mask *dwbc_mask, |
400 | int inst); |
401 | |
402 | bool dwb2_disable(struct dwbc *dwbc); |
403 | |
404 | bool dwb2_is_enabled(struct dwbc *dwbc); |
405 | |
406 | void dwb2_set_stereo(struct dwbc *dwbc, |
407 | struct dwb_stereo_params *stereo_params); |
408 | |
409 | void dwb2_set_new_content(struct dwbc *dwbc, |
410 | bool is_new_content); |
411 | |
412 | void dwb2_config_dwb_cnv(struct dwbc *dwbc, |
413 | struct dc_dwb_params *params); |
414 | |
415 | void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params); |
416 | |
417 | bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20, |
418 | uint32_t src_height, |
419 | uint32_t dest_height, |
420 | struct scaling_taps num_taps, |
421 | enum dwb_subsample_position subsample_position); |
422 | |
423 | bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20, |
424 | uint32_t src_width, |
425 | uint32_t dest_width, |
426 | struct scaling_taps num_taps); |
427 | |
428 | |
429 | #endif |
430 | |
431 | |
432 | |