1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include <linux/delay.h> |
27 | |
28 | #include "dcn20_vmid.h" |
29 | #include "reg_helper.h" |
30 | |
31 | #define REG(reg)\ |
32 | vmid->regs->reg |
33 | |
34 | #define CTX \ |
35 | vmid->ctx |
36 | |
37 | #undef FN |
38 | #define FN(reg_name, field_name) \ |
39 | vmid->shifts->field_name, vmid->masks->field_name |
40 | |
41 | #define DC_LOGGER \ |
42 | CTX->logger |
43 | |
44 | static void dcn20_wait_for_vmid_ready(struct dcn20_vmid *vmid) |
45 | { |
46 | /* According the hardware spec, we need to poll for the lowest |
47 | * bit of PAGE_TABLE_BASE_ADDR_LO32 = 1 any time a GPUVM |
48 | * context is updated. We can't use REG_WAIT here since we |
49 | * don't have a seperate field to wait on. |
50 | * |
51 | * TODO: Confirm timeout / poll interval with hardware team |
52 | */ |
53 | |
54 | int max_times = 10000; |
55 | int delay_us = 5; |
56 | int i; |
57 | |
58 | for (i = 0; i < max_times; ++i) { |
59 | uint32_t entry_lo32; |
60 | |
61 | REG_GET(PAGE_TABLE_BASE_ADDR_LO32, |
62 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, |
63 | &entry_lo32); |
64 | |
65 | if (entry_lo32 & 0x1) |
66 | return; |
67 | |
68 | udelay(delay_us); |
69 | } |
70 | |
71 | /* VM setup timed out */ |
72 | DC_LOG_WARNING("Timeout while waiting for GPUVM context update\n" ); |
73 | ASSERT(0); |
74 | } |
75 | |
76 | void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config) |
77 | { |
78 | REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, |
79 | VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_start_addr >> 32) & 0xF); |
80 | REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, |
81 | VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, config->page_table_start_addr & 0xFFFFFFFF); |
82 | |
83 | REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, |
84 | VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_end_addr >> 32) & 0xF); |
85 | REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, |
86 | VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, config->page_table_end_addr & 0xFFFFFFFF); |
87 | |
88 | REG_SET_2(CNTL, 0, |
89 | VM_CONTEXT0_PAGE_TABLE_DEPTH, config->depth, |
90 | VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, config->block_size); |
91 | |
92 | REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, |
93 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF); |
94 | /* Note: per hardware spec PAGE_TABLE_BASE_ADDR_LO32 must be programmed last in sequence */ |
95 | REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, |
96 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF); |
97 | |
98 | dcn20_wait_for_vmid_ready(vmid); |
99 | } |
100 | |