1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef _DCN30_RESOURCE_H_
27#define _DCN30_RESOURCE_H_
28
29#include "core_types.h"
30
31#define TO_DCN30_RES_POOL(pool)\
32 container_of(pool, struct dcn30_resource_pool, base)
33
34struct dc;
35struct resource_pool;
36struct _vcs_dpi_display_pipe_params_st;
37
38extern struct _vcs_dpi_ip_params_st dcn3_0_ip;
39extern struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc;
40
41struct dcn30_resource_pool {
42 struct resource_pool base;
43};
44struct resource_pool *dcn30_create_resource_pool(
45 const struct dc_init_data *init_data,
46 struct dc *dc);
47
48void dcn30_set_mcif_arb_params(
49 struct dc *dc,
50 struct dc_state *context,
51 display_e2e_pipe_params_st *pipes,
52 int pipe_cnt);
53
54unsigned int dcn30_calc_max_scaled_time(
55 unsigned int time_per_pixel,
56 enum mmhubbub_wbif_mode mode,
57 unsigned int urgent_watermark);
58
59bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
60 bool fast_validate);
61bool dcn30_internal_validate_bw(
62 struct dc *dc,
63 struct dc_state *context,
64 display_e2e_pipe_params_st *pipes,
65 int *pipe_cnt_out,
66 int *vlevel_out,
67 bool fast_validate,
68 bool allow_self_refresh_only);
69void dcn30_calculate_wm_and_dlg(
70 struct dc *dc, struct dc_state *context,
71 display_e2e_pipe_params_st *pipes,
72 int pipe_cnt,
73 int vlevel);
74void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
75void dcn30_populate_dml_writeback_from_context(
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
77
78int dcn30_populate_dml_pipes_from_context(
79 struct dc *dc, struct dc_state *context,
80 display_e2e_pipe_params_st *pipes,
81 bool fast_validate);
82
83bool dcn30_acquire_post_bldn_3dlut(
84 struct resource_context *res_ctx,
85 const struct resource_pool *pool,
86 int mpcc_id,
87 struct dc_3dlut **lut,
88 struct dc_transfer_func **shaper);
89
90bool dcn30_release_post_bldn_3dlut(
91 struct resource_context *res_ctx,
92 const struct resource_pool *pool,
93 struct dc_3dlut **lut,
94 struct dc_transfer_func **shaper);
95
96enum dc_status dcn30_add_stream_to_ctx(
97 struct dc *dc,
98 struct dc_state *new_ctx,
99 struct dc_stream_state *dc_stream);
100
101void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
102
103bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);
104void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);
105int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
107
108#endif /* _DCN30_RESOURCE_H_ */
109

source code of linux/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h