1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_LINK_ENCODER__DCN31_H__
27#define __DC_LINK_ENCODER__DCN31_H__
28
29#include "dcn30/dcn30_dio_link_encoder.h"
30
31
32#define LE_DCN31_REG_LIST(id)\
33 LE_DCN3_REG_LIST(id),\
34 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
35 SR(DIO_LINKA_CNTL), \
36 SR(DIO_LINKB_CNTL), \
37 SR(DIO_LINKC_CNTL), \
38 SR(DIO_LINKD_CNTL), \
39 SR(DIO_LINKE_CNTL), \
40 SR(DIO_LINKF_CNTL)
41
42#define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \
43 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
44 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
45 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
46 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
47 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
48 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
49 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
50 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
51 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
52 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
53 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
54 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
55 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
56 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
57 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
58 LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
59 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
60 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
61 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\
62 LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
63 LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
64 LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
65
66#define DPCS_DCN31_REG_LIST(id) \
67 SRI(TMDS_CTL_BITS, DIG, id), \
68 SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
69 SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
70 SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
71 SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
72 SRI(RDPCSPIPE_PHY_CNTL6, RDPCSPIPE, id), \
73 SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
74 SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
75 SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
76 SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
77 SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
78 SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
79 SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
80 SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
81 SRI(RDPCSTX_CNTL, RDPCSTX, id), \
82 SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
83 SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
84 SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
85 SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
86 SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
87 SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
88 SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
89 SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
90 SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
91 SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
92 SR(RDPCSTX0_RDPCSTX_SCRATCH), \
93 SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
94 SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
95
96#define DPCS_DCN31_MASK_SH_LIST(mask_sh)\
97 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
98 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
99 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
100 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
101 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
102 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
103 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
104 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
105 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
106 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
107 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
108 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
109 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
110 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
111 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
112 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
113 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
114 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
115 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
116 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
117 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
118 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
119 LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
120 LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
121 LE_SF(RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
122 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
123 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
124 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
125 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
126 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
127 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
128 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
129 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
130 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
131 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
132 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
133 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
134 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
135 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
136 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
137 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
138 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
139 LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
140 LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
141 LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
142 LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
143 LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
144 LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
145 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
146 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
147 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
148 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
149 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
150 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
151 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
152 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
153 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
154 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
155 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
156 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
157 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
158 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
159 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
160 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
161 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
162 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
163 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
164 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
165 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
166 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
167 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
168 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
169 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
170 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
171 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
172 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
173 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
174 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
175 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
176 LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
177 LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
178 LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
179 LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
180 LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
181 LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
182 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
183 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
184 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
185 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
186 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
187 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
188 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
189 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
190 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
191 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
192 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
193 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
194 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
195 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
196 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
197 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
198 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
199 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh)
200
201#define DPCS_DCN314_REG_LIST(id) \
202 SRI(TMDS_CTL_BITS, DIG, id), \
203 SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
204 SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
205 SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
206 SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
207 SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
208 SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
209 SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
210 SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
211 SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
212 SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
213 SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
214 SRI(RDPCSTX_CNTL, RDPCSTX, id), \
215 SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
216 SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
217 SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
218 SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
219 SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
220 SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
221 SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
222 SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
223 SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
224 SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
225 SR(RDPCSTX0_RDPCSTX_SCRATCH), \
226 SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
227 SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
228
229void dcn31_link_encoder_construct(
230 struct dcn20_link_encoder *enc20,
231 const struct encoder_init_data *init_data,
232 const struct encoder_feature_support *enc_features,
233 const struct dcn10_link_enc_registers *link_regs,
234 const struct dcn10_link_enc_aux_registers *aux_regs,
235 const struct dcn10_link_enc_hpd_registers *hpd_regs,
236 const struct dcn10_link_enc_shift *link_shift,
237 const struct dcn10_link_enc_mask *link_mask);
238
239/*
240 * Create a minimal link encoder object with no dc_link object associated with it.
241 */
242void dcn31_link_encoder_construct_minimal(
243 struct dcn20_link_encoder *enc20,
244 struct dc_context *ctx,
245 const struct encoder_feature_support *enc_features,
246 const struct dcn10_link_enc_registers *link_regs,
247 enum engine_id eng_id);
248
249void dcn31_link_encoder_set_dio_phy_mux(
250 struct link_encoder *enc,
251 enum encoder_type_select sel,
252 uint32_t hpo_inst);
253
254/*
255 * Enable DP transmitter and its encoder.
256 */
257void dcn31_link_encoder_enable_dp_output(
258 struct link_encoder *enc,
259 const struct dc_link_settings *link_settings,
260 enum clock_source_id clock_source);
261
262/*
263 * Enable DP transmitter and its encoder in MST mode.
264 */
265void dcn31_link_encoder_enable_dp_mst_output(
266 struct link_encoder *enc,
267 const struct dc_link_settings *link_settings,
268 enum clock_source_id clock_source);
269
270/*
271 * Disable transmitter and its encoder.
272 */
273void dcn31_link_encoder_disable_output(
274 struct link_encoder *enc,
275 enum signal_type signal);
276
277/*
278 * Check whether USB-C DP Alt mode is disabled
279 */
280bool dcn31_link_encoder_is_in_alt_mode(
281 struct link_encoder *enc);
282
283void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
284 struct dc_link_settings *link_settings);
285
286#endif /* __DC_LINK_ENCODER__DCN31_H__ */
287

source code of linux/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h