| 1 | /* |
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| 2 | * Copyright 2020 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: AMD |
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| 23 | * |
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| 24 | */ |
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| 25 | |
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| 26 | #ifndef _DCN32_RESOURCE_H_ |
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| 27 | #define _DCN32_RESOURCE_H_ |
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| 28 | |
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| 29 | #include "core_types.h" |
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| 30 | |
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| 31 | #define DCN3_2_DEFAULT_DET_SIZE 256 |
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| 32 | #define DCN3_2_MAX_DET_SIZE 1152 |
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| 33 | #define DCN3_2_MIN_DET_SIZE 128 |
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| 34 | #define DCN3_2_MIN_COMPBUF_SIZE_KB 128 |
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| 35 | #define DCN3_2_DET_SEG_SIZE 64 |
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| 36 | #define DCN3_2_MALL_MBLK_SIZE_BYTES 65536 // 64 * 1024 |
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| 37 | #define DCN3_2_MBLK_WIDTH 128 |
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| 38 | #define DCN3_2_MBLK_HEIGHT_4BPE 128 |
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| 39 | #define DCN3_2_MBLK_HEIGHT_8BPE 64 |
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| 40 | #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq |
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| 41 | #define SUBVP_HIGH_REFRESH_LIST_LEN 4 |
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| 42 | #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800 |
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| 43 | #define DCN3_2_VMIN_DISPCLK_HZ 717000000 |
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| 44 | |
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| 45 | #define TO_DCN32_RES_POOL(pool)\ |
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| 46 | container_of(pool, struct dcn32_resource_pool, base) |
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| 47 | |
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| 48 | extern struct _vcs_dpi_ip_params_st dcn3_2_ip; |
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| 49 | extern struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc; |
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| 50 | |
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| 51 | struct subvp_high_refresh_list { |
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| 52 | int min_refresh; |
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| 53 | int max_refresh; |
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| 54 | struct resolution { |
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| 55 | int width; |
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| 56 | int height; |
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| 57 | } res[SUBVP_HIGH_REFRESH_LIST_LEN]; |
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| 58 | }; |
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| 59 | |
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| 60 | struct dcn32_resource_pool { |
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| 61 | struct resource_pool base; |
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| 62 | }; |
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| 63 | |
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| 64 | struct resource_pool *dcn32_create_resource_pool( |
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| 65 | const struct dc_init_data *init_data, |
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| 66 | struct dc *dc); |
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| 67 | |
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| 68 | struct panel_cntl *dcn32_panel_cntl_create( |
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| 69 | const struct panel_cntl_init_data *init_data); |
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| 70 | |
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| 71 | bool dcn32_acquire_post_bldn_3dlut( |
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| 72 | struct resource_context *res_ctx, |
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| 73 | const struct resource_pool *pool, |
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| 74 | int mpcc_id, |
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| 75 | struct dc_3dlut **lut, |
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| 76 | struct dc_transfer_func **shaper); |
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| 77 | |
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| 78 | bool dcn32_release_post_bldn_3dlut( |
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| 79 | struct resource_context *res_ctx, |
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| 80 | const struct resource_pool *pool, |
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| 81 | struct dc_3dlut **lut, |
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| 82 | struct dc_transfer_func **shaper); |
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| 83 | |
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| 84 | bool dcn32_remove_phantom_pipes(struct dc *dc, |
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| 85 | struct dc_state *context, bool fast_update); |
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| 86 | |
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| 87 | void dcn32_retain_phantom_pipes(struct dc *dc, |
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| 88 | struct dc_state *context); |
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| 89 | |
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| 90 | void dcn32_add_phantom_pipes(struct dc *dc, |
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| 91 | struct dc_state *context, |
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| 92 | display_e2e_pipe_params_st *pipes, |
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| 93 | unsigned int pipe_cnt, |
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| 94 | unsigned int index); |
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| 95 | |
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| 96 | bool dcn32_validate_bandwidth(struct dc *dc, |
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| 97 | struct dc_state *context, |
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| 98 | bool fast_validate); |
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| 99 | |
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| 100 | int dcn32_populate_dml_pipes_from_context( |
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| 101 | struct dc *dc, struct dc_state *context, |
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| 102 | display_e2e_pipe_params_st *pipes, |
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| 103 | bool fast_validate); |
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| 104 | |
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| 105 | void dcn32_calculate_wm_and_dlg( |
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| 106 | struct dc *dc, struct dc_state *context, |
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| 107 | display_e2e_pipe_params_st *pipes, |
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| 108 | int pipe_cnt, |
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| 109 | int vlevel); |
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| 110 | |
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| 111 | uint32_t dcn32_helper_mall_bytes_to_ways( |
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| 112 | struct dc *dc, |
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| 113 | uint32_t total_size_in_mall_bytes); |
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| 114 | |
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| 115 | uint32_t dcn32_helper_calculate_mall_bytes_for_cursor( |
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| 116 | struct dc *dc, |
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| 117 | struct pipe_ctx *pipe_ctx, |
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| 118 | bool ignore_cursor_buf); |
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| 119 | |
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| 120 | uint32_t dcn32_helper_calculate_num_ways_for_subvp( |
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| 121 | struct dc *dc, |
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| 122 | struct dc_state *context); |
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| 123 | |
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| 124 | void dcn32_merge_pipes_for_subvp(struct dc *dc, |
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| 125 | struct dc_state *context); |
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| 126 | |
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| 127 | bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc, |
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| 128 | struct dc_state *context); |
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| 129 | |
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| 130 | bool dcn32_subvp_in_use(struct dc *dc, |
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| 131 | struct dc_state *context); |
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| 132 | |
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| 133 | bool dcn32_mpo_in_use(struct dc_state *context); |
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| 134 | |
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| 135 | bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context); |
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| 136 | bool dcn32_is_center_timing(struct pipe_ctx *pipe); |
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| 137 | bool dcn32_is_psr_capable(struct pipe_ctx *pipe); |
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| 138 | |
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| 139 | struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( |
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| 140 | const struct dc_state *cur_ctx, |
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| 141 | struct dc_state *new_ctx, |
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| 142 | const struct resource_pool *pool, |
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| 143 | const struct pipe_ctx *opp_head_pipe); |
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| 144 | |
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| 145 | struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( |
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| 146 | const struct dc_state *cur_ctx, |
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| 147 | struct dc_state *new_ctx, |
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| 148 | const struct resource_pool *pool, |
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| 149 | const struct pipe_ctx *otg_master); |
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| 150 | |
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| 151 | void dcn32_release_pipe(struct dc_state *context, |
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| 152 | struct pipe_ctx *pipe, |
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| 153 | const struct resource_pool *pool); |
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| 154 | |
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| 155 | void dcn32_determine_det_override(struct dc *dc, |
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| 156 | struct dc_state *context, |
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| 157 | display_e2e_pipe_params_st *pipes); |
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| 158 | |
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| 159 | void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, |
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| 160 | display_e2e_pipe_params_st *pipes); |
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| 161 | |
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| 162 | void dcn32_save_mall_state(struct dc *dc, |
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| 163 | struct dc_state *context, |
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| 164 | struct mall_temp_config *temp_config); |
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| 165 | |
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| 166 | void dcn32_restore_mall_state(struct dc *dc, |
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| 167 | struct dc_state *context, |
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| 168 | struct mall_temp_config *temp_config); |
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| 169 | |
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| 170 | struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, const struct dc_state *context); |
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| 171 | |
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| 172 | bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe); |
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| 173 | |
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| 174 | bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe); |
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| 175 | |
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| 176 | unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans); |
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| 177 | |
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| 178 | double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context); |
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| 179 | |
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| 180 | bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height); |
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| 181 | |
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| 182 | bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context); |
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| 183 | |
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| 184 | bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel); |
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| 185 | |
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| 186 | /* definitions for run time init of reg offsets */ |
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| 187 | |
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| 188 | /* CLK SRC */ |
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| 189 | #define CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) \ |
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| 190 | SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \ |
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| 191 | SRII_ARR_2(PHASE, DP_DTO, 0, index), \ |
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| 192 | SRII_ARR_2(PHASE, DP_DTO, 1, index), \ |
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| 193 | SRII_ARR_2(PHASE, DP_DTO, 2, index), \ |
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| 194 | SRII_ARR_2(PHASE, DP_DTO, 3, index), \ |
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| 195 | SRII_ARR_2(MODULO, DP_DTO, 0, index), \ |
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| 196 | SRII_ARR_2(MODULO, DP_DTO, 1, index), \ |
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| 197 | SRII_ARR_2(MODULO, DP_DTO, 2, index), \ |
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| 198 | SRII_ARR_2(MODULO, DP_DTO, 3, index), \ |
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| 199 | SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \ |
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| 200 | SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \ |
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| 201 | SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \ |
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| 202 | SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index) |
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| 203 | |
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| 204 | /* ABM */ |
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| 205 | #define ABM_DCN32_REG_LIST_RI(id) \ |
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| 206 | SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ |
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| 207 | SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ |
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| 208 | SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ |
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| 209 | SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \ |
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| 210 | SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ |
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| 211 | SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ |
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| 212 | SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ |
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| 213 | SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \ |
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| 214 | SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ |
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| 215 | SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ |
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| 216 | SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ |
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| 217 | SRI_ARR(DC_ABM1_ACE_THRES_12, ABM, id), NBIO_SR_ARR(BIOS_SCRATCH_2, id) |
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| 218 | |
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| 219 | /* Audio */ |
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| 220 | #define AUD_COMMON_REG_LIST_RI(id) \ |
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| 221 | SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id), \ |
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| 222 | SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id), \ |
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| 223 | SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, id), \ |
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| 224 | SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, id), \ |
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| 225 | SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, id), \ |
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| 226 | SR_ARR(DCCG_AUDIO_DTO_SOURCE, id), SR_ARR(DCCG_AUDIO_DTO0_MODULE, id), \ |
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| 227 | SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id), \ |
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| 228 | SR_ARR(DCCG_AUDIO_DTO1_PHASE, id) \ |
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| 229 | |
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| 230 | /* VPG */ |
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| 231 | |
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| 232 | #define VPG_DCN3_REG_LIST_RI(id) \ |
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| 233 | SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \ |
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| 234 | SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \ |
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| 235 | SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \ |
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| 236 | SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \ |
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| 237 | SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id) |
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| 238 | |
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| 239 | /* AFMT */ |
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| 240 | #define AFMT_DCN3_REG_LIST_RI(id) \ |
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| 241 | SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \ |
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| 242 | SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \ |
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| 243 | SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \ |
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| 244 | SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \ |
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| 245 | SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \ |
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| 246 | SRI_ARR(AFMT_60958_0, AFMT, id), SRI_ARR(AFMT_60958_1, AFMT, id), \ |
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| 247 | SRI_ARR(AFMT_60958_2, AFMT, id), SRI_ARR(AFMT_MEM_PWR, AFMT, id) |
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| 248 | |
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| 249 | /* APG */ |
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| 250 | #define APG_DCN31_REG_LIST_RI(id) \ |
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| 251 | SRI_ARR(APG_CONTROL, APG, id), SRI_ARR(APG_CONTROL2, APG, id), \ |
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| 252 | SRI_ARR(APG_MEM_PWR, APG, id), SRI_ARR(APG_DBG_GEN_CONTROL, APG, id) |
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| 253 | |
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| 254 | /* Stream encoder */ |
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| 255 | #define SE_DCN32_REG_LIST_RI(id) \ |
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| 256 | SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id), \ |
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| 257 | SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \ |
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| 258 | SRI_ARR(HDMI_GC, DIG, id), \ |
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| 259 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ |
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| 260 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ |
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| 261 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ |
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| 262 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ |
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| 263 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ |
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| 264 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ |
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| 265 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ |
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| 266 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ |
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| 267 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ |
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| 268 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ |
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| 269 | SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ |
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| 270 | SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \ |
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| 271 | SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id), \ |
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| 272 | SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \ |
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| 273 | SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \ |
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| 274 | SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \ |
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| 275 | SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \ |
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| 276 | SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \ |
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| 277 | SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \ |
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| 278 | SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \ |
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| 279 | SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \ |
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| 280 | SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \ |
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| 281 | SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \ |
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| 282 | SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \ |
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| 283 | SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \ |
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| 284 | SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \ |
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| 285 | SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \ |
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| 286 | SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \ |
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| 287 | SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \ |
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| 288 | SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \ |
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| 289 | SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \ |
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| 290 | SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \ |
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| 291 | SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id), \ |
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| 292 | SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ |
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| 293 | SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ |
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| 294 | SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \ |
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| 295 | SRI_ARR(DME_CONTROL, DME, id), \ |
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| 296 | SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ |
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| 297 | SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ |
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| 298 | SRI_ARR(DIG_FE_CNTL, DIG, id), SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \ |
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| 299 | SRI_ARR(DIG_FIFO_CTRL0, DIG, id) |
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| 300 | |
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| 301 | /* Aux regs */ |
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| 302 | |
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| 303 | #define AUX_REG_LIST_RI(id) \ |
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| 304 | SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \ |
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| 305 | SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id) |
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| 306 | |
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| 307 | #define DCN2_AUX_REG_LIST_RI(id) \ |
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| 308 | AUX_REG_LIST_RI(id), SRI_ARR(AUX_DPHY_TX_CONTROL, DP_AUX, id) |
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| 309 | |
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| 310 | /* HDP */ |
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| 311 | #define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id) |
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| 312 | |
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| 313 | /* Link encoder */ |
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| 314 | #define LE_DCN3_REG_LIST_RI(id) \ |
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| 315 | SRI_ARR(DIG_BE_CNTL, DIG, id), SRI_ARR(DIG_BE_EN_CNTL, DIG, id), \ |
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| 316 | SRI_ARR(TMDS_CTL_BITS, DIG, id), \ |
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| 317 | SRI_ARR(TMDS_DCBALANCER_CONTROL, DIG, id), SRI_ARR(DP_CONFIG, DP, id), \ |
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| 318 | SRI_ARR(DP_DPHY_CNTL, DP, id), SRI_ARR(DP_DPHY_PRBS_CNTL, DP, id), \ |
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| 319 | SRI_ARR(DP_DPHY_SCRAM_CNTL, DP, id), SRI_ARR(DP_DPHY_SYM0, DP, id), \ |
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| 320 | SRI_ARR(DP_DPHY_SYM1, DP, id), SRI_ARR(DP_DPHY_SYM2, DP, id), \ |
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| 321 | SRI_ARR(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ |
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| 322 | SRI_ARR(DP_LINK_CNTL, DP, id), SRI_ARR(DP_LINK_FRAMING_CNTL, DP, id), \ |
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| 323 | SRI_ARR(DP_MSE_SAT0, DP, id), SRI_ARR(DP_MSE_SAT1, DP, id), \ |
|---|
| 324 | SRI_ARR(DP_MSE_SAT2, DP, id), SRI_ARR(DP_MSE_SAT_UPDATE, DP, id), \ |
|---|
| 325 | SRI_ARR(DP_SEC_CNTL, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \ |
|---|
| 326 | SRI_ARR(DP_DPHY_FAST_TRAINING, DP, id), SRI_ARR(DP_SEC_CNTL1, DP, id), \ |
|---|
| 327 | SRI_ARR(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ |
|---|
| 328 | SRI_ARR(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) |
|---|
| 329 | |
|---|
| 330 | #define LE_DCN31_REG_LIST_RI(id) \ |
|---|
| 331 | LE_DCN3_REG_LIST_RI(id), SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \ |
|---|
| 332 | SR_ARR(DIO_LINKA_CNTL, id), SR_ARR(DIO_LINKB_CNTL, id), \ |
|---|
| 333 | SR_ARR(DIO_LINKC_CNTL, id), SR_ARR(DIO_LINKD_CNTL, id), \ |
|---|
| 334 | SR_ARR(DIO_LINKE_CNTL, id), SR_ARR(DIO_LINKF_CNTL, id) |
|---|
| 335 | |
|---|
| 336 | #define UNIPHY_DCN2_REG_LIST_RI(id, phyid) \ |
|---|
| 337 | SRI_ARR_ALPHABET(CLOCK_ENABLE, SYMCLK, id, phyid), \ |
|---|
| 338 | SRI_ARR_ALPHABET(CHANNEL_XBAR_CNTL, UNIPHY, id, phyid) |
|---|
| 339 | |
|---|
| 340 | /* HPO DP stream encoder */ |
|---|
| 341 | #define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) \ |
|---|
| 342 | SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \ |
|---|
| 343 | SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \ |
|---|
| 344 | SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \ |
|---|
| 345 | SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \ |
|---|
| 346 | SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \ |
|---|
| 347 | SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \ |
|---|
| 348 | SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \ |
|---|
| 349 | SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \ |
|---|
| 350 | SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 351 | SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \ |
|---|
| 352 | SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 353 | SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \ |
|---|
| 354 | SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \ |
|---|
| 355 | SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \ |
|---|
| 356 | SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \ |
|---|
| 357 | SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \ |
|---|
| 358 | SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \ |
|---|
| 359 | SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \ |
|---|
| 360 | SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \ |
|---|
| 361 | SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \ |
|---|
| 362 | SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 363 | SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 364 | SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 365 | SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 366 | SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 367 | SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 368 | SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \ |
|---|
| 369 | SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \ |
|---|
| 370 | SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \ |
|---|
| 371 | SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \ |
|---|
| 372 | SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \ |
|---|
| 373 | SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 374 | SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id), \ |
|---|
| 375 | SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \ |
|---|
| 376 | SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id) |
|---|
| 377 | |
|---|
| 378 | /* HPO DP link encoder regs */ |
|---|
| 379 | #define DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) \ |
|---|
| 380 | SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \ |
|---|
| 381 | SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \ |
|---|
| 382 | SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \ |
|---|
| 383 | SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \ |
|---|
| 384 | SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \ |
|---|
| 385 | SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \ |
|---|
| 386 | SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \ |
|---|
| 387 | SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \ |
|---|
| 388 | SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \ |
|---|
| 389 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \ |
|---|
| 390 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \ |
|---|
| 391 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \ |
|---|
| 392 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \ |
|---|
| 393 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \ |
|---|
| 394 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \ |
|---|
| 395 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \ |
|---|
| 396 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \ |
|---|
| 397 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \ |
|---|
| 398 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \ |
|---|
| 399 | SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \ |
|---|
| 400 | SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \ |
|---|
| 401 | SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \ |
|---|
| 402 | SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \ |
|---|
| 403 | SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \ |
|---|
| 404 | SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \ |
|---|
| 405 | SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \ |
|---|
| 406 | SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \ |
|---|
| 407 | SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \ |
|---|
| 408 | SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id) |
|---|
| 409 | |
|---|
| 410 | /* DPP */ |
|---|
| 411 | #define DPP_REG_LIST_DCN30_COMMON_RI(id) \ |
|---|
| 412 | SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \ |
|---|
| 413 | SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \ |
|---|
| 414 | SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \ |
|---|
| 415 | SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \ |
|---|
| 416 | SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ |
|---|
| 417 | SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ |
|---|
| 418 | SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \ |
|---|
| 419 | SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \ |
|---|
| 420 | SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \ |
|---|
| 421 | SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \ |
|---|
| 422 | SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \ |
|---|
| 423 | SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \ |
|---|
| 424 | SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \ |
|---|
| 425 | SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \ |
|---|
| 426 | SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \ |
|---|
| 427 | SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \ |
|---|
| 428 | SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \ |
|---|
| 429 | SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \ |
|---|
| 430 | SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \ |
|---|
| 431 | SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \ |
|---|
| 432 | SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \ |
|---|
| 433 | SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \ |
|---|
| 434 | SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \ |
|---|
| 435 | SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \ |
|---|
| 436 | SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \ |
|---|
| 437 | SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \ |
|---|
| 438 | SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \ |
|---|
| 439 | SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \ |
|---|
| 440 | SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \ |
|---|
| 441 | SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \ |
|---|
| 442 | SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \ |
|---|
| 443 | SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \ |
|---|
| 444 | SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \ |
|---|
| 445 | SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \ |
|---|
| 446 | SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \ |
|---|
| 447 | SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \ |
|---|
| 448 | SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \ |
|---|
| 449 | SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \ |
|---|
| 450 | SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \ |
|---|
| 451 | SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \ |
|---|
| 452 | SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \ |
|---|
| 453 | SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \ |
|---|
| 454 | SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \ |
|---|
| 455 | SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \ |
|---|
| 456 | SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \ |
|---|
| 457 | SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \ |
|---|
| 458 | SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \ |
|---|
| 459 | SRI_ARR(CM_GAMUT_REMAP_CONTROL, CM, id), \ |
|---|
| 460 | SRI_ARR(CM_GAMUT_REMAP_C11_C12, CM, id), \ |
|---|
| 461 | SRI_ARR(CM_GAMUT_REMAP_C13_C14, CM, id), \ |
|---|
| 462 | SRI_ARR(CM_GAMUT_REMAP_C21_C22, CM, id), \ |
|---|
| 463 | SRI_ARR(CM_GAMUT_REMAP_C23_C24, CM, id), \ |
|---|
| 464 | SRI_ARR(CM_GAMUT_REMAP_C31_C32, CM, id), \ |
|---|
| 465 | SRI_ARR(CM_GAMUT_REMAP_C33_C34, CM, id), \ |
|---|
| 466 | SRI_ARR(CM_GAMUT_REMAP_B_C11_C12, CM, id), \ |
|---|
| 467 | SRI_ARR(CM_GAMUT_REMAP_B_C13_C14, CM, id), \ |
|---|
| 468 | SRI_ARR(CM_GAMUT_REMAP_B_C21_C22, CM, id), \ |
|---|
| 469 | SRI_ARR(CM_GAMUT_REMAP_B_C23_C24, CM, id), \ |
|---|
| 470 | SRI_ARR(CM_GAMUT_REMAP_B_C31_C32, CM, id), \ |
|---|
| 471 | SRI_ARR(CM_GAMUT_REMAP_B_C33_C34, CM, id), \ |
|---|
| 472 | SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ |
|---|
| 473 | SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ |
|---|
| 474 | SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \ |
|---|
| 475 | SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \ |
|---|
| 476 | SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \ |
|---|
| 477 | SRI_ARR(DSCL_CONTROL, DSCL, id), \ |
|---|
| 478 | SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \ |
|---|
| 479 | SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ |
|---|
| 480 | SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ |
|---|
| 481 | SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \ |
|---|
| 482 | SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ |
|---|
| 483 | SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ |
|---|
| 484 | SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \ |
|---|
| 485 | SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \ |
|---|
| 486 | SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \ |
|---|
| 487 | SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \ |
|---|
| 488 | SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \ |
|---|
| 489 | SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \ |
|---|
| 490 | SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \ |
|---|
| 491 | SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \ |
|---|
| 492 | SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \ |
|---|
| 493 | SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \ |
|---|
| 494 | SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \ |
|---|
| 495 | SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \ |
|---|
| 496 | SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \ |
|---|
| 497 | SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \ |
|---|
| 498 | SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \ |
|---|
| 499 | SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \ |
|---|
| 500 | SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \ |
|---|
| 501 | SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \ |
|---|
| 502 | SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \ |
|---|
| 503 | SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \ |
|---|
| 504 | SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ |
|---|
| 505 | SRI_ARR(CURSOR0_CONTROL, CNVC_CUR, id), \ |
|---|
| 506 | SRI_ARR(CURSOR0_COLOR0, CNVC_CUR, id), \ |
|---|
| 507 | SRI_ARR(CURSOR0_COLOR1, CNVC_CUR, id), \ |
|---|
| 508 | SRI_ARR(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \ |
|---|
| 509 | SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \ |
|---|
| 510 | SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ |
|---|
| 511 | SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id), \ |
|---|
| 512 | SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \ |
|---|
| 513 | SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \ |
|---|
| 514 | SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \ |
|---|
| 515 | SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \ |
|---|
| 516 | SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \ |
|---|
| 517 | SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \ |
|---|
| 518 | SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ |
|---|
| 519 | SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ |
|---|
| 520 | SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \ |
|---|
| 521 | SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \ |
|---|
| 522 | SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \ |
|---|
| 523 | SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ |
|---|
| 524 | SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \ |
|---|
| 525 | SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \ |
|---|
| 526 | SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id) |
|---|
| 527 | |
|---|
| 528 | /* OPP */ |
|---|
| 529 | #define OPP_REG_LIST_DCN_RI(id) \ |
|---|
| 530 | SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \ |
|---|
| 531 | SRI_ARR(FMT_DITHER_RAND_R_SEED, FMT, id), \ |
|---|
| 532 | SRI_ARR(FMT_DITHER_RAND_G_SEED, FMT, id), \ |
|---|
| 533 | SRI_ARR(FMT_DITHER_RAND_B_SEED, FMT, id), \ |
|---|
| 534 | SRI_ARR(FMT_CLAMP_CNTL, FMT, id), \ |
|---|
| 535 | SRI_ARR(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ |
|---|
| 536 | SRI_ARR(FMT_MAP420_MEMORY_CONTROL, FMT, id), \ |
|---|
| 537 | SRI_ARR(OPPBUF_CONTROL, OPPBUF, id), \ |
|---|
| 538 | SRI_ARR(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \ |
|---|
| 539 | SRI_ARR(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \ |
|---|
| 540 | SRI_ARR(OPP_PIPE_CONTROL, OPP_PIPE, id) \ |
|---|
| 541 | |
|---|
| 542 | #define OPP_REG_LIST_DCN10_RI(id) OPP_REG_LIST_DCN_RI(id) |
|---|
| 543 | |
|---|
| 544 | #define OPP_DPG_REG_LIST_RI(id) \ |
|---|
| 545 | SRI_ARR(DPG_CONTROL, DPG, id), SRI_ARR(DPG_DIMENSIONS, DPG, id), \ |
|---|
| 546 | SRI_ARR(DPG_OFFSET_SEGMENT, DPG, id), SRI_ARR(DPG_COLOUR_B_CB, DPG, id), \ |
|---|
| 547 | SRI_ARR(DPG_COLOUR_G_Y, DPG, id), SRI_ARR(DPG_COLOUR_R_CR, DPG, id), \ |
|---|
| 548 | SRI_ARR(DPG_RAMP_CONTROL, DPG, id), SRI_ARR(DPG_STATUS, DPG, id) |
|---|
| 549 | |
|---|
| 550 | #define OPP_REG_LIST_DCN30_RI(id) \ |
|---|
| 551 | OPP_REG_LIST_DCN10_RI(id), OPP_DPG_REG_LIST_RI(id), \ |
|---|
| 552 | SRI_ARR(FMT_422_CONTROL, FMT, id) |
|---|
| 553 | |
|---|
| 554 | /* Aux engine regs */ |
|---|
| 555 | #define AUX_COMMON_REG_LIST0_RI(id) \ |
|---|
| 556 | SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_ARB_CONTROL, DP_AUX, id), \ |
|---|
| 557 | SRI_ARR(AUX_SW_DATA, DP_AUX, id), SRI_ARR(AUX_SW_CONTROL, DP_AUX, id), \ |
|---|
| 558 | SRI_ARR(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ |
|---|
| 559 | SRI_ARR(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \ |
|---|
| 560 | SRI_ARR(AUX_SW_STATUS, DP_AUX, id) |
|---|
| 561 | |
|---|
| 562 | /* DWBC */ |
|---|
| 563 | #define DWBC_COMMON_REG_LIST_DCN30_RI(id) \ |
|---|
| 564 | SR_ARR(DWB_ENABLE_CLK_CTRL, id), SR_ARR(DWB_MEM_PWR_CTRL, id), \ |
|---|
| 565 | SR_ARR(FC_MODE_CTRL, id), SR_ARR(FC_FLOW_CTRL, id), \ |
|---|
| 566 | SR_ARR(FC_WINDOW_START, id), SR_ARR(FC_WINDOW_SIZE, id), \ |
|---|
| 567 | SR_ARR(FC_SOURCE_SIZE, id), SR_ARR(DWB_UPDATE_CTRL, id), \ |
|---|
| 568 | SR_ARR(DWB_CRC_CTRL, id), SR_ARR(DWB_CRC_MASK_R_G, id), \ |
|---|
| 569 | SR_ARR(DWB_CRC_MASK_B_A, id), SR_ARR(DWB_CRC_VAL_R_G, id), \ |
|---|
| 570 | SR_ARR(DWB_CRC_VAL_B_A, id), SR_ARR(DWB_OUT_CTRL, id), \ |
|---|
| 571 | SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, id), \ |
|---|
| 572 | SR_ARR(DWB_MMHUBBUB_BACKPRESSURE_CNT, id), \ |
|---|
| 573 | SR_ARR(DWB_HOST_READ_CONTROL, id), SR_ARR(DWB_SOFT_RESET, id), \ |
|---|
| 574 | SR_ARR(DWB_HDR_MULT_COEF, id), SR_ARR(DWB_GAMUT_REMAP_MODE, id), \ |
|---|
| 575 | SR_ARR(DWB_GAMUT_REMAP_COEF_FORMAT, id), \ |
|---|
| 576 | SR_ARR(DWB_GAMUT_REMAPA_C11_C12, id), \ |
|---|
| 577 | SR_ARR(DWB_GAMUT_REMAPA_C13_C14, id), \ |
|---|
| 578 | SR_ARR(DWB_GAMUT_REMAPA_C21_C22, id), \ |
|---|
| 579 | SR_ARR(DWB_GAMUT_REMAPA_C23_C24, id), \ |
|---|
| 580 | SR_ARR(DWB_GAMUT_REMAPA_C31_C32, id), \ |
|---|
| 581 | SR_ARR(DWB_GAMUT_REMAPA_C33_C34, id), \ |
|---|
| 582 | SR_ARR(DWB_GAMUT_REMAPB_C11_C12, id), \ |
|---|
| 583 | SR_ARR(DWB_GAMUT_REMAPB_C13_C14, id), \ |
|---|
| 584 | SR_ARR(DWB_GAMUT_REMAPB_C21_C22, id), \ |
|---|
| 585 | SR_ARR(DWB_GAMUT_REMAPB_C23_C24, id), \ |
|---|
| 586 | SR_ARR(DWB_GAMUT_REMAPB_C31_C32, id), \ |
|---|
| 587 | SR_ARR(DWB_GAMUT_REMAPB_C33_C34, id), SR_ARR(DWB_OGAM_CONTROL, id), \ |
|---|
| 588 | SR_ARR(DWB_OGAM_LUT_INDEX, id), SR_ARR(DWB_OGAM_LUT_DATA, id), \ |
|---|
| 589 | SR_ARR(DWB_OGAM_LUT_CONTROL, id), \ |
|---|
| 590 | SR_ARR(DWB_OGAM_RAMA_START_CNTL_B, id), \ |
|---|
| 591 | SR_ARR(DWB_OGAM_RAMA_START_CNTL_G, id), \ |
|---|
| 592 | SR_ARR(DWB_OGAM_RAMA_START_CNTL_R, id), \ |
|---|
| 593 | SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_B, id), \ |
|---|
| 594 | SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B, id), \ |
|---|
| 595 | SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_G, id), \ |
|---|
| 596 | SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G, id), \ |
|---|
| 597 | SR_ARR(DWB_OGAM_RAMA_START_BASE_CNTL_R, id), \ |
|---|
| 598 | SR_ARR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R, id), \ |
|---|
| 599 | SR_ARR(DWB_OGAM_RAMA_END_CNTL1_B, id), \ |
|---|
| 600 | SR_ARR(DWB_OGAM_RAMA_END_CNTL2_B, id), \ |
|---|
| 601 | SR_ARR(DWB_OGAM_RAMA_END_CNTL1_G, id), \ |
|---|
| 602 | SR_ARR(DWB_OGAM_RAMA_END_CNTL2_G, id), \ |
|---|
| 603 | SR_ARR(DWB_OGAM_RAMA_END_CNTL1_R, id), \ |
|---|
| 604 | SR_ARR(DWB_OGAM_RAMA_END_CNTL2_R, id), \ |
|---|
| 605 | SR_ARR(DWB_OGAM_RAMA_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMA_OFFSET_G, id), \ |
|---|
| 606 | SR_ARR(DWB_OGAM_RAMA_OFFSET_R, id), \ |
|---|
| 607 | SR_ARR(DWB_OGAM_RAMA_REGION_0_1, id), \ |
|---|
| 608 | SR_ARR(DWB_OGAM_RAMA_REGION_2_3, id), \ |
|---|
| 609 | SR_ARR(DWB_OGAM_RAMA_REGION_4_5, id), \ |
|---|
| 610 | SR_ARR(DWB_OGAM_RAMA_REGION_6_7, id), \ |
|---|
| 611 | SR_ARR(DWB_OGAM_RAMA_REGION_8_9, id), \ |
|---|
| 612 | SR_ARR(DWB_OGAM_RAMA_REGION_10_11, id), \ |
|---|
| 613 | SR_ARR(DWB_OGAM_RAMA_REGION_12_13, id), \ |
|---|
| 614 | SR_ARR(DWB_OGAM_RAMA_REGION_14_15, id), \ |
|---|
| 615 | SR_ARR(DWB_OGAM_RAMA_REGION_16_17, id), \ |
|---|
| 616 | SR_ARR(DWB_OGAM_RAMA_REGION_18_19, id), \ |
|---|
| 617 | SR_ARR(DWB_OGAM_RAMA_REGION_20_21, id), \ |
|---|
| 618 | SR_ARR(DWB_OGAM_RAMA_REGION_22_23, id), \ |
|---|
| 619 | SR_ARR(DWB_OGAM_RAMA_REGION_24_25, id), \ |
|---|
| 620 | SR_ARR(DWB_OGAM_RAMA_REGION_26_27, id), \ |
|---|
| 621 | SR_ARR(DWB_OGAM_RAMA_REGION_28_29, id), \ |
|---|
| 622 | SR_ARR(DWB_OGAM_RAMA_REGION_30_31, id), \ |
|---|
| 623 | SR_ARR(DWB_OGAM_RAMA_REGION_32_33, id), \ |
|---|
| 624 | SR_ARR(DWB_OGAM_RAMB_START_CNTL_B, id), \ |
|---|
| 625 | SR_ARR(DWB_OGAM_RAMB_START_CNTL_G, id), \ |
|---|
| 626 | SR_ARR(DWB_OGAM_RAMB_START_CNTL_R, id), \ |
|---|
| 627 | SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_B, id), \ |
|---|
| 628 | SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B, id), \ |
|---|
| 629 | SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_G, id), \ |
|---|
| 630 | SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G, id), \ |
|---|
| 631 | SR_ARR(DWB_OGAM_RAMB_START_BASE_CNTL_R, id), \ |
|---|
| 632 | SR_ARR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R, id), \ |
|---|
| 633 | SR_ARR(DWB_OGAM_RAMB_END_CNTL1_B, id), \ |
|---|
| 634 | SR_ARR(DWB_OGAM_RAMB_END_CNTL2_B, id), \ |
|---|
| 635 | SR_ARR(DWB_OGAM_RAMB_END_CNTL1_G, id), \ |
|---|
| 636 | SR_ARR(DWB_OGAM_RAMB_END_CNTL2_G, id), \ |
|---|
| 637 | SR_ARR(DWB_OGAM_RAMB_END_CNTL1_R, id), \ |
|---|
| 638 | SR_ARR(DWB_OGAM_RAMB_END_CNTL2_R, id), \ |
|---|
| 639 | SR_ARR(DWB_OGAM_RAMB_OFFSET_B, id), SR_ARR(DWB_OGAM_RAMB_OFFSET_G, id), \ |
|---|
| 640 | SR_ARR(DWB_OGAM_RAMB_OFFSET_R, id), \ |
|---|
| 641 | SR_ARR(DWB_OGAM_RAMB_REGION_0_1, id), \ |
|---|
| 642 | SR_ARR(DWB_OGAM_RAMB_REGION_2_3, id), \ |
|---|
| 643 | SR_ARR(DWB_OGAM_RAMB_REGION_4_5, id), \ |
|---|
| 644 | SR_ARR(DWB_OGAM_RAMB_REGION_6_7, id), \ |
|---|
| 645 | SR_ARR(DWB_OGAM_RAMB_REGION_8_9, id), \ |
|---|
| 646 | SR_ARR(DWB_OGAM_RAMB_REGION_10_11, id), \ |
|---|
| 647 | SR_ARR(DWB_OGAM_RAMB_REGION_12_13, id), \ |
|---|
| 648 | SR_ARR(DWB_OGAM_RAMB_REGION_14_15, id), \ |
|---|
| 649 | SR_ARR(DWB_OGAM_RAMB_REGION_16_17, id), \ |
|---|
| 650 | SR_ARR(DWB_OGAM_RAMB_REGION_18_19, id), \ |
|---|
| 651 | SR_ARR(DWB_OGAM_RAMB_REGION_20_21, id), \ |
|---|
| 652 | SR_ARR(DWB_OGAM_RAMB_REGION_22_23, id), \ |
|---|
| 653 | SR_ARR(DWB_OGAM_RAMB_REGION_24_25, id), \ |
|---|
| 654 | SR_ARR(DWB_OGAM_RAMB_REGION_26_27, id), \ |
|---|
| 655 | SR_ARR(DWB_OGAM_RAMB_REGION_28_29, id), \ |
|---|
| 656 | SR_ARR(DWB_OGAM_RAMB_REGION_30_31, id), \ |
|---|
| 657 | SR_ARR(DWB_OGAM_RAMB_REGION_32_33, id) |
|---|
| 658 | |
|---|
| 659 | /* MCIF */ |
|---|
| 660 | |
|---|
| 661 | #define MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst) \ |
|---|
| 662 | SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \ |
|---|
| 663 | SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \ |
|---|
| 664 | SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \ |
|---|
| 665 | SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \ |
|---|
| 666 | SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \ |
|---|
| 667 | SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \ |
|---|
| 668 | SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \ |
|---|
| 669 | SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \ |
|---|
| 670 | SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \ |
|---|
| 671 | SRI2_ARR(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst), \ |
|---|
| 672 | SRI2_ARR(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst), \ |
|---|
| 673 | SRI2_ARR(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst), \ |
|---|
| 674 | SRI2_ARR(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst), \ |
|---|
| 675 | SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst), \ |
|---|
| 676 | SRI2_ARR(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst), \ |
|---|
| 677 | SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst), \ |
|---|
| 678 | SRI2_ARR(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst), \ |
|---|
| 679 | SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst), \ |
|---|
| 680 | SRI2_ARR(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst), \ |
|---|
| 681 | SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst), \ |
|---|
| 682 | SRI2_ARR(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst), \ |
|---|
| 683 | SRI2_ARR(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst), \ |
|---|
| 684 | SRI2_ARR(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MMHUBBUB, inst), \ |
|---|
| 685 | SRI2_ARR(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst), \ |
|---|
| 686 | SRI2_ARR(MCIF_WB_WATERMARK, MMHUBBUB, inst), \ |
|---|
| 687 | SRI2_ARR(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst), \ |
|---|
| 688 | SRI2_ARR(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst), \ |
|---|
| 689 | SRI2_ARR(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst), \ |
|---|
| 690 | SRI2_ARR(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst), \ |
|---|
| 691 | SRI2_ARR(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst), \ |
|---|
| 692 | SRI2_ARR(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst), \ |
|---|
| 693 | SRI2_ARR(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst), \ |
|---|
| 694 | SRI2_ARR(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst), \ |
|---|
| 695 | SRI2_ARR(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst), \ |
|---|
| 696 | SRI2_ARR(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst), \ |
|---|
| 697 | SRI2_ARR(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst), \ |
|---|
| 698 | SRI2_ARR(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst), \ |
|---|
| 699 | SRI2_ARR(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst), \ |
|---|
| 700 | SRI2_ARR(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst), \ |
|---|
| 701 | SRI2_ARR(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst), \ |
|---|
| 702 | SRI2_ARR(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst), \ |
|---|
| 703 | SRI2_ARR(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst), \ |
|---|
| 704 | SRI2_ARR(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst), \ |
|---|
| 705 | SRI2_ARR(MMHUBBUB_MEM_PWR_CNTL, MMHUBBUB, inst), \ |
|---|
| 706 | SRI2_ARR(MMHUBBUB_WARMUP_ADDR_REGION, MMHUBBUB, inst), \ |
|---|
| 707 | SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, MMHUBBUB, inst), \ |
|---|
| 708 | SRI2_ARR(MMHUBBUB_WARMUP_BASE_ADDR_LOW, MMHUBBUB, inst), \ |
|---|
| 709 | SRI2_ARR(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB, inst) |
|---|
| 710 | |
|---|
| 711 | /* DSC */ |
|---|
| 712 | |
|---|
| 713 | #define DSC_REG_LIST_DCN20_RI(id) \ |
|---|
| 714 | SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \ |
|---|
| 715 | SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id), \ |
|---|
| 716 | SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id), \ |
|---|
| 717 | SRI_ARR(DSCC_STATUS, DSCC, id), \ |
|---|
| 718 | SRI_ARR(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id), \ |
|---|
| 719 | SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \ |
|---|
| 720 | SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id), \ |
|---|
| 721 | SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id), \ |
|---|
| 722 | SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id), \ |
|---|
| 723 | SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id), \ |
|---|
| 724 | SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id), \ |
|---|
| 725 | SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id), \ |
|---|
| 726 | SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id), \ |
|---|
| 727 | SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id), \ |
|---|
| 728 | SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id), \ |
|---|
| 729 | SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id), \ |
|---|
| 730 | SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id), \ |
|---|
| 731 | SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id), \ |
|---|
| 732 | SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id), \ |
|---|
| 733 | SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id), \ |
|---|
| 734 | SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id), \ |
|---|
| 735 | SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id), \ |
|---|
| 736 | SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id), \ |
|---|
| 737 | SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id), \ |
|---|
| 738 | SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id), \ |
|---|
| 739 | SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id), \ |
|---|
| 740 | SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id), \ |
|---|
| 741 | SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id), \ |
|---|
| 742 | SRI_ARR(DSCC_MEM_POWER_CONTROL, DSCC, id), \ |
|---|
| 743 | SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id), \ |
|---|
| 744 | SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id), \ |
|---|
| 745 | SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id), \ |
|---|
| 746 | SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id), \ |
|---|
| 747 | SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id), \ |
|---|
| 748 | SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id), \ |
|---|
| 749 | SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id), \ |
|---|
| 750 | SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id), \ |
|---|
| 751 | SRI_ARR(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 752 | SRI_ARR(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 753 | SRI_ARR(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 754 | SRI_ARR(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 755 | SRI_ARR(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 756 | SRI_ARR(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 757 | SRI_ARR(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 758 | SRI_ARR(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id), \ |
|---|
| 759 | SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id), \ |
|---|
| 760 | SRI_ARR(DSCCIF_CONFIG1, DSCCIF, id), \ |
|---|
| 761 | SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id) |
|---|
| 762 | |
|---|
| 763 | /* MPC */ |
|---|
| 764 | |
|---|
| 765 | #define MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst) \ |
|---|
| 766 | SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst) |
|---|
| 767 | |
|---|
| 768 | #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst) \ |
|---|
| 769 | SRII(MUX, MPC_OUT, inst), VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst) |
|---|
| 770 | |
|---|
| 771 | #define MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst) \ |
|---|
| 772 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(CSC_MODE, MPC_OUT, inst), \ |
|---|
| 773 | SRII(CSC_C11_C12_A, MPC_OUT, inst), SRII(CSC_C33_C34_A, MPC_OUT, inst), \ |
|---|
| 774 | SRII(CSC_C11_C12_B, MPC_OUT, inst), SRII(CSC_C33_C34_B, MPC_OUT, inst), \ |
|---|
| 775 | SRII(DENORM_CONTROL, MPC_OUT, inst), \ |
|---|
| 776 | SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst), \ |
|---|
| 777 | SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), SR(MPC_OUT_CSC_COEF_FORMAT) |
|---|
| 778 | |
|---|
| 779 | #define MPC_COMMON_REG_LIST_DCN1_0_RI(inst) \ |
|---|
| 780 | SRII(MPCC_TOP_SEL, MPCC, inst), SRII(MPCC_BOT_SEL, MPCC, inst), \ |
|---|
| 781 | SRII(MPCC_CONTROL, MPCC, inst), SRII(MPCC_STATUS, MPCC, inst), \ |
|---|
| 782 | SRII(MPCC_OPP_ID, MPCC, inst), SRII(MPCC_BG_G_Y, MPCC, inst), \ |
|---|
| 783 | SRII(MPCC_BG_R_CR, MPCC, inst), SRII(MPCC_BG_B_CB, MPCC, inst), \ |
|---|
| 784 | SRII(MPCC_SM_CONTROL, MPCC, inst), \ |
|---|
| 785 | SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst) |
|---|
| 786 | |
|---|
| 787 | #define MPC_REG_LIST_DCN3_0_RI(inst) \ |
|---|
| 788 | MPC_COMMON_REG_LIST_DCN1_0_RI(inst), SRII(MPCC_TOP_GAIN, MPCC, inst), \ |
|---|
| 789 | SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst), \ |
|---|
| 790 | SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst), \ |
|---|
| 791 | SRII(MPCC_MEM_PWR_CTRL, MPCC, inst), \ |
|---|
| 792 | SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst), \ |
|---|
| 793 | SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \ |
|---|
| 794 | SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst), \ |
|---|
| 795 | SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst), \ |
|---|
| 796 | SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst), \ |
|---|
| 797 | SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst), \ |
|---|
| 798 | SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst), \ |
|---|
| 799 | SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst), \ |
|---|
| 800 | SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst), \ |
|---|
| 801 | SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst), \ |
|---|
| 802 | SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst), \ |
|---|
| 803 | SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst), \ |
|---|
| 804 | SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst), \ |
|---|
| 805 | SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst), \ |
|---|
| 806 | SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst), \ |
|---|
| 807 | SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst), \ |
|---|
| 808 | SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst), \ |
|---|
| 809 | SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst), \ |
|---|
| 810 | SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst), \ |
|---|
| 811 | SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst), \ |
|---|
| 812 | SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst), \ |
|---|
| 813 | SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst), \ |
|---|
| 814 | SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst), \ |
|---|
| 815 | SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst), \ |
|---|
| 816 | SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst), \ |
|---|
| 817 | SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst), \ |
|---|
| 818 | SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst), \ |
|---|
| 819 | SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst), \ |
|---|
| 820 | SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst), \ |
|---|
| 821 | SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst), \ |
|---|
| 822 | SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst), \ |
|---|
| 823 | SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst), \ |
|---|
| 824 | SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst), \ |
|---|
| 825 | SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst), \ |
|---|
| 826 | SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst), \ |
|---|
| 827 | SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst), \ |
|---|
| 828 | SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst), \ |
|---|
| 829 | SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst), \ |
|---|
| 830 | SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst), \ |
|---|
| 831 | SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst), \ |
|---|
| 832 | SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst), \ |
|---|
| 833 | SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst), \ |
|---|
| 834 | SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst), \ |
|---|
| 835 | SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst), \ |
|---|
| 836 | SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst), \ |
|---|
| 837 | SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst), \ |
|---|
| 838 | SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst), \ |
|---|
| 839 | SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst), \ |
|---|
| 840 | SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst), \ |
|---|
| 841 | SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst) |
|---|
| 842 | |
|---|
| 843 | #define MPC_REG_LIST_DCN3_2_RI(inst) \ |
|---|
| 844 | MPC_REG_LIST_DCN3_0_RI(inst),\ |
|---|
| 845 | SRII(MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC, inst),\ |
|---|
| 846 | SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\ |
|---|
| 847 | SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\ |
|---|
| 848 | SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\ |
|---|
| 849 | SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\ |
|---|
| 850 | SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\ |
|---|
| 851 | SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\ |
|---|
| 852 | SRII(MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM, inst),\ |
|---|
| 853 | SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\ |
|---|
| 854 | SRII(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM, inst),\ |
|---|
| 855 | SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 856 | SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 857 | SRII(MPCC_MCM_SHAPER_RAMA_START_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 858 | SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 859 | SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 860 | SRII(MPCC_MCM_SHAPER_RAMA_END_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 861 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM, inst),\ |
|---|
| 862 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_2_3, MPCC_MCM, inst),\ |
|---|
| 863 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_4_5, MPCC_MCM, inst),\ |
|---|
| 864 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_6_7, MPCC_MCM, inst),\ |
|---|
| 865 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_8_9, MPCC_MCM, inst),\ |
|---|
| 866 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_10_11, MPCC_MCM, inst),\ |
|---|
| 867 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_12_13, MPCC_MCM, inst),\ |
|---|
| 868 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_14_15, MPCC_MCM, inst),\ |
|---|
| 869 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_16_17, MPCC_MCM, inst),\ |
|---|
| 870 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_18_19, MPCC_MCM, inst),\ |
|---|
| 871 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_20_21, MPCC_MCM, inst),\ |
|---|
| 872 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_22_23, MPCC_MCM, inst),\ |
|---|
| 873 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_24_25, MPCC_MCM, inst),\ |
|---|
| 874 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_26_27, MPCC_MCM, inst),\ |
|---|
| 875 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_28_29, MPCC_MCM, inst),\ |
|---|
| 876 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_30_31, MPCC_MCM, inst),\ |
|---|
| 877 | SRII(MPCC_MCM_SHAPER_RAMA_REGION_32_33, MPCC_MCM, inst),\ |
|---|
| 878 | SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 879 | SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 880 | SRII(MPCC_MCM_SHAPER_RAMB_START_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 881 | SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 882 | SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 883 | SRII(MPCC_MCM_SHAPER_RAMB_END_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 884 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_0_1, MPCC_MCM, inst),\ |
|---|
| 885 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_2_3, MPCC_MCM, inst),\ |
|---|
| 886 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_4_5, MPCC_MCM, inst),\ |
|---|
| 887 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_6_7, MPCC_MCM, inst),\ |
|---|
| 888 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_8_9, MPCC_MCM, inst),\ |
|---|
| 889 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_10_11, MPCC_MCM, inst),\ |
|---|
| 890 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_12_13, MPCC_MCM, inst),\ |
|---|
| 891 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_14_15, MPCC_MCM, inst),\ |
|---|
| 892 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_16_17, MPCC_MCM, inst),\ |
|---|
| 893 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_18_19, MPCC_MCM, inst),\ |
|---|
| 894 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_20_21, MPCC_MCM, inst),\ |
|---|
| 895 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_22_23, MPCC_MCM, inst),\ |
|---|
| 896 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_24_25, MPCC_MCM, inst),\ |
|---|
| 897 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_26_27, MPCC_MCM, inst),\ |
|---|
| 898 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_28_29, MPCC_MCM, inst),\ |
|---|
| 899 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_30_31, MPCC_MCM, inst),\ |
|---|
| 900 | SRII(MPCC_MCM_SHAPER_RAMB_REGION_32_33, MPCC_MCM, inst),\ |
|---|
| 901 | SRII(MPCC_MCM_3DLUT_MODE, MPCC_MCM, inst), /*TODO: may need to add other 3DLUT regs*/\ |
|---|
| 902 | SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\ |
|---|
| 903 | SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\ |
|---|
| 904 | SRII(MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM, inst),\ |
|---|
| 905 | SRII(MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM, inst),\ |
|---|
| 906 | SRII(MPCC_MCM_3DLUT_OUT_NORM_FACTOR, MPCC_MCM, inst),\ |
|---|
| 907 | SRII(MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM, inst),\ |
|---|
| 908 | SRII(MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM, inst),\ |
|---|
| 909 | SRII(MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM, inst),\ |
|---|
| 910 | SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\ |
|---|
| 911 | SRII(MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM, inst),\ |
|---|
| 912 | SRII(MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM, inst),\ |
|---|
| 913 | SRII(MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM, inst),\ |
|---|
| 914 | SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 915 | SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 916 | SRII(MPCC_MCM_1DLUT_RAMA_START_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 917 | SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 918 | SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 919 | SRII(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 920 | SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 921 | SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 922 | SRII(MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 923 | SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM, inst),\ |
|---|
| 924 | SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM, inst),\ |
|---|
| 925 | SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G, MPCC_MCM, inst),\ |
|---|
| 926 | SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G, MPCC_MCM, inst),\ |
|---|
| 927 | SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R, MPCC_MCM, inst),\ |
|---|
| 928 | SRII(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R, MPCC_MCM, inst),\ |
|---|
| 929 | SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM, inst),\ |
|---|
| 930 | SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_G, MPCC_MCM, inst),\ |
|---|
| 931 | SRII(MPCC_MCM_1DLUT_RAMA_OFFSET_R, MPCC_MCM, inst),\ |
|---|
| 932 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM, inst),\ |
|---|
| 933 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_2_3, MPCC_MCM, inst),\ |
|---|
| 934 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_4_5, MPCC_MCM, inst),\ |
|---|
| 935 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_6_7, MPCC_MCM, inst),\ |
|---|
| 936 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_8_9, MPCC_MCM, inst),\ |
|---|
| 937 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_10_11, MPCC_MCM, inst),\ |
|---|
| 938 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_12_13, MPCC_MCM, inst),\ |
|---|
| 939 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_14_15, MPCC_MCM, inst),\ |
|---|
| 940 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_16_17, MPCC_MCM, inst),\ |
|---|
| 941 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_18_19, MPCC_MCM, inst),\ |
|---|
| 942 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_20_21, MPCC_MCM, inst),\ |
|---|
| 943 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_22_23, MPCC_MCM, inst),\ |
|---|
| 944 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_24_25, MPCC_MCM, inst),\ |
|---|
| 945 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_26_27, MPCC_MCM, inst),\ |
|---|
| 946 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_28_29, MPCC_MCM, inst),\ |
|---|
| 947 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_30_31, MPCC_MCM, inst),\ |
|---|
| 948 | SRII(MPCC_MCM_1DLUT_RAMA_REGION_32_33, MPCC_MCM, inst),\ |
|---|
| 949 | SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 950 | SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 951 | SRII(MPCC_MCM_1DLUT_RAMB_START_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 952 | SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 953 | SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 954 | SRII(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 955 | SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B, MPCC_MCM, inst),\ |
|---|
| 956 | SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G, MPCC_MCM, inst),\ |
|---|
| 957 | SRII(MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R, MPCC_MCM, inst),\ |
|---|
| 958 | SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B, MPCC_MCM, inst),\ |
|---|
| 959 | SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B, MPCC_MCM, inst),\ |
|---|
| 960 | SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G, MPCC_MCM, inst),\ |
|---|
| 961 | SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G, MPCC_MCM, inst),\ |
|---|
| 962 | SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R, MPCC_MCM, inst),\ |
|---|
| 963 | SRII(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R, MPCC_MCM, inst),\ |
|---|
| 964 | SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_B, MPCC_MCM, inst),\ |
|---|
| 965 | SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_G, MPCC_MCM, inst),\ |
|---|
| 966 | SRII(MPCC_MCM_1DLUT_RAMB_OFFSET_R, MPCC_MCM, inst),\ |
|---|
| 967 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_0_1, MPCC_MCM, inst),\ |
|---|
| 968 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_2_3, MPCC_MCM, inst),\ |
|---|
| 969 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_4_5, MPCC_MCM, inst),\ |
|---|
| 970 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_6_7, MPCC_MCM, inst),\ |
|---|
| 971 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_8_9, MPCC_MCM, inst),\ |
|---|
| 972 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_10_11, MPCC_MCM, inst),\ |
|---|
| 973 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_12_13, MPCC_MCM, inst),\ |
|---|
| 974 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_14_15, MPCC_MCM, inst),\ |
|---|
| 975 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_16_17, MPCC_MCM, inst),\ |
|---|
| 976 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_18_19, MPCC_MCM, inst),\ |
|---|
| 977 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_20_21, MPCC_MCM, inst),\ |
|---|
| 978 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_22_23, MPCC_MCM, inst),\ |
|---|
| 979 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_24_25, MPCC_MCM, inst),\ |
|---|
| 980 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_26_27, MPCC_MCM, inst),\ |
|---|
| 981 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_28_29, MPCC_MCM, inst),\ |
|---|
| 982 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_30_31, MPCC_MCM, inst),\ |
|---|
| 983 | SRII(MPCC_MCM_1DLUT_RAMB_REGION_32_33, MPCC_MCM, inst),\ |
|---|
| 984 | SRII(MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM, inst) |
|---|
| 985 | /* OPTC */ |
|---|
| 986 | |
|---|
| 987 | #define OPTC_COMMON_REG_LIST_DCN3_2_RI(inst) \ |
|---|
| 988 | SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \ |
|---|
| 989 | SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \ |
|---|
| 990 | SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \ |
|---|
| 991 | SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \ |
|---|
| 992 | SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \ |
|---|
| 993 | SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ |
|---|
| 994 | SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ |
|---|
| 995 | SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \ |
|---|
| 996 | SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \ |
|---|
| 997 | SRI_ARR(OTG_H_TOTAL, OTG, inst), \ |
|---|
| 998 | SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \ |
|---|
| 999 | SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \ |
|---|
| 1000 | SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \ |
|---|
| 1001 | SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \ |
|---|
| 1002 | SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \ |
|---|
| 1003 | SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \ |
|---|
| 1004 | SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \ |
|---|
| 1005 | SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \ |
|---|
| 1006 | SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \ |
|---|
| 1007 | SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \ |
|---|
| 1008 | SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \ |
|---|
| 1009 | SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \ |
|---|
| 1010 | SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \ |
|---|
| 1011 | SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \ |
|---|
| 1012 | SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \ |
|---|
| 1013 | SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \ |
|---|
| 1014 | SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \ |
|---|
| 1015 | SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \ |
|---|
| 1016 | SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \ |
|---|
| 1017 | SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \ |
|---|
| 1018 | SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \ |
|---|
| 1019 | SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \ |
|---|
| 1020 | SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \ |
|---|
| 1021 | SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \ |
|---|
| 1022 | SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \ |
|---|
| 1023 | SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \ |
|---|
| 1024 | SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \ |
|---|
| 1025 | SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \ |
|---|
| 1026 | SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \ |
|---|
| 1027 | SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \ |
|---|
| 1028 | SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst), \ |
|---|
| 1029 | SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst), \ |
|---|
| 1030 | SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \ |
|---|
| 1031 | SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \ |
|---|
| 1032 | SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \ |
|---|
| 1033 | SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \ |
|---|
| 1034 | SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \ |
|---|
| 1035 | SR_ARR(GSL_SOURCE_SELECT, inst), \ |
|---|
| 1036 | SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \ |
|---|
| 1037 | SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ |
|---|
| 1038 | SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ |
|---|
| 1039 | SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \ |
|---|
| 1040 | SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \ |
|---|
| 1041 | SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \ |
|---|
| 1042 | SRI_ARR(OTG_DSC_START_POSITION, OTG, inst), \ |
|---|
| 1043 | SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \ |
|---|
| 1044 | SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \ |
|---|
| 1045 | SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \ |
|---|
| 1046 | SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ |
|---|
| 1047 | SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ |
|---|
| 1048 | SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ |
|---|
| 1049 | SRI_ARR(OTG_DRR_CONTROL, OTG, inst) |
|---|
| 1050 | |
|---|
| 1051 | /* HUBP */ |
|---|
| 1052 | |
|---|
| 1053 | #define HUBP_REG_LIST_DCN_VM_RI(id) \ |
|---|
| 1054 | SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \ |
|---|
| 1055 | SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \ |
|---|
| 1056 | SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \ |
|---|
| 1057 | SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \ |
|---|
| 1058 | SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) |
|---|
| 1059 | #define HUBP_REG_LIST_DCN_RI(id) \ |
|---|
| 1060 | SRI_ARR(DCHUBP_CNTL, HUBP, id), SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \ |
|---|
| 1061 | SRI_ARR(HUBPREQ_DEBUG, HUBP, id), SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \ |
|---|
| 1062 | SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \ |
|---|
| 1063 | SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \ |
|---|
| 1064 | SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \ |
|---|
| 1065 | SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \ |
|---|
| 1066 | SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \ |
|---|
| 1067 | SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ |
|---|
| 1068 | SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ |
|---|
| 1069 | SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ |
|---|
| 1070 | SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ |
|---|
| 1071 | SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ |
|---|
| 1072 | SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ |
|---|
| 1073 | SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \ |
|---|
| 1074 | SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \ |
|---|
| 1075 | SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \ |
|---|
| 1076 | SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \ |
|---|
| 1077 | SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \ |
|---|
| 1078 | SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \ |
|---|
| 1079 | SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \ |
|---|
| 1080 | SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id), \ |
|---|
| 1081 | SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \ |
|---|
| 1082 | SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id), \ |
|---|
| 1083 | SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \ |
|---|
| 1084 | SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \ |
|---|
| 1085 | SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \ |
|---|
| 1086 | SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \ |
|---|
| 1087 | SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \ |
|---|
| 1088 | SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \ |
|---|
| 1089 | SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \ |
|---|
| 1090 | SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \ |
|---|
| 1091 | SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \ |
|---|
| 1092 | SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \ |
|---|
| 1093 | SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \ |
|---|
| 1094 | SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \ |
|---|
| 1095 | SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \ |
|---|
| 1096 | SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \ |
|---|
| 1097 | SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \ |
|---|
| 1098 | SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \ |
|---|
| 1099 | SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \ |
|---|
| 1100 | SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \ |
|---|
| 1101 | SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \ |
|---|
| 1102 | SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \ |
|---|
| 1103 | SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \ |
|---|
| 1104 | SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \ |
|---|
| 1105 | SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \ |
|---|
| 1106 | SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \ |
|---|
| 1107 | SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \ |
|---|
| 1108 | SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \ |
|---|
| 1109 | SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \ |
|---|
| 1110 | SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \ |
|---|
| 1111 | SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \ |
|---|
| 1112 | SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \ |
|---|
| 1113 | SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \ |
|---|
| 1114 | SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \ |
|---|
| 1115 | SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \ |
|---|
| 1116 | SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \ |
|---|
| 1117 | SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \ |
|---|
| 1118 | SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \ |
|---|
| 1119 | SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \ |
|---|
| 1120 | SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \ |
|---|
| 1121 | SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \ |
|---|
| 1122 | SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id), \ |
|---|
| 1123 | SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \ |
|---|
| 1124 | SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \ |
|---|
| 1125 | SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \ |
|---|
| 1126 | SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \ |
|---|
| 1127 | SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \ |
|---|
| 1128 | SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \ |
|---|
| 1129 | SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \ |
|---|
| 1130 | SRI_ARR(HUBP_CLK_CNTL, HUBP, id) |
|---|
| 1131 | #define HUBP_REG_LIST_DCN2_COMMON_RI(id) \ |
|---|
| 1132 | HUBP_REG_LIST_DCN_RI(id), HUBP_REG_LIST_DCN_VM_RI(id), \ |
|---|
| 1133 | SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \ |
|---|
| 1134 | SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \ |
|---|
| 1135 | SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \ |
|---|
| 1136 | SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \ |
|---|
| 1137 | SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \ |
|---|
| 1138 | SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ |
|---|
| 1139 | SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ |
|---|
| 1140 | SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \ |
|---|
| 1141 | SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ |
|---|
| 1142 | SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \ |
|---|
| 1143 | SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \ |
|---|
| 1144 | SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \ |
|---|
| 1145 | SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \ |
|---|
| 1146 | SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \ |
|---|
| 1147 | SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \ |
|---|
| 1148 | SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \ |
|---|
| 1149 | SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \ |
|---|
| 1150 | SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \ |
|---|
| 1151 | SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \ |
|---|
| 1152 | SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \ |
|---|
| 1153 | SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \ |
|---|
| 1154 | SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \ |
|---|
| 1155 | SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \ |
|---|
| 1156 | SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \ |
|---|
| 1157 | SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ |
|---|
| 1158 | SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id) |
|---|
| 1159 | #define HUBP_REG_LIST_DCN21_RI(id) \ |
|---|
| 1160 | HUBP_REG_LIST_DCN2_COMMON_RI(id), SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \ |
|---|
| 1161 | SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \ |
|---|
| 1162 | SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \ |
|---|
| 1163 | SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \ |
|---|
| 1164 | SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \ |
|---|
| 1165 | SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id) |
|---|
| 1166 | #define HUBP_REG_LIST_DCN30_RI(id) \ |
|---|
| 1167 | HUBP_REG_LIST_DCN21_RI(id), SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id) |
|---|
| 1168 | #define HUBP_REG_LIST_DCN32_RI(id) \ |
|---|
| 1169 | HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \ |
|---|
| 1170 | SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ |
|---|
| 1171 | SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id) |
|---|
| 1172 | |
|---|
| 1173 | /* HUBBUB */ |
|---|
| 1174 | |
|---|
| 1175 | #define HUBBUB_REG_LIST_DCN32_RI(id) \ |
|---|
| 1176 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A), \ |
|---|
| 1177 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B), \ |
|---|
| 1178 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C), \ |
|---|
| 1179 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D), \ |
|---|
| 1180 | SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL), \ |
|---|
| 1181 | SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL), \ |
|---|
| 1182 | SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ |
|---|
| 1183 | SR(DCHUBBUB_SOFT_RESET), SR(DCHUBBUB_CRC_CTRL), \ |
|---|
| 1184 | SR(DCN_VM_FB_LOCATION_BASE), SR(DCN_VM_FB_LOCATION_TOP), \ |
|---|
| 1185 | SR(DCN_VM_FB_OFFSET), SR(DCN_VM_AGP_BOT), SR(DCN_VM_AGP_TOP), \ |
|---|
| 1186 | SR(DCN_VM_AGP_BASE), HUBBUB_SR_WATERMARK_REG_LIST(), \ |
|---|
| 1187 | SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B), \ |
|---|
| 1188 | SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D), \ |
|---|
| 1189 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A), \ |
|---|
| 1190 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B), \ |
|---|
| 1191 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C), \ |
|---|
| 1192 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D), \ |
|---|
| 1193 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A), \ |
|---|
| 1194 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B), \ |
|---|
| 1195 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C), \ |
|---|
| 1196 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D), SR(DCHUBBUB_DET0_CTRL), \ |
|---|
| 1197 | SR(DCHUBBUB_DET1_CTRL), SR(DCHUBBUB_DET2_CTRL), SR(DCHUBBUB_DET3_CTRL), \ |
|---|
| 1198 | SR(DCHUBBUB_COMPBUF_CTRL), SR(COMPBUF_RESERVED_SPACE), \ |
|---|
| 1199 | SR(DCHUBBUB_DEBUG_CTRL_0), \ |
|---|
| 1200 | SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL), \ |
|---|
| 1201 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A), \ |
|---|
| 1202 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B), \ |
|---|
| 1203 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C), \ |
|---|
| 1204 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D), \ |
|---|
| 1205 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A), \ |
|---|
| 1206 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B), \ |
|---|
| 1207 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C), \ |
|---|
| 1208 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D), \ |
|---|
| 1209 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A), \ |
|---|
| 1210 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B), \ |
|---|
| 1211 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C), \ |
|---|
| 1212 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D), \ |
|---|
| 1213 | SR(DCHUBBUB_ARB_MALL_CNTL), \ |
|---|
| 1214 | SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB), \ |
|---|
| 1215 | SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS), \ |
|---|
| 1216 | SR(SDPIF_REQUEST_RATE_LIMIT) |
|---|
| 1217 | |
|---|
| 1218 | /* DCCG */ |
|---|
| 1219 | |
|---|
| 1220 | #define DCCG_REG_LIST_DCN32_RI() \ |
|---|
| 1221 | SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0), \ |
|---|
| 1222 | DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2), \ |
|---|
| 1223 | DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \ |
|---|
| 1224 | SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \ |
|---|
| 1225 | SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \ |
|---|
| 1226 | SR(PHYESYMCLK_CLOCK_CNTL), SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \ |
|---|
| 1227 | SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL), \ |
|---|
| 1228 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \ |
|---|
| 1229 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \ |
|---|
| 1230 | DCCG_SRII(MODULO, DTBCLK_DTO, 0), DCCG_SRII(MODULO, DTBCLK_DTO, 1), \ |
|---|
| 1231 | DCCG_SRII(MODULO, DTBCLK_DTO, 2), DCCG_SRII(MODULO, DTBCLK_DTO, 3), \ |
|---|
| 1232 | DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \ |
|---|
| 1233 | DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \ |
|---|
| 1234 | SR(DCCG_AUDIO_DTBCLK_DTO_MODULO), SR(DCCG_AUDIO_DTBCLK_DTO_PHASE), \ |
|---|
| 1235 | SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), \ |
|---|
| 1236 | SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL) |
|---|
| 1237 | |
|---|
| 1238 | /* VMID */ |
|---|
| 1239 | #define DCN20_VMID_REG_LIST_RI(id) \ |
|---|
| 1240 | SRI_ARR(CNTL, DCN_VM_CONTEXT, id), \ |
|---|
| 1241 | SRI_ARR(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id), \ |
|---|
| 1242 | SRI_ARR(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id), \ |
|---|
| 1243 | SRI_ARR(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id), \ |
|---|
| 1244 | SRI_ARR(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id), \ |
|---|
| 1245 | SRI_ARR(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id), \ |
|---|
| 1246 | SRI_ARR(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id) |
|---|
| 1247 | |
|---|
| 1248 | /* I2C HW */ |
|---|
| 1249 | |
|---|
| 1250 | #define I2C_HW_ENGINE_COMMON_REG_LIST_RI(id) \ |
|---|
| 1251 | SRI_ARR_I2C(SETUP, DC_I2C_DDC, id), SRI_ARR_I2C(SPEED, DC_I2C_DDC, id), \ |
|---|
| 1252 | SRI_ARR_I2C(HW_STATUS, DC_I2C_DDC, id), \ |
|---|
| 1253 | SR_ARR_I2C(DC_I2C_ARBITRATION, id), \ |
|---|
| 1254 | SR_ARR_I2C(DC_I2C_CONTROL, id), SR_ARR_I2C(DC_I2C_SW_STATUS, id), \ |
|---|
| 1255 | SR_ARR_I2C(DC_I2C_TRANSACTION0, id), SR_ARR_I2C(DC_I2C_TRANSACTION1, id),\ |
|---|
| 1256 | SR_ARR_I2C(DC_I2C_TRANSACTION2, id), SR_ARR_I2C(DC_I2C_TRANSACTION3, id),\ |
|---|
| 1257 | SR_ARR_I2C(DC_I2C_DATA, id), SR_ARR_I2C(MICROSECOND_TIME_BASE_DIV, id) |
|---|
| 1258 | |
|---|
| 1259 | #define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) \ |
|---|
| 1260 | I2C_HW_ENGINE_COMMON_REG_LIST_RI(id), SR_ARR_I2C(DIO_MEM_PWR_CTRL, id), \ |
|---|
| 1261 | SR_ARR_I2C(DIO_MEM_PWR_STATUS, id) |
|---|
| 1262 | |
|---|
| 1263 | #endif /* _DCN32_RESOURCE_H_ */ |
|---|
| 1264 | |
|---|
