1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright 2023 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | */ |
24 | |
25 | #ifndef __DC_LINK_ENCODER__DCN35_H__ |
26 | #define __DC_LINK_ENCODER__DCN35_H__ |
27 | |
28 | #include "dcn32/dcn32_dio_link_encoder.h" |
29 | #include "dcn30/dcn30_dio_link_encoder.h" |
30 | #include "dcn31/dcn31_dio_link_encoder.h" |
31 | |
32 | #define LINK_ENCODER_MASK_SH_LIST_DCN35(mask_sh) \ |
33 | LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_BE_ENABLE, mask_sh),\ |
34 | LE_SF(DIG0_DIG_BE_CNTL, DIG_RB_SWITCH_EN, mask_sh),\ |
35 | LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ |
36 | LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ |
37 | LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\ |
38 | LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\ |
39 | LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\ |
40 | LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\ |
41 | LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\ |
42 | LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ |
43 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ |
44 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ |
45 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ |
46 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ |
47 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ |
48 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ |
49 | LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ |
50 | LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ |
51 | LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ |
52 | LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ |
53 | LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ |
54 | LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ |
55 | LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ |
56 | LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ |
57 | LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ |
58 | LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ |
59 | LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ |
60 | LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ |
61 | LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ |
62 | LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ |
63 | LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ |
64 | LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ |
65 | LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ |
66 | LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ |
67 | LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ |
68 | LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ |
69 | LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ |
70 | LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ |
71 | LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ |
72 | LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ |
73 | LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ |
74 | LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ |
75 | LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ |
76 | LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ |
77 | LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ |
78 | LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ |
79 | LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ |
80 | LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ |
81 | LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ |
82 | LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ |
83 | LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ |
84 | LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ |
85 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ |
86 | LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh),\ |
87 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ |
88 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ |
89 | LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ |
90 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ |
91 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ |
92 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ |
93 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ |
94 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ |
95 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ |
96 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ |
97 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ |
98 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ |
99 | LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ |
100 | LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ |
101 | LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ |
102 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ |
103 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ |
104 | LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\ |
105 | LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\ |
106 | LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\ |
107 | LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh),\ |
108 | LE_SF(DIO_CLK_CNTL, DISPCLK_R_GATE_DIS, mask_sh),\ |
109 | LE_SF(DIO_CLK_CNTL, DISPCLK_G_GATE_DIS, mask_sh),\ |
110 | LE_SF(DIO_CLK_CNTL, REFCLK_R_GATE_DIS, mask_sh),\ |
111 | LE_SF(DIO_CLK_CNTL, REFCLK_G_GATE_DIS, mask_sh),\ |
112 | LE_SF(DIO_CLK_CNTL, SOCCLK_G_GATE_DIS, mask_sh),\ |
113 | LE_SF(DIO_CLK_CNTL, SYMCLK_FE_R_GATE_DIS, mask_sh),\ |
114 | LE_SF(DIO_CLK_CNTL, SYMCLK_FE_G_GATE_DIS, mask_sh),\ |
115 | LE_SF(DIO_CLK_CNTL, SYMCLK_R_GATE_DIS, mask_sh),\ |
116 | LE_SF(DIO_CLK_CNTL, SYMCLK_G_GATE_DIS, mask_sh),\ |
117 | LE_SF(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, mask_sh) |
118 | |
119 | |
120 | void dcn35_link_encoder_construct( |
121 | struct dcn20_link_encoder *enc20, |
122 | const struct encoder_init_data *init_data, |
123 | const struct encoder_feature_support *enc_features, |
124 | const struct dcn10_link_enc_registers *link_regs, |
125 | const struct dcn10_link_enc_aux_registers *aux_regs, |
126 | const struct dcn10_link_enc_hpd_registers *hpd_regs, |
127 | const struct dcn10_link_enc_shift *link_shift, |
128 | const struct dcn10_link_enc_mask *link_mask); |
129 | |
130 | void dcn35_link_encoder_init(struct link_encoder *enc); |
131 | void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enabled); |
132 | bool dcn35_is_dig_enabled(struct link_encoder *enc); |
133 | |
134 | enum signal_type dcn35_get_dig_mode(struct link_encoder *enc); |
135 | void dcn35_link_encoder_setup(struct link_encoder *enc, enum signal_type signal); |
136 | |
137 | #endif /* __DC_LINK_ENCODER__DCN35_H__ */ |
138 | |