| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright 2023 Advanced Micro Devices, Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: AMD |
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| 24 | * |
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| 25 | */ |
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| 26 | |
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| 27 | #include "dcn35_opp.h" |
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| 28 | #include "reg_helper.h" |
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| 29 | |
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| 30 | #define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg |
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| 31 | |
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| 32 | #undef FN |
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| 33 | #define FN(reg_name, field_name) \ |
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| 34 | ((const struct dcn35_opp_shift *)(oppn20->opp_shift))->field_name, \ |
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| 35 | ((const struct dcn35_opp_mask *)(oppn20->opp_mask))->field_name |
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| 36 | |
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| 37 | #define CTX oppn20->base.ctx |
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| 38 | |
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| 39 | void dcn35_opp_construct(struct dcn20_opp *oppn20, struct dc_context *ctx, |
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| 40 | uint32_t inst, const struct dcn35_opp_registers *regs, |
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| 41 | const struct dcn35_opp_shift *opp_shift, |
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| 42 | const struct dcn35_opp_mask *opp_mask) |
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| 43 | { |
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| 44 | dcn20_opp_construct(oppn20, ctx, inst, |
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| 45 | regs: (const struct dcn20_opp_registers *)regs, |
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| 46 | opp_shift: (const struct dcn20_opp_shift *)opp_shift, |
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| 47 | opp_mask: (const struct dcn20_opp_mask *)opp_mask); |
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| 48 | } |
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| 49 | |
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| 50 | void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable) |
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| 51 | { |
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| 52 | REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable); |
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| 53 | } |
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| 54 | |
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