1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright 2021 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: AMD |
24 | * |
25 | */ |
26 | #include "core_types.h" |
27 | |
28 | #ifndef __DCN20_FPU_H__ |
29 | #define __DCN20_FPU_H__ |
30 | |
31 | void dcn20_populate_dml_writeback_from_context(struct dc *dc, |
32 | struct resource_context *res_ctx, |
33 | display_e2e_pipe_params_st *pipes); |
34 | |
35 | void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, |
36 | struct dc_state *context, |
37 | display_e2e_pipe_params_st *pipes, |
38 | int pipe_cnt, int i); |
39 | void dcn20_calculate_dlg_params(struct dc *dc, |
40 | struct dc_state *context, |
41 | display_e2e_pipe_params_st *pipes, |
42 | int pipe_cnt, |
43 | int vlevel); |
44 | int dcn20_populate_dml_pipes_from_context(struct dc *dc, |
45 | struct dc_state *context, |
46 | display_e2e_pipe_params_st *pipes, |
47 | bool fast_validate); |
48 | void dcn20_calculate_wm(struct dc *dc, |
49 | struct dc_state *context, |
50 | display_e2e_pipe_params_st *pipes, |
51 | int *out_pipe_cnt, |
52 | int *pipe_split_from, |
53 | int vlevel, |
54 | bool fast_validate); |
55 | void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb, |
56 | struct pp_smu_nv_clock_table max_clocks); |
57 | void dcn20_update_bounding_box(struct dc *dc, |
58 | struct _vcs_dpi_soc_bounding_box_st *bb, |
59 | struct pp_smu_nv_clock_table *max_clocks, |
60 | unsigned int *uclk_states, |
61 | unsigned int num_states); |
62 | void dcn20_patch_bounding_box(struct dc *dc, |
63 | struct _vcs_dpi_soc_bounding_box_st *bb); |
64 | bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, |
65 | bool fast_validate, display_e2e_pipe_params_st *pipes); |
66 | void dcn20_fpu_set_wm_ranges(int i, |
67 | struct pp_smu_wm_range_sets *ranges, |
68 | struct _vcs_dpi_soc_bounding_box_st *loaded_bb); |
69 | void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, |
70 | int vlevel, |
71 | int max_mpc_comb, |
72 | int pipe_idx, |
73 | bool is_validating_bw); |
74 | |
75 | int dcn21_populate_dml_pipes_from_context(struct dc *dc, |
76 | struct dc_state *context, |
77 | display_e2e_pipe_params_st *pipes, |
78 | bool fast_validate); |
79 | bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool |
80 | fast_validate, display_e2e_pipe_params_st *pipes); |
81 | void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); |
82 | |
83 | void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params); |
84 | |
85 | void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, |
86 | struct resource_context *res_ctx, |
87 | display_e2e_pipe_params_st *pipes); |
88 | |
89 | #endif /* __DCN20_FPU_H__ */ |
90 | |