1	/* SPDX-License-Identifier: MIT */
2	/*
3	* Copyright 2023 Advanced Micro Devices, Inc.
4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:
11	*
12	* The above copyright notice and this permission notice shall be included in
13	* all copies or substantial portions of the Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21	* OTHER DEALINGS IN THE SOFTWARE.
22	*
23	* Authors: AMD
24	*
25	*/
26
27	#ifndef __DISPLAY_MODE_CORE_STRUCT_H__
28	#define __DISPLAY_MODE_CORE_STRUCT_H__
29
30	#include "display_mode_lib_defines.h"
31
32	enum dml_project_id {
33	dml_project_invalid = 0,
34	dml_project_default = 1,
35	dml_project_dcn32 = dml_project_default,
36	dml_project_dcn321 = 2,
37	dml_project_dcn35 = 3,
38	dml_project_dcn351 = 4,
39	};
40	enum dml_prefetch_modes {
41	dml_prefetch_support_uclk_fclk_and_stutter_if_possible = 0,
42	dml_prefetch_support_uclk_fclk_and_stutter = 1,
43	dml_prefetch_support_fclk_and_stutter = 2,
44	dml_prefetch_support_stutter = 3,
45	dml_prefetch_support_none = 4
46	};
47	enum dml_use_mall_for_pstate_change_mode {
48	dml_use_mall_pstate_change_disable = 0,
49	dml_use_mall_pstate_change_full_frame = 1,
50	dml_use_mall_pstate_change_sub_viewport = 2,
51	dml_use_mall_pstate_change_phantom_pipe = 3
52	};
53	enum dml_use_mall_for_static_screen_mode {
54	dml_use_mall_static_screen_disable = 0,
55	dml_use_mall_static_screen_enable = 1,
56	dml_use_mall_static_screen_optimize = 2
57	};
58	enum dml_output_encoder_class {
59	dml_dp = 0,
60	dml_edp = 1,
61	dml_dp2p0 = 2,
62	dml_hdmi = 3,
63	dml_hdmifrl = 4,
64	dml_none = 5
65	};
66	enum dml_output_link_dp_rate{
67	dml_dp_rate_na = 0,
68	dml_dp_rate_hbr = 1,
69	dml_dp_rate_hbr2 = 2,
70	dml_dp_rate_hbr3 = 3,
71	dml_dp_rate_uhbr10 = 4,
72	dml_dp_rate_uhbr13p5 = 5,
73	dml_dp_rate_uhbr20 = 6
74	};
75	enum dml_output_type_and_rate__type{
76	dml_output_type_unknown = 0,
77	dml_output_type_dp = 1,
78	dml_output_type_edp = 2,
79	dml_output_type_dp2p0 = 3,
80	dml_output_type_hdmi = 4,
81	dml_output_type_hdmifrl = 5
82	};
83	enum dml_output_type_and_rate__rate {
84	dml_output_rate_unknown = 0,
85	dml_output_rate_dp_rate_hbr = 1,
86	dml_output_rate_dp_rate_hbr2 = 2,
87	dml_output_rate_dp_rate_hbr3 = 3,
88	dml_output_rate_dp_rate_uhbr10 = 4,
89	dml_output_rate_dp_rate_uhbr13p5 = 5,
90	dml_output_rate_dp_rate_uhbr20 = 6,
91	dml_output_rate_hdmi_rate_3x3 = 7,
92	dml_output_rate_hdmi_rate_6x3 = 8,
93	dml_output_rate_hdmi_rate_6x4 = 9,
94	dml_output_rate_hdmi_rate_8x4 = 10,
95	dml_output_rate_hdmi_rate_10x4 = 11,
96	dml_output_rate_hdmi_rate_12x4 = 12
97	};
98	enum dml_output_format_class {
99	dml_444 = 0,
100	dml_s422 = 1,
101	dml_n422 = 2,
102	dml_420 = 3
103	};
104	enum dml_source_format_class {
105	dml_444_8 = 0,
106	dml_444_16 = 1,
107	dml_444_32 = 2,
108	dml_444_64 = 3,
109	dml_420_8 = 4,
110	dml_420_10 = 5,
111	dml_420_12 = 6,
112	dml_422_8 = 7,
113	dml_422_10 = 8,
114	dml_rgbe_alpha = 9,
115	dml_rgbe = 10,
116	dml_mono_8 = 11,
117	dml_mono_16 = 12
118	};
119	enum dml_output_bpc_class {
120	dml_out_6 = 0,
121	dml_out_8 = 1,
122	dml_out_10 = 2,
123	dml_out_12 = 3,
124	dml_out_16 = 4
125	};
126	enum dml_output_standard_class {
127	dml_std_cvt = 0,
128	dml_std_cea = 1,
129	dml_std_cvtr2 = 2
130	};
131	enum dml_rotation_angle {
132	dml_rotation_0 = 0,
133	dml_rotation_90 = 1,
134	dml_rotation_180 = 2,
135	dml_rotation_270 = 3,
136	dml_rotation_0m = 4,
137	dml_rotation_90m = 5,
138	dml_rotation_180m = 6,
139	dml_rotation_270m = 7
140	};
141	enum dml_swizzle_mode {
142	dml_sw_linear = 0,
143	dml_sw_256b_s = 1,
144	dml_sw_256b_d = 2,
145	dml_sw_256b_r = 3,
146	dml_sw_4kb_z = 4,
147	dml_sw_4kb_s = 5,
148	dml_sw_4kb_d = 6,
149	dml_sw_4kb_r = 7,
150	dml_sw_64kb_z = 8,
151	dml_sw_64kb_s = 9,
152	dml_sw_64kb_d = 10,
153	dml_sw_64kb_r = 11,
154	dml_sw_256kb_z = 12,
155	dml_sw_256kb_s = 13,
156	dml_sw_256kb_d = 14,
157	dml_sw_256kb_r = 15,
158	dml_sw_64kb_z_t = 16,
159	dml_sw_64kb_s_t = 17,
160	dml_sw_64kb_d_t = 18,
161	dml_sw_64kb_r_t = 19,
162	dml_sw_4kb_z_x = 20,
163	dml_sw_4kb_s_x = 21,
164	dml_sw_4kb_d_x = 22,
165	dml_sw_4kb_r_x = 23,
166	dml_sw_64kb_z_x = 24,
167	dml_sw_64kb_s_x = 25,
168	dml_sw_64kb_d_x = 26,
169	dml_sw_64kb_r_x = 27,
170	dml_sw_256kb_z_x = 28,
171	dml_sw_256kb_s_x = 29,
172	dml_sw_256kb_d_x = 30,
173	dml_sw_256kb_r_x = 31
174	};
175	enum dml_lb_depth {
176	dml_lb_6 = 0,
177	dml_lb_8 = 1,
178	dml_lb_10 = 2,
179	dml_lb_12 = 3,
180	dml_lb_16 = 4
181	};
182	enum dml_voltage_state {
183	dml_vmin_lv = 0,
184	dml_vmin = 1,
185	dml_vmid = 2,
186	dml_vnom = 3,
187	dml_vmax = 4
188	};
189	enum dml_source_macro_tile_size {
190	dml_4k_tile = 0,
191	dml_64k_tile = 1,
192	dml_256k_tile = 2
193	};
194	enum dml_cursor_bpp {
195	dml_cur_2bit = 0,
196	dml_cur_32bit = 1,
197	dml_cur_64bit = 2
198	};
199	enum dml_dram_clock_change_support {
200	dml_dram_clock_change_vactive = 0,
201	dml_dram_clock_change_vblank = 1,
202	dml_dram_clock_change_vblank_drr = 2,
203	dml_dram_clock_change_vactive_w_mall_full_frame = 3,
204	dml_dram_clock_change_vactive_w_mall_sub_vp = 4,
205	dml_dram_clock_change_vblank_w_mall_full_frame = 5,
206	dml_dram_clock_change_vblank_drr_w_mall_full_frame = 6,
207	dml_dram_clock_change_vblank_w_mall_sub_vp = 7,
208	dml_dram_clock_change_vblank_drr_w_mall_sub_vp = 8,
209	dml_dram_clock_change_unsupported = 9
210	};
211	enum dml_fclock_change_support {
212	dml_fclock_change_vactive = 0,
213	dml_fclock_change_vblank = 1,
214	dml_fclock_change_unsupported = 2
215	};
216	enum dml_dsc_enable {
217	dml_dsc_disable = 0,
218	dml_dsc_enable = 1,
219	dml_dsc_enable_if_necessary = 2
220	};
221	enum dml_mpc_use_policy {
222	dml_mpc_disabled = 0,
223	dml_mpc_as_possible = 1,
224	dml_mpc_as_needed_for_voltage = 2,
225	dml_mpc_as_needed_for_pstate_and_voltage = 3
226	};
227	enum dml_odm_use_policy {
228	dml_odm_use_policy_bypass = 0,
229	dml_odm_use_policy_combine_as_needed = 1,
230	dml_odm_use_policy_combine_2to1 = 2,
231	dml_odm_use_policy_combine_4to1 = 3,
232	dml_odm_use_policy_split_1to2 = 4,
233	dml_odm_use_policy_mso_1to2 = 5,
234	dml_odm_use_policy_mso_1to4 = 6
235	};
236	enum dml_odm_mode {
237	dml_odm_mode_bypass = 0,
238	dml_odm_mode_combine_2to1 = 1,
239	dml_odm_mode_combine_4to1 = 2,
240	dml_odm_mode_split_1to2 = 3,
241	dml_odm_mode_mso_1to2 = 4,
242	dml_odm_mode_mso_1to4 = 5
243	};
244	enum dml_writeback_configuration {
245	dml_whole_buffer_for_single_stream_no_interleave = 0,
246	dml_whole_buffer_for_single_stream_interleave = 1
247	};
248	enum dml_immediate_flip_requirement {
249	dml_immediate_flip_not_required = 0,
250	dml_immediate_flip_required = 1,
251	dml_immediate_flip_if_possible = 2
252	};
253	enum dml_unbounded_requesting_policy {
254	dml_unbounded_requesting_enable = 0,
255	dml_unbounded_requesting_edp_only = 1,
256	dml_unbounded_requesting_disable = 2
257	};
258	enum dml_clk_cfg_policy {
259	dml_use_required_freq = 0,
260	dml_use_override_freq = 1,
261	dml_use_state_freq = 2
262	};
263
264
265	struct soc_state_bounding_box_st {
266	dml_float_t socclk_mhz;
267	dml_float_t dscclk_mhz;
268	dml_float_t phyclk_mhz;
269	dml_float_t phyclk_d18_mhz;
270	dml_float_t phyclk_d32_mhz;
271	dml_float_t dtbclk_mhz;
272	dml_float_t fabricclk_mhz;
273	dml_float_t dcfclk_mhz;
274	dml_float_t dispclk_mhz;
275	dml_float_t dppclk_mhz;
276	dml_float_t dram_speed_mts;
277	dml_float_t urgent_latency_pixel_data_only_us;
278	dml_float_t urgent_latency_pixel_mixed_with_vm_data_us;
279	dml_float_t urgent_latency_vm_data_only_us;
280	dml_float_t writeback_latency_us;
281	dml_float_t urgent_latency_adjustment_fabric_clock_component_us;
282	dml_float_t urgent_latency_adjustment_fabric_clock_reference_mhz;
283	dml_float_t sr_exit_time_us;
284	dml_float_t sr_enter_plus_exit_time_us;
285	dml_float_t sr_exit_z8_time_us;
286	dml_float_t sr_enter_plus_exit_z8_time_us;
287	dml_float_t dram_clock_change_latency_us;
288	dml_float_t fclk_change_latency_us;
289	dml_float_t usr_retraining_latency_us;
290	dml_bool_t use_ideal_dram_bw_strobe;
291	};
292
293	struct soc_bounding_box_st {
294	dml_float_t dprefclk_mhz;
295	dml_float_t xtalclk_mhz;
296	dml_float_t pcierefclk_mhz;
297	dml_float_t refclk_mhz;
298	dml_float_t amclk_mhz;
299	dml_float_t max_outstanding_reqs;
300	dml_float_t pct_ideal_sdp_bw_after_urgent;
301	dml_float_t pct_ideal_fabric_bw_after_urgent;
302	dml_float_t pct_ideal_dram_bw_after_urgent_pixel_only;
303	dml_float_t pct_ideal_dram_bw_after_urgent_pixel_and_vm;
304	dml_float_t pct_ideal_dram_bw_after_urgent_vm_only;
305	dml_float_t pct_ideal_dram_bw_after_urgent_strobe;
306	dml_float_t max_avg_sdp_bw_use_normal_percent;
307	dml_float_t max_avg_fabric_bw_use_normal_percent;
308	dml_float_t max_avg_dram_bw_use_normal_percent;
309	dml_float_t max_avg_dram_bw_use_normal_strobe_percent;
310	dml_uint_t round_trip_ping_latency_dcfclk_cycles;
311	dml_uint_t urgent_out_of_order_return_per_channel_pixel_only_bytes;
312	dml_uint_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
313	dml_uint_t urgent_out_of_order_return_per_channel_vm_only_bytes;
314	dml_uint_t num_chans;
315	dml_uint_t return_bus_width_bytes;
316	dml_uint_t dram_channel_width_bytes;
317	dml_uint_t fabric_datapath_to_dcn_data_return_bytes;
318	dml_uint_t hostvm_min_page_size_kbytes;
319	dml_uint_t gpuvm_min_page_size_kbytes;
320	dml_float_t phy_downspread_percent;
321	dml_float_t dcn_downspread_percent;
322	dml_float_t smn_latency_us;
323	dml_uint_t mall_allocated_for_dcn_mbytes;
324	dml_float_t dispclk_dppclk_vco_speed_mhz;
325	dml_bool_t do_urgent_latency_adjustment;
326	};
327
328	struct ip_params_st {
329	dml_uint_t vblank_nom_default_us;
330	dml_uint_t rob_buffer_size_kbytes;
331	dml_uint_t config_return_buffer_size_in_kbytes;
332	dml_uint_t config_return_buffer_segment_size_in_kbytes;
333	dml_uint_t compressed_buffer_segment_size_in_kbytes;
334	dml_uint_t meta_fifo_size_in_kentries;
335	dml_uint_t zero_size_buffer_entries;
336	dml_uint_t dpte_buffer_size_in_pte_reqs_luma;
337	dml_uint_t dpte_buffer_size_in_pte_reqs_chroma;
338	dml_uint_t dcc_meta_buffer_size_bytes;
339	dml_bool_t gpuvm_enable;
340	dml_bool_t hostvm_enable;
341	dml_uint_t gpuvm_max_page_table_levels;
342	dml_uint_t hostvm_max_page_table_levels;
343	dml_uint_t pixel_chunk_size_kbytes;
344	dml_uint_t alpha_pixel_chunk_size_kbytes;
345	dml_uint_t min_pixel_chunk_size_bytes;
346	dml_uint_t meta_chunk_size_kbytes;
347	dml_uint_t min_meta_chunk_size_bytes;
348	dml_uint_t writeback_chunk_size_kbytes;
349	dml_uint_t line_buffer_size_bits;
350	dml_uint_t max_line_buffer_lines;
351	dml_uint_t writeback_interface_buffer_size_kbytes;
352	dml_uint_t max_num_dpp;
353	dml_uint_t max_num_otg;
354	dml_uint_t max_num_wb;
355	dml_uint_t max_dchub_pscl_bw_pix_per_clk;
356	dml_uint_t max_pscl_lb_bw_pix_per_clk;
357	dml_uint_t max_lb_vscl_bw_pix_per_clk;
358	dml_uint_t max_vscl_hscl_bw_pix_per_clk;
359	dml_float_t max_hscl_ratio;
360	dml_float_t max_vscl_ratio;
361	dml_uint_t max_hscl_taps;
362	dml_uint_t max_vscl_taps;
363	dml_uint_t num_dsc;
364	dml_uint_t maximum_dsc_bits_per_component;
365	dml_uint_t maximum_pixels_per_line_per_dsc_unit;
366	dml_bool_t dsc422_native_support;
367	dml_bool_t cursor_64bpp_support;
368	dml_float_t dispclk_ramp_margin_percent;
369	dml_uint_t dppclk_delay_subtotal;
370	dml_uint_t dppclk_delay_scl;
371	dml_uint_t dppclk_delay_scl_lb_only;
372	dml_uint_t dppclk_delay_cnvc_formatter;
373	dml_uint_t dppclk_delay_cnvc_cursor;
374	dml_uint_t cursor_buffer_size;
375	dml_uint_t cursor_chunk_size;
376	dml_uint_t dispclk_delay_subtotal;
377	dml_bool_t dynamic_metadata_vm_enabled;
378	dml_uint_t max_inter_dcn_tile_repeaters;
379	dml_uint_t max_num_hdmi_frl_outputs;
380	dml_uint_t max_num_dp2p0_outputs;
381	dml_uint_t max_num_dp2p0_streams;
382	dml_bool_t dcc_supported;
383	dml_bool_t ptoi_supported;
384	dml_float_t writeback_max_hscl_ratio;
385	dml_float_t writeback_max_vscl_ratio;
386	dml_float_t writeback_min_hscl_ratio;
387	dml_float_t writeback_min_vscl_ratio;
388	dml_uint_t writeback_max_hscl_taps;
389	dml_uint_t writeback_max_vscl_taps;
390	dml_uint_t writeback_line_buffer_buffer_size;
391	};
392
393	struct DmlPipe {
394	dml_float_t Dppclk;
395	dml_float_t Dispclk;
396	dml_float_t PixelClock;
397	dml_float_t DCFClkDeepSleep;
398	dml_uint_t DPPPerSurface;
399	dml_bool_t ScalerEnabled;
400	enum dml_rotation_angle SourceScan;
401	dml_uint_t ViewportHeight;
402	dml_uint_t ViewportHeightChroma;
403	dml_uint_t BlockWidth256BytesY;
404	dml_uint_t BlockHeight256BytesY;
405	dml_uint_t BlockWidth256BytesC;
406	dml_uint_t BlockHeight256BytesC;
407	dml_uint_t BlockWidthY;
408	dml_uint_t BlockHeightY;
409	dml_uint_t BlockWidthC;
410	dml_uint_t BlockHeightC;
411	dml_uint_t InterlaceEnable;
412	dml_uint_t NumberOfCursors;
413	dml_uint_t VBlank;
414	dml_uint_t HTotal;
415	dml_uint_t HActive;
416	dml_bool_t DCCEnable;
417	enum dml_odm_mode ODMMode;
418	enum dml_source_format_class SourcePixelFormat;
419	enum dml_swizzle_mode SurfaceTiling;
420	dml_uint_t BytePerPixelY;
421	dml_uint_t BytePerPixelC;
422	dml_bool_t ProgressiveToInterlaceUnitInOPP;
423	dml_float_t VRatio;
424	dml_float_t VRatioChroma;
425	dml_uint_t VTaps;
426	dml_uint_t VTapsChroma;
427	dml_uint_t PitchY;
428	dml_uint_t DCCMetaPitchY;
429	dml_uint_t PitchC;
430	dml_uint_t DCCMetaPitchC;
431	dml_bool_t ViewportStationary;
432	dml_uint_t ViewportXStart;
433	dml_uint_t ViewportYStart;
434	dml_uint_t ViewportXStartC;
435	dml_uint_t ViewportYStartC;
436	dml_bool_t FORCE_ONE_ROW_FOR_FRAME;
437	dml_uint_t SwathHeightY;
438	dml_uint_t SwathHeightC;
439	};
440
441	struct Watermarks {
442	dml_float_t UrgentWatermark;
443	dml_float_t WritebackUrgentWatermark;
444	dml_float_t DRAMClockChangeWatermark;
445	dml_float_t FCLKChangeWatermark;
446	dml_float_t WritebackDRAMClockChangeWatermark;
447	dml_float_t WritebackFCLKChangeWatermark;
448	dml_float_t StutterExitWatermark;
449	dml_float_t StutterEnterPlusExitWatermark;
450	dml_float_t Z8StutterExitWatermark;
451	dml_float_t Z8StutterEnterPlusExitWatermark;
452	dml_float_t USRRetrainingWatermark;
453	};
454
455	struct SOCParametersList {
456	dml_float_t UrgentLatency;
457	dml_float_t ExtraLatency;
458	dml_float_t WritebackLatency;
459	dml_float_t DRAMClockChangeLatency;
460	dml_float_t FCLKChangeLatency;
461	dml_float_t SRExitTime;
462	dml_float_t SREnterPlusExitTime;
463	dml_float_t SRExitZ8Time;
464	dml_float_t SREnterPlusExitZ8Time;
465	dml_float_t USRRetrainingLatency;
466	dml_float_t SMNLatency;
467	};
468
469	/// @brief Struct that represent Plane configration of a display cfg
470	struct dml_plane_cfg_st {
471	//
472	// Pipe/Surface Parameters
473	//
474	dml_bool_t GPUVMEnable; /// <brief Set if any pipe has GPUVM enable
475	dml_bool_t HostVMEnable; /// <brief Set if any pipe has HostVM enable
476
477	dml_uint_t GPUVMMaxPageTableLevels; /// <brief GPUVM level; max of all pipes'
478	dml_uint_t HostVMMaxPageTableLevels; /// <brief HostVM level; max of all pipes'; that is the number of non-cache HVM level
479
480	dml_uint_t GPUVMMinPageSizeKBytes[__DML_NUM_PLANES__];
481	dml_bool_t ForceOneRowForFrame[__DML_NUM_PLANES__];
482	dml_bool_t PTEBufferModeOverrideEn[__DML_NUM_PLANES__]; //< brief when override enable; the DML will only check the given pte buffer and will use the pte buffer mode as is
483	dml_bool_t PTEBufferMode[__DML_NUM_PLANES__];
484	dml_uint_t ViewportWidth[__DML_NUM_PLANES__];
485	dml_uint_t ViewportHeight[__DML_NUM_PLANES__];
486	dml_uint_t ViewportWidthChroma[__DML_NUM_PLANES__];
487	dml_uint_t ViewportHeightChroma[__DML_NUM_PLANES__];
488	dml_uint_t ViewportXStart[__DML_NUM_PLANES__];
489	dml_uint_t ViewportXStartC[__DML_NUM_PLANES__];
490	dml_uint_t ViewportYStart[__DML_NUM_PLANES__];
491	dml_uint_t ViewportYStartC[__DML_NUM_PLANES__];
492	dml_bool_t ViewportStationary[__DML_NUM_PLANES__];
493
494	dml_bool_t ScalerEnabled[__DML_NUM_PLANES__];
495	dml_float_t HRatio[__DML_NUM_PLANES__];
496	dml_float_t VRatio[__DML_NUM_PLANES__];
497	dml_float_t HRatioChroma[__DML_NUM_PLANES__];
498	dml_float_t VRatioChroma[__DML_NUM_PLANES__];
499	dml_uint_t HTaps[__DML_NUM_PLANES__];
500	dml_uint_t VTaps[__DML_NUM_PLANES__];
501	dml_uint_t HTapsChroma[__DML_NUM_PLANES__];
502	dml_uint_t VTapsChroma[__DML_NUM_PLANES__];
503	dml_uint_t LBBitPerPixel[__DML_NUM_PLANES__];
504
505	enum dml_rotation_angle SourceScan[__DML_NUM_PLANES__];
506	dml_uint_t ScalerRecoutWidth[__DML_NUM_PLANES__];
507
508	dml_bool_t DynamicMetadataEnable[__DML_NUM_PLANES__];
509	dml_uint_t DynamicMetadataLinesBeforeActiveRequired[__DML_NUM_PLANES__];
510	dml_uint_t DynamicMetadataTransmittedBytes[__DML_NUM_PLANES__];
511	dml_uint_t DETSizeOverride[__DML_NUM_PLANES__]; /// <brief user can specify the desire DET buffer usage per-plane
512
513	dml_uint_t NumberOfCursors[__DML_NUM_PLANES__];
514	dml_uint_t CursorWidth[__DML_NUM_PLANES__];
515	dml_uint_t CursorBPP[__DML_NUM_PLANES__];
516
517	enum dml_use_mall_for_static_screen_mode UseMALLForStaticScreen[__DML_NUM_PLANES__];
518	enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange[__DML_NUM_PLANES__];
519
520	dml_uint_t BlendingAndTiming[__DML_NUM_PLANES__]; /// <brief From which timing group (like OTG) that this plane is getting its timing from. Mode check also need this info for example to check num OTG; encoder; dsc etc.
521	}; // dml_plane_cfg_st;
522
523	/// @brief Surface Parameters
524	struct dml_surface_cfg_st {
525	enum dml_swizzle_mode SurfaceTiling[__DML_NUM_PLANES__];
526	enum dml_source_format_class SourcePixelFormat[__DML_NUM_PLANES__];
527	dml_uint_t PitchY[__DML_NUM_PLANES__];
528	dml_uint_t SurfaceWidthY[__DML_NUM_PLANES__];
529	dml_uint_t SurfaceHeightY[__DML_NUM_PLANES__];
530	dml_uint_t PitchC[__DML_NUM_PLANES__];
531	dml_uint_t SurfaceWidthC[__DML_NUM_PLANES__];
532	dml_uint_t SurfaceHeightC[__DML_NUM_PLANES__];
533
534	dml_bool_t DCCEnable[__DML_NUM_PLANES__];
535	dml_uint_t DCCMetaPitchY[__DML_NUM_PLANES__];
536	dml_uint_t DCCMetaPitchC[__DML_NUM_PLANES__];
537
538	dml_float_t DCCRateLuma[__DML_NUM_PLANES__];
539	dml_float_t DCCRateChroma[__DML_NUM_PLANES__];
540	dml_float_t DCCFractionOfZeroSizeRequestsLuma[__DML_NUM_PLANES__];
541	dml_float_t DCCFractionOfZeroSizeRequestsChroma[__DML_NUM_PLANES__];
542	}; // dml_surface_cfg_st
543
544	/// @brief structure that represents the timing configuration
545	struct dml_timing_cfg_st {
546	dml_uint_t HTotal[__DML_NUM_PLANES__];
547	dml_uint_t VTotal[__DML_NUM_PLANES__];
548	dml_uint_t HBlankEnd[__DML_NUM_PLANES__];
549	dml_uint_t VBlankEnd[__DML_NUM_PLANES__];
550	dml_uint_t RefreshRate[__DML_NUM_PLANES__];
551	dml_uint_t VFrontPorch[__DML_NUM_PLANES__];
552	dml_float_t PixelClock[__DML_NUM_PLANES__];
553	dml_uint_t HActive[__DML_NUM_PLANES__];
554	dml_uint_t VActive[__DML_NUM_PLANES__];
555	dml_bool_t Interlace[__DML_NUM_PLANES__];
556	dml_bool_t DRRDisplay[__DML_NUM_PLANES__];
557	dml_uint_t VBlankNom[__DML_NUM_PLANES__];
558	}; // dml_timing_cfg_st;
559
560	/// @brief structure that represents the output stream
561	struct dml_output_cfg_st {
562	// Output Setting
563	dml_uint_t DSCInputBitPerComponent[__DML_NUM_PLANES__];
564	enum dml_output_format_class OutputFormat[__DML_NUM_PLANES__];
565	enum dml_output_encoder_class OutputEncoder[__DML_NUM_PLANES__];
566	dml_uint_t OutputMultistreamId[__DML_NUM_PLANES__];
567	dml_bool_t OutputMultistreamEn[__DML_NUM_PLANES__];
568	dml_float_t OutputBpp[__DML_NUM_PLANES__]; //< brief Use by mode_programming to specify a output bpp; user can use the output from mode_support (support.OutputBpp)
569	dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__];
570	enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determine if dsc is required
571	dml_uint_t OutputLinkDPLanes[__DML_NUM_PLANES__];
572	enum dml_output_link_dp_rate OutputLinkDPRate[__DML_NUM_PLANES__];
573	dml_float_t ForcedOutputLinkBPP[__DML_NUM_PLANES__];
574	dml_uint_t AudioSampleRate[__DML_NUM_PLANES__];
575	dml_uint_t AudioSampleLayout[__DML_NUM_PLANES__];
576	dml_bool_t OutputDisabled[__DML_NUM_PLANES__];
577	}; // dml_timing_cfg_st;
578
579	/// @brief Writeback Setting
580	struct dml_writeback_cfg_st {
581	enum dml_source_format_class WritebackPixelFormat[__DML_NUM_PLANES__];
582	dml_bool_t WritebackEnable[__DML_NUM_PLANES__];
583	dml_uint_t ActiveWritebacksPerSurface[__DML_NUM_PLANES__];
584	dml_uint_t WritebackDestinationWidth[__DML_NUM_PLANES__];
585	dml_uint_t WritebackDestinationHeight[__DML_NUM_PLANES__];
586	dml_uint_t WritebackSourceWidth[__DML_NUM_PLANES__];
587	dml_uint_t WritebackSourceHeight[__DML_NUM_PLANES__];
588	dml_uint_t WritebackHTaps[__DML_NUM_PLANES__];
589	dml_uint_t WritebackVTaps[__DML_NUM_PLANES__];
590	dml_float_t WritebackHRatio[__DML_NUM_PLANES__];
591	dml_float_t WritebackVRatio[__DML_NUM_PLANES__];
592	}; // dml_writeback_cfg_st;
593
594	/// @brief Hardware resource specific; mainly used by mode_programming when test/sw wants to do some specific setting
595	/// which are not the same as what the mode support stage derive. When call mode_support with mode_programm; the hw-specific
596	// resource will be set to what the mode_support layer recommends
597	struct dml_hw_resource_st {
598	enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
599	dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.
600	dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is enabled; used in mode_programming
601	dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode
602	dml_float_t DLGRefClkFreqMHz; /// <brief DLG Global Reference timer
603	};
604
605	/// @brief DML display configuration.
606	/// Describe how to display a surface in multi-plane setup and output to different output and writeback using the specified timgin
607	struct dml_display_cfg_st {
608	struct dml_surface_cfg_st surface;
609	struct dml_plane_cfg_st plane;
610	struct dml_timing_cfg_st timing;
611	struct dml_output_cfg_st output;
612	struct dml_writeback_cfg_st writeback;
613	unsigned int num_surfaces;
614	unsigned int num_timings;
615
616	struct dml_hw_resource_st hw; //< brief for mode programming
617	}; // dml_display_cfg_st
618
619	/// @brief To control the clk usage for model programming
620	struct dml_clk_cfg_st {
621	enum dml_clk_cfg_policy dcfclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq
622	enum dml_clk_cfg_policy dispclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq
623	enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__];
624
625	dml_float_t dcfclk_freq_mhz;
626	dml_float_t dispclk_freq_mhz;
627	dml_float_t dppclk_freq_mhz[__DML_NUM_PLANES__];
628	}; // dml_clk_cfg_st
629
630	/// @brief DML mode evaluation and programming policy
631	/// Those knobs that affect mode support and mode programming
632	struct dml_mode_eval_policy_st {
633	// -------------------
634	// Policy
635	// -------------------
636	enum dml_mpc_use_policy MPCCombineUse[__DML_NUM_PLANES__]; /// <brief MPC Combine mode as selected by the user; used in mode check stage
637	enum dml_odm_use_policy ODMUse[__DML_NUM_PLANES__]; /// <brief ODM mode as selected by the user; used in mode check stage
638	enum dml_unbounded_requesting_policy UseUnboundedRequesting; ///< brief Unbounded request mode preference
639	enum dml_immediate_flip_requirement ImmediateFlipRequirement[__DML_NUM_PLANES__]; /// <brief Is immediate flip a requirement for this plane. When host vm is present iflip is needed regardless
640	enum dml_prefetch_modes AllowForPStateChangeOrStutterInVBlank[__DML_NUM_PLANES__]; /// <brief To specify if the DML should calculate the values for support different pwr saving features (cstate; pstate; etc.) during vblank
641
642	enum dml_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal;
643	bool UseOnlyMaxPrefetchModes;
644	dml_bool_t UseMinimumRequiredDCFCLK; //<brief When set the mode_check stage will figure the min DCFCLK freq to support the given display configuration. User can tell use the output DCFCLK for mode programming.
645	dml_bool_t DRAMClockChangeRequirementFinal;
646	dml_bool_t FCLKChangeRequirementFinal;
647	dml_bool_t USRRetrainingRequiredFinal;
648	dml_bool_t EnhancedPrefetchScheduleAccelerationFinal;
649
650	dml_bool_t NomDETInKByteOverrideEnable; //<brief Nomimal DET buffer size for a pipe. If this size fit the required 2 swathes; DML will use this DET size
651	dml_uint_t NomDETInKByteOverrideValue;
652
653	dml_bool_t DCCProgrammingAssumesScanDirectionUnknownFinal;
654	dml_bool_t SynchronizeTimingsFinal;
655	dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
656	dml_bool_t AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the DRAM clock change is not support (assuming the soc will be stay in max power state)
657	dml_bool_t AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the Fabric clock change is not support (assuming the soc will be stay in max power state
658	};
659
660	/// @brief Contains important information after the mode support steps. Also why a mode is not supported.
661	struct dml_mode_support_info_st {
662	//-----------------
663	// Mode Support Information
664	//-----------------
665	dml_bool_t ModeIsSupported; //<brief Is the mode support any voltage and combine setting
666	dml_bool_t ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming
667	dml_uint_t MaximumMPCCombine; //<brief If using MPC combine helps the power saving support; then this will be set to 1
668	dml_bool_t UnboundedRequestEnabled;
669	dml_uint_t CompressedBufferSizeInkByte;
670
671	/* Mode Support Reason */
672	dml_bool_t WritebackLatencySupport;
673	dml_bool_t ScaleRatioAndTapsSupport;
674	dml_bool_t SourceFormatPixelAndScanSupport;
675	dml_bool_t MPCCombineMethodIncompatible;
676	dml_bool_t P2IWith420;
677	dml_bool_t DSCOnlyIfNecessaryWithBPP;
678	dml_bool_t DSC422NativeNotSupported;
679	dml_bool_t LinkRateDoesNotMatchDPVersion;
680	dml_bool_t LinkRateForMultistreamNotIndicated;
681	dml_bool_t BPPForMultistreamNotIndicated;
682	dml_bool_t MultistreamWithHDMIOreDP;
683	dml_bool_t MSOOrODMSplitWithNonDPLink;
684	dml_bool_t NotEnoughLanesForMSO;
685	dml_bool_t NumberOfOTGSupport;
686	dml_bool_t NumberOfHDMIFRLSupport;
687	dml_bool_t NumberOfDP2p0Support;
688	dml_bool_t NonsupportedDSCInputBPC;
689	dml_bool_t WritebackScaleRatioAndTapsSupport;
690	dml_bool_t CursorSupport;
691	dml_bool_t PitchSupport;
692	dml_bool_t ViewportExceedsSurface;
693	dml_bool_t ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
694	dml_bool_t ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
695	dml_bool_t InvalidCombinationOfMALLUseForPStateAndStaticScreen;
696	dml_bool_t InvalidCombinationOfMALLUseForPState;
697	dml_bool_t ExceededMALLSize;
698	dml_bool_t EnoughWritebackUnits;
699
700	dml_bool_t ExceededMultistreamSlots;
701	dml_bool_t ODMCombineTwoToOneSupportCheckOK;
702	dml_bool_t ODMCombineFourToOneSupportCheckOK;
703	dml_bool_t NotEnoughDSCUnits;
704	dml_bool_t NotEnoughDSCSlices;
705	dml_bool_t PixelsPerLinePerDSCUnitSupport;
706	dml_bool_t DSCCLKRequiredMoreThanSupported;
707	dml_bool_t DTBCLKRequiredMoreThanSupported;
708	dml_bool_t LinkCapacitySupport;
709
710	dml_bool_t ROBSupport[2];
711	dml_bool_t PTEBufferSizeNotExceeded[2];
712	dml_bool_t DCCMetaBufferSizeNotExceeded[2];
713	dml_bool_t TotalVerticalActiveBandwidthSupport[2];
714	enum dml_dram_clock_change_support DRAMClockChangeSupport[2];
715	dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__];
716	dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];
717	enum dml_fclock_change_support FCLKChangeSupport[2];
718	dml_bool_t USRRetrainingSupport[2];
719	dml_bool_t VActiveBandwithSupport[2];
720	dml_bool_t PrefetchSupported[2];
721	dml_bool_t DynamicMetadataSupported[2];
722	dml_bool_t VRatioInPrefetchSupported[2];
723	dml_bool_t DISPCLK_DPPCLK_Support[2];
724	dml_bool_t TotalAvailablePipesSupport[2];
725	dml_bool_t ModeSupport[2];
726	dml_bool_t ViewportSizeSupport[2];
727	dml_bool_t ImmediateFlipSupportedForState[2];
728
729	dml_bool_t NoTimeForPrefetch[2][__DML_NUM_PLANES__];
730	dml_bool_t NoTimeForDynamicMetadata[2][__DML_NUM_PLANES__];
731
732	dml_bool_t MPCCombineEnable[__DML_NUM_PLANES__]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting
733	enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
734	dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.
735	dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is actually required; used in mode_programming
736	dml_bool_t FECEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the FEC is actually required
737	dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode
738
739	dml_float_t OutputBpp[__DML_NUM_PLANES__];
740	enum dml_output_type_and_rate__type OutputType[__DML_NUM_PLANES__];
741	enum dml_output_type_and_rate__rate OutputRate[__DML_NUM_PLANES__];
742
743	dml_float_t AlignedDCCMetaPitchY[__DML_NUM_PLANES__]; /// <brief Pitch value that is aligned to tiling setting
744	dml_float_t AlignedDCCMetaPitchC[__DML_NUM_PLANES__];
745	dml_float_t AlignedYPitch[__DML_NUM_PLANES__];
746	dml_float_t AlignedCPitch[__DML_NUM_PLANES__];
747	dml_float_t MaxTotalVerticalActiveAvailableBandwidth[2]; /// <brief nominal bw available for display
748	}; // dml_mode_support_info_st
749
750	/// @brief Treat this as the intermediate values and outputs of mode check function. User can query the content of the struct to know more about the result of mode evaluation.
751	struct mode_support_st {
752	struct ip_params_st ip;
753	struct soc_bounding_box_st soc;
754	struct soc_state_bounding_box_st state; //<brief Per-state bbox values; only 1 state per compute
755	struct dml_mode_eval_policy_st policy;
756
757	dml_uint_t state_idx; //<brief The power state idx for the power state under this computation
758	dml_uint_t max_state_idx; //<brief The MAX power state idx
759	struct soc_state_bounding_box_st max_state; //<brief The MAX power state; some algo needs to know the max state info to determine if
760	struct dml_display_cfg_st cache_display_cfg; // <brief A copy of the current display cfg in consideration
761
762	// Physical info; only using for programming
763	dml_uint_t num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg
764
765	// Calculated Clocks
766	dml_float_t RequiredDISPCLK[2]; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc.
767	dml_float_t RequiredDPPCLKThisState[__DML_NUM_PLANES__];
768	dml_float_t DCFCLKState[2]; /// <brief recommended DCFCLK freq; calculated by DML. If UseMinimumRequiredDCFCLK is not set; then it will be just the state DCFCLK; else it will min DCFCLK for support
769	dml_float_t RequiredDISPCLKPerSurface[2][__DML_NUM_PLANES__];
770	dml_float_t RequiredDPPCLKPerSurface[2][__DML_NUM_PLANES__];
771
772	dml_float_t FabricClock; /// <brief Basically just the clock freq at the min (or given) state
773	dml_float_t DRAMSpeed; /// <brief Basically just the clock freq at the min (or given) state
774	dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
775	dml_float_t DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
776	dml_float_t GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes
777
778	// ----------------------------------
779	// Mode Support Info and fail reason
780	// ----------------------------------
781	struct dml_mode_support_info_st support;
782
783	// These are calculated before the ModeSupport and ModeProgram step
784	// They represent the bound for the return buffer sizing
785	dml_uint_t MaxTotalDETInKByte;
786	dml_uint_t NomDETInKByte;
787	dml_uint_t MinCompressedBufferSizeInKByte;
788
789	// Info obtained at the end of mode support calculations
790	// The reported info is at the "optimal" state and combine setting
791	dml_float_t ReturnBW;
792	dml_float_t ReturnDRAMBW;
793	dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
794	dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__];
795	dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__];
796	dml_uint_t SwathHeightY[__DML_NUM_PLANES__];
797	dml_uint_t SwathHeightC[__DML_NUM_PLANES__];
798
799	// ----------------------------------
800	// Intermediates/Informational
801	// ----------------------------------
802	dml_uint_t TotImmediateFlipBytes;
803	dml_bool_t DCCEnabledInAnySurface;
804	dml_float_t WritebackRequiredDISPCLK;
805	dml_float_t TimeCalc;
806	dml_float_t TWait;
807
808	dml_uint_t SwathWidthYAllStates[2][__DML_NUM_PLANES__];
809	dml_uint_t SwathWidthCAllStates[2][__DML_NUM_PLANES__];
810	dml_uint_t SwathHeightYAllStates[2][__DML_NUM_PLANES__];
811	dml_uint_t SwathHeightCAllStates[2][__DML_NUM_PLANES__];
812	dml_uint_t SwathWidthYThisState[__DML_NUM_PLANES__];
813	dml_uint_t SwathWidthCThisState[__DML_NUM_PLANES__];
814	dml_uint_t SwathHeightYThisState[__DML_NUM_PLANES__];
815	dml_uint_t SwathHeightCThisState[__DML_NUM_PLANES__];
816	dml_uint_t DETBufferSizeInKByteAllStates[2][__DML_NUM_PLANES__];
817	dml_uint_t DETBufferSizeYAllStates[2][__DML_NUM_PLANES__];
818	dml_uint_t DETBufferSizeCAllStates[2][__DML_NUM_PLANES__];
819	dml_bool_t UnboundedRequestEnabledAllStates[2];
820	dml_uint_t CompressedBufferSizeInkByteAllStates[2];
821	dml_bool_t UnboundedRequestEnabledThisState;
822	dml_uint_t CompressedBufferSizeInkByteThisState;
823	dml_uint_t DETBufferSizeInKByteThisState[__DML_NUM_PLANES__];
824	dml_uint_t DETBufferSizeYThisState[__DML_NUM_PLANES__];
825	dml_uint_t DETBufferSizeCThisState[__DML_NUM_PLANES__];
826	dml_float_t VRatioPreY[2][__DML_NUM_PLANES__];
827	dml_float_t VRatioPreC[2][__DML_NUM_PLANES__];
828	dml_uint_t swath_width_luma_ub_all_states[2][__DML_NUM_PLANES__];
829	dml_uint_t swath_width_chroma_ub_all_states[2][__DML_NUM_PLANES__];
830	dml_uint_t swath_width_luma_ub_this_state[__DML_NUM_PLANES__];
831	dml_uint_t swath_width_chroma_ub_this_state[__DML_NUM_PLANES__];
832	dml_uint_t RequiredSlots[__DML_NUM_PLANES__];
833	dml_uint_t PDEAndMetaPTEBytesPerFrame[2][__DML_NUM_PLANES__];
834	dml_uint_t MetaRowBytes[2][__DML_NUM_PLANES__];
835	dml_uint_t DPTEBytesPerRow[2][__DML_NUM_PLANES__];
836	dml_uint_t PrefetchLinesY[2][__DML_NUM_PLANES__];
837	dml_uint_t PrefetchLinesC[2][__DML_NUM_PLANES__];
838	dml_uint_t MaxNumSwY[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch
839	dml_uint_t MaxNumSwC[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch
840	dml_uint_t PrefillY[__DML_NUM_PLANES__];
841	dml_uint_t PrefillC[__DML_NUM_PLANES__];
842
843	dml_uint_t PrefetchLinesYThisState[__DML_NUM_PLANES__];
844	dml_uint_t PrefetchLinesCThisState[__DML_NUM_PLANES__];
845	dml_uint_t DPTEBytesPerRowThisState[__DML_NUM_PLANES__];
846	dml_uint_t PDEAndMetaPTEBytesPerFrameThisState[__DML_NUM_PLANES__];
847	dml_uint_t MetaRowBytesThisState[__DML_NUM_PLANES__];
848	dml_bool_t use_one_row_for_frame[2][__DML_NUM_PLANES__];
849	dml_bool_t use_one_row_for_frame_flip[2][__DML_NUM_PLANES__];
850	dml_bool_t use_one_row_for_frame_this_state[__DML_NUM_PLANES__];
851	dml_bool_t use_one_row_for_frame_flip_this_state[__DML_NUM_PLANES__];
852
853	dml_float_t LineTimesForPrefetch[__DML_NUM_PLANES__];
854	dml_float_t LinesForMetaPTE[__DML_NUM_PLANES__];
855	dml_float_t LinesForMetaAndDPTERow[__DML_NUM_PLANES__];
856	dml_float_t SwathWidthYSingleDPP[__DML_NUM_PLANES__];
857	dml_float_t SwathWidthCSingleDPP[__DML_NUM_PLANES__];
858	dml_uint_t BytePerPixelY[__DML_NUM_PLANES__];
859	dml_uint_t BytePerPixelC[__DML_NUM_PLANES__];
860	dml_float_t BytePerPixelInDETY[__DML_NUM_PLANES__];
861	dml_float_t BytePerPixelInDETC[__DML_NUM_PLANES__];
862
863	dml_uint_t Read256BlockHeightY[__DML_NUM_PLANES__];
864	dml_uint_t Read256BlockWidthY[__DML_NUM_PLANES__];
865	dml_uint_t Read256BlockHeightC[__DML_NUM_PLANES__];
866	dml_uint_t Read256BlockWidthC[__DML_NUM_PLANES__];
867	dml_uint_t MacroTileHeightY[__DML_NUM_PLANES__];
868	dml_uint_t MacroTileHeightC[__DML_NUM_PLANES__];
869	dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__];
870	dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__];
871	dml_float_t PSCL_FACTOR[__DML_NUM_PLANES__];
872	dml_float_t PSCL_FACTOR_CHROMA[__DML_NUM_PLANES__];
873	dml_float_t MaximumSwathWidthLuma[__DML_NUM_PLANES__];
874	dml_float_t MaximumSwathWidthChroma[__DML_NUM_PLANES__];
875	dml_float_t Tno_bw[__DML_NUM_PLANES__];
876	dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__];
877	dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__];
878	dml_float_t WritebackDelayTime[__DML_NUM_PLANES__];
879	dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__];
880	dml_uint_t dpte_row_height[__DML_NUM_PLANES__];
881	dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__];
882	dml_uint_t meta_row_height[__DML_NUM_PLANES__];
883	dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__];
884	dml_float_t UrgLatency;
885	dml_float_t UrgentBurstFactorCursor[__DML_NUM_PLANES__];
886	dml_float_t UrgentBurstFactorCursorPre[__DML_NUM_PLANES__];
887	dml_float_t UrgentBurstFactorLuma[__DML_NUM_PLANES__];
888	dml_float_t UrgentBurstFactorLumaPre[__DML_NUM_PLANES__];
889	dml_float_t UrgentBurstFactorChroma[__DML_NUM_PLANES__];
890	dml_float_t UrgentBurstFactorChromaPre[__DML_NUM_PLANES__];
891	dml_float_t MaximumSwathWidthInLineBufferLuma;
892	dml_float_t MaximumSwathWidthInLineBufferChroma;
893	dml_float_t ExtraLatency;
894
895	// Backend
896	dml_bool_t RequiresDSC[__DML_NUM_PLANES__];
897	dml_bool_t RequiresFEC[__DML_NUM_PLANES__];
898	dml_float_t OutputBppPerState[__DML_NUM_PLANES__];
899	dml_uint_t DSCDelayPerState[__DML_NUM_PLANES__];
900	enum dml_output_type_and_rate__type OutputTypePerState[__DML_NUM_PLANES__];
901	enum dml_output_type_and_rate__rate OutputRatePerState[__DML_NUM_PLANES__];
902
903	// Bandwidth Related Info
904	dml_float_t BandwidthAvailableForImmediateFlip;
905	dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__];
906	dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__];
907	dml_float_t WriteBandwidth[__DML_NUM_PLANES__];
908	dml_float_t RequiredPrefetchPixelDataBWLuma[__DML_NUM_PLANES__];
909	dml_float_t RequiredPrefetchPixelDataBWChroma[__DML_NUM_PLANES__];
910	dml_float_t cursor_bw[__DML_NUM_PLANES__];
911	dml_float_t cursor_bw_pre[__DML_NUM_PLANES__];
912	dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__];
913	dml_float_t final_flip_bw[__DML_NUM_PLANES__];
914	dml_float_t meta_row_bandwidth_this_state[__DML_NUM_PLANES__];
915	dml_float_t dpte_row_bandwidth_this_state[__DML_NUM_PLANES__];
916	dml_float_t ReturnBWPerState[2];
917	dml_float_t ReturnDRAMBWPerState[2];
918	dml_float_t meta_row_bandwidth[2][__DML_NUM_PLANES__];
919	dml_float_t dpte_row_bandwidth[2][__DML_NUM_PLANES__];
920
921	// Something that should be feedback to caller
922	enum dml_odm_mode ODMModePerState[__DML_NUM_PLANES__];
923	enum dml_odm_mode ODMModeThisState[__DML_NUM_PLANES__];
924	dml_uint_t SurfaceSizeInMALL[__DML_NUM_PLANES__];
925	dml_uint_t NoOfDPP[2][__DML_NUM_PLANES__];
926	dml_uint_t NoOfDPPThisState[__DML_NUM_PLANES__];
927	dml_bool_t MPCCombine[2][__DML_NUM_PLANES__];
928	dml_bool_t MPCCombineThisState[__DML_NUM_PLANES__];
929	dml_float_t ProjectedDCFCLKDeepSleep[2];
930	dml_float_t MinDPPCLKUsingSingleDPP[__DML_NUM_PLANES__];
931	dml_bool_t SingleDPPViewportSizeSupportPerSurface[__DML_NUM_PLANES__];
932	dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__];
933	dml_bool_t NotUrgentLatencyHiding[__DML_NUM_PLANES__];
934	dml_bool_t NotUrgentLatencyHidingPre[__DML_NUM_PLANES__];
935	dml_bool_t PTEBufferSizeNotExceededPerState[__DML_NUM_PLANES__];
936	dml_bool_t DCCMetaBufferSizeNotExceededPerState[__DML_NUM_PLANES__];
937	dml_uint_t PrefetchMode[__DML_NUM_PLANES__];
938	dml_uint_t TotalNumberOfActiveDPP[2];
939	dml_uint_t TotalNumberOfSingleDPPSurfaces[2];
940	dml_uint_t TotalNumberOfDCCActiveDPP[2];
941
942	dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];
943
944	}; // mode_support_st
945
946	/// @brief A mega structure that houses various info for model programming step.
947	struct mode_program_st {
948
949	//-------------
950	// Intermediate/Informational
951	//-------------
952	dml_float_t UrgentLatency;
953	dml_float_t UrgentLatencyWithUSRRetraining;
954	dml_uint_t VInitPreFillY[__DML_NUM_PLANES__];
955	dml_uint_t VInitPreFillC[__DML_NUM_PLANES__];
956	dml_uint_t MaxNumSwathY[__DML_NUM_PLANES__];
957	dml_uint_t MaxNumSwathC[__DML_NUM_PLANES__];
958
959	dml_float_t BytePerPixelDETY[__DML_NUM_PLANES__];
960	dml_float_t BytePerPixelDETC[__DML_NUM_PLANES__];
961	dml_uint_t BytePerPixelY[__DML_NUM_PLANES__];
962	dml_uint_t BytePerPixelC[__DML_NUM_PLANES__];
963	dml_uint_t SwathWidthY[__DML_NUM_PLANES__];
964	dml_uint_t SwathWidthC[__DML_NUM_PLANES__];
965	dml_uint_t SwathWidthSingleDPPY[__DML_NUM_PLANES__];
966	dml_uint_t SwathWidthSingleDPPC[__DML_NUM_PLANES__];
967	dml_float_t ReadBandwidthSurfaceLuma[__DML_NUM_PLANES__];
968	dml_float_t ReadBandwidthSurfaceChroma[__DML_NUM_PLANES__];
969
970	dml_uint_t PixelPTEBytesPerRow[__DML_NUM_PLANES__];
971	dml_uint_t PDEAndMetaPTEBytesFrame[__DML_NUM_PLANES__];
972	dml_uint_t MetaRowByte[__DML_NUM_PLANES__];
973	dml_uint_t PrefetchSourceLinesY[__DML_NUM_PLANES__];
974	dml_float_t RequiredPrefetchPixDataBWLuma[__DML_NUM_PLANES__];
975	dml_float_t RequiredPrefetchPixDataBWChroma[__DML_NUM_PLANES__];
976	dml_uint_t PrefetchSourceLinesC[__DML_NUM_PLANES__];
977	dml_float_t PSCL_THROUGHPUT[__DML_NUM_PLANES__];
978	dml_float_t PSCL_THROUGHPUT_CHROMA[__DML_NUM_PLANES__];
979	dml_uint_t DSCDelay[__DML_NUM_PLANES__];
980	dml_float_t DPPCLKUsingSingleDPP[__DML_NUM_PLANES__];
981
982	dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__];
983	dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__];
984	dml_uint_t BlockHeight256BytesY[__DML_NUM_PLANES__];
985	dml_uint_t BlockHeight256BytesC[__DML_NUM_PLANES__];
986	dml_uint_t BlockWidth256BytesY[__DML_NUM_PLANES__];
987	dml_uint_t BlockWidth256BytesC[__DML_NUM_PLANES__];
988
989	dml_uint_t BlockHeightY[__DML_NUM_PLANES__];
990	dml_uint_t BlockHeightC[__DML_NUM_PLANES__];
991	dml_uint_t BlockWidthY[__DML_NUM_PLANES__];
992	dml_uint_t BlockWidthC[__DML_NUM_PLANES__];
993
994	dml_uint_t SurfaceSizeInTheMALL[__DML_NUM_PLANES__];
995	dml_float_t VRatioPrefetchY[__DML_NUM_PLANES__];
996	dml_float_t VRatioPrefetchC[__DML_NUM_PLANES__];
997	dml_float_t Tno_bw[__DML_NUM_PLANES__];
998	dml_float_t final_flip_bw[__DML_NUM_PLANES__];
999	dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__];
1000	dml_float_t cursor_bw[__DML_NUM_PLANES__];
1001	dml_float_t cursor_bw_pre[__DML_NUM_PLANES__];
1002	dml_float_t WritebackDelay[__DML_NUM_PLANES__];
1003	dml_uint_t dpte_row_height[__DML_NUM_PLANES__];
1004	dml_uint_t dpte_row_height_linear[__DML_NUM_PLANES__];
1005	dml_uint_t meta_req_width[__DML_NUM_PLANES__];
1006	dml_uint_t meta_req_height[__DML_NUM_PLANES__];
1007	dml_uint_t meta_row_width[__DML_NUM_PLANES__];
1008	dml_uint_t meta_row_height[__DML_NUM_PLANES__];
1009	dml_uint_t dpte_row_width_luma_ub[__DML_NUM_PLANES__];
1010	dml_uint_t dpte_row_width_chroma_ub[__DML_NUM_PLANES__];
1011	dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__];
1012	dml_uint_t dpte_row_height_linear_chroma[__DML_NUM_PLANES__];
1013	dml_uint_t meta_req_width_chroma[__DML_NUM_PLANES__];
1014	dml_uint_t meta_req_height_chroma[__DML_NUM_PLANES__];
1015	dml_uint_t meta_row_width_chroma[__DML_NUM_PLANES__];
1016	dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__];
1017	dml_uint_t vm_group_bytes[__DML_NUM_PLANES__];
1018	dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__];
1019	dml_float_t meta_row_bw[__DML_NUM_PLANES__];
1020	dml_float_t dpte_row_bw[__DML_NUM_PLANES__];
1021	dml_float_t UrgBurstFactorCursor[__DML_NUM_PLANES__];
1022	dml_float_t UrgBurstFactorCursorPre[__DML_NUM_PLANES__];
1023	dml_float_t UrgBurstFactorLuma[__DML_NUM_PLANES__];
1024	dml_float_t UrgBurstFactorLumaPre[__DML_NUM_PLANES__];
1025	dml_float_t UrgBurstFactorChroma[__DML_NUM_PLANES__];
1026	dml_float_t UrgBurstFactorChromaPre[__DML_NUM_PLANES__];
1027
1028	dml_uint_t swath_width_luma_ub[__DML_NUM_PLANES__];
1029	dml_uint_t swath_width_chroma_ub[__DML_NUM_PLANES__];
1030	dml_uint_t PixelPTEReqWidthY[__DML_NUM_PLANES__];
1031	dml_uint_t PixelPTEReqHeightY[__DML_NUM_PLANES__];
1032	dml_uint_t PTERequestSizeY[__DML_NUM_PLANES__];
1033	dml_uint_t PixelPTEReqWidthC[__DML_NUM_PLANES__];
1034	dml_uint_t PixelPTEReqHeightC[__DML_NUM_PLANES__];
1035	dml_uint_t PTERequestSizeC[__DML_NUM_PLANES__];
1036
1037	dml_float_t Tdmdl_vm[__DML_NUM_PLANES__];
1038	dml_float_t Tdmdl[__DML_NUM_PLANES__];
1039	dml_float_t TSetup[__DML_NUM_PLANES__];
1040	dml_uint_t dpde0_bytes_per_frame_ub_l[__DML_NUM_PLANES__];
1041	dml_uint_t meta_pte_bytes_per_frame_ub_l[__DML_NUM_PLANES__];
1042	dml_uint_t dpde0_bytes_per_frame_ub_c[__DML_NUM_PLANES__];
1043	dml_uint_t meta_pte_bytes_per_frame_ub_c[__DML_NUM_PLANES__];
1044
1045	dml_bool_t UnboundedRequestEnabled;
1046	dml_uint_t compbuf_reserved_space_64b;
1047	dml_uint_t compbuf_reserved_space_zs;
1048	dml_uint_t CompressedBufferSizeInkByte;
1049
1050	dml_bool_t NoUrgentLatencyHiding[__DML_NUM_PLANES__];
1051	dml_bool_t NoUrgentLatencyHidingPre[__DML_NUM_PLANES__];
1052	dml_float_t UrgentExtraLatency;
1053	dml_bool_t PrefetchAndImmediateFlipSupported;
1054	dml_float_t TotalDataReadBandwidth;
1055	dml_float_t BandwidthAvailableForImmediateFlip;
1056	dml_bool_t NotEnoughTimeForDynamicMetadata[__DML_NUM_PLANES__];
1057
1058	dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__];
1059	dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__];
1060
1061	dml_float_t total_dcn_read_bw_with_flip;
1062	dml_float_t total_dcn_read_bw_with_flip_no_urgent_burst;
1063	dml_float_t TotalDataReadBandwidthNotIncludingMALLPrefetch;
1064	dml_float_t total_dcn_read_bw_with_flip_not_including_MALL_prefetch;
1065	dml_float_t non_urgent_total_dcn_read_bw_with_flip;
1066	dml_float_t non_urgent_total_dcn_read_bw_with_flip_not_including_MALL_prefetch;
1067
1068	dml_bool_t use_one_row_for_frame[__DML_NUM_PLANES__];
1069	dml_bool_t use_one_row_for_frame_flip[__DML_NUM_PLANES__];
1070
1071	dml_float_t TCalc;
1072	dml_uint_t TotImmediateFlipBytes;
1073
1074	// -------------------
1075	// Output
1076	// -------------------
1077	dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe
1078	dml_uint_t num_active_pipes;
1079
1080	dml_bool_t NoTimeToPrefetch[__DML_NUM_PLANES__]; /// <brief Prefetch schedule calculation result
1081
1082	// Support
1083	dml_uint_t PrefetchMode[__DML_NUM_PLANES__]; /// <brief prefetch mode used for prefetch support check in mode programming step
1084	dml_bool_t PrefetchModeSupported; /// <brief Is the prefetch mode (bandwidth and latency) supported
1085	dml_bool_t ImmediateFlipSupported;
1086	dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__];
1087
1088	// Clock
1089	dml_float_t Dcfclk;
1090	dml_float_t Dispclk; /// <brief dispclk being used in mode programming
1091	dml_float_t Dppclk[__DML_NUM_PLANES__]; /// <brief dppclk being used in mode programming
1092	dml_float_t WritebackDISPCLK;
1093	dml_float_t GlobalDPPCLK;
1094
1095	//@ brief These "calculated" dispclk and dppclk clocks are calculated in the mode programming step.
1096	// Depends on the dml_clk_cfg_st option; these calculated values may not used in subsequent calculation.
1097	// Possible DV usage: Calculated values fetched by test once after mode_programming step and then possibly
1098	// use the values as min and adjust the actual freq used for the 2nd pass
1099	dml_float_t Dispclk_calculated;
1100	dml_float_t Dppclk_calculated[__DML_NUM_PLANES__];
1101
1102	dml_float_t DSCCLK_calculated[__DML_NUM_PLANES__]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now
1103	dml_float_t DCFCLKDeepSleep;
1104
1105	// ARB reg
1106	dml_bool_t DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
1107	struct Watermarks Watermark;
1108
1109	// DCC compression control
1110	dml_uint_t DCCYMaxUncompressedBlock[__DML_NUM_PLANES__];
1111	dml_uint_t DCCYMaxCompressedBlock[__DML_NUM_PLANES__];
1112	dml_uint_t DCCYIndependentBlock[__DML_NUM_PLANES__];
1113	dml_uint_t DCCCMaxUncompressedBlock[__DML_NUM_PLANES__];
1114	dml_uint_t DCCCMaxCompressedBlock[__DML_NUM_PLANES__];
1115	dml_uint_t DCCCIndependentBlock[__DML_NUM_PLANES__];
1116
1117	// Stutter Efficiency
1118	dml_float_t StutterEfficiency;
1119	dml_float_t StutterEfficiencyNotIncludingVBlank;
1120	dml_uint_t NumberOfStutterBurstsPerFrame;
1121	dml_float_t Z8StutterEfficiency;
1122	dml_uint_t Z8NumberOfStutterBurstsPerFrame;
1123	dml_float_t Z8StutterEfficiencyNotIncludingVBlank;
1124	dml_float_t StutterPeriod;
1125	dml_float_t Z8StutterEfficiencyBestCase;
1126	dml_uint_t Z8NumberOfStutterBurstsPerFrameBestCase;
1127	dml_float_t Z8StutterEfficiencyNotIncludingVBlankBestCase;
1128	dml_float_t StutterPeriodBestCase;
1129
1130	// DLG TTU reg
1131	dml_float_t MIN_DST_Y_NEXT_START[__DML_NUM_PLANES__];
1132	dml_bool_t VREADY_AT_OR_AFTER_VSYNC[__DML_NUM_PLANES__];
1133	dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__];
1134	dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__];
1135	dml_float_t DestinationLinesForPrefetch[__DML_NUM_PLANES__];
1136	dml_float_t DestinationLinesToRequestVMInVBlank[__DML_NUM_PLANES__];
1137	dml_float_t DestinationLinesToRequestRowInVBlank[__DML_NUM_PLANES__];
1138	dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__];
1139	dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__];
1140	dml_float_t MinTTUVBlank[__DML_NUM_PLANES__];
1141	dml_float_t DisplayPipeLineDeliveryTimeLuma[__DML_NUM_PLANES__];
1142	dml_float_t DisplayPipeLineDeliveryTimeChroma[__DML_NUM_PLANES__];
1143	dml_float_t DisplayPipeLineDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__];
1144	dml_float_t DisplayPipeLineDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__];
1145	dml_float_t DisplayPipeRequestDeliveryTimeLuma[__DML_NUM_PLANES__];
1146	dml_float_t DisplayPipeRequestDeliveryTimeChroma[__DML_NUM_PLANES__];
1147	dml_float_t DisplayPipeRequestDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__];
1148	dml_float_t DisplayPipeRequestDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__];
1149	dml_float_t CursorRequestDeliveryTime[__DML_NUM_PLANES__];
1150	dml_float_t CursorRequestDeliveryTimePrefetch[__DML_NUM_PLANES__];
1151
1152	dml_float_t DST_Y_PER_PTE_ROW_NOM_L[__DML_NUM_PLANES__];
1153	dml_float_t DST_Y_PER_PTE_ROW_NOM_C[__DML_NUM_PLANES__];
1154	dml_float_t DST_Y_PER_META_ROW_NOM_L[__DML_NUM_PLANES__];
1155	dml_float_t DST_Y_PER_META_ROW_NOM_C[__DML_NUM_PLANES__];
1156	dml_float_t TimePerMetaChunkNominal[__DML_NUM_PLANES__];
1157	dml_float_t TimePerChromaMetaChunkNominal[__DML_NUM_PLANES__];
1158	dml_float_t TimePerMetaChunkVBlank[__DML_NUM_PLANES__];
1159	dml_float_t TimePerChromaMetaChunkVBlank[__DML_NUM_PLANES__];
1160	dml_float_t TimePerMetaChunkFlip[__DML_NUM_PLANES__];
1161	dml_float_t TimePerChromaMetaChunkFlip[__DML_NUM_PLANES__];
1162	dml_float_t time_per_pte_group_nom_luma[__DML_NUM_PLANES__];
1163	dml_float_t time_per_pte_group_nom_chroma[__DML_NUM_PLANES__];
1164	dml_float_t time_per_pte_group_vblank_luma[__DML_NUM_PLANES__];
1165	dml_float_t time_per_pte_group_vblank_chroma[__DML_NUM_PLANES__];
1166	dml_float_t time_per_pte_group_flip_luma[__DML_NUM_PLANES__];
1167	dml_float_t time_per_pte_group_flip_chroma[__DML_NUM_PLANES__];
1168	dml_float_t TimePerVMGroupVBlank[__DML_NUM_PLANES__];
1169	dml_float_t TimePerVMGroupFlip[__DML_NUM_PLANES__];
1170	dml_float_t TimePerVMRequestVBlank[__DML_NUM_PLANES__];
1171	dml_float_t TimePerVMRequestFlip[__DML_NUM_PLANES__];
1172
1173	dml_float_t FractionOfUrgentBandwidth;
1174	dml_float_t FractionOfUrgentBandwidthImmediateFlip;
1175
1176	// RQ registers
1177	dml_bool_t PTE_BUFFER_MODE[__DML_NUM_PLANES__];
1178	dml_uint_t BIGK_FRAGMENT_SIZE[__DML_NUM_PLANES__];
1179
1180	dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];
1181	dml_bool_t UsesMALLForStaticScreen[__DML_NUM_PLANES__];
1182
1183	// OTG
1184	dml_uint_t VStartupMin[__DML_NUM_PLANES__]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.
1185	dml_uint_t VStartup[__DML_NUM_PLANES__]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank))
1186	dml_uint_t VUpdateOffsetPix[__DML_NUM_PLANES__];
1187	dml_uint_t VUpdateWidthPix[__DML_NUM_PLANES__];
1188	dml_uint_t VReadyOffsetPix[__DML_NUM_PLANES__];
1189
1190	// Latency and Support
1191	dml_float_t MaxActiveFCLKChangeLatencySupported;
1192	dml_bool_t USRRetrainingSupport;
1193	enum dml_fclock_change_support FCLKChangeSupport;
1194	enum dml_dram_clock_change_support DRAMClockChangeSupport;
1195	dml_float_t MaxActiveDRAMClockChangeLatencySupported[__DML_NUM_PLANES__];
1196	dml_float_t WritebackAllowFCLKChangeEndPosition[__DML_NUM_PLANES__];
1197	dml_float_t WritebackAllowDRAMClockChangeEndPosition[__DML_NUM_PLANES__];
1198
1199	// buffer sizing
1200	dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
1201	dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__];
1202	dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__];
1203	dml_uint_t SwathHeightY[__DML_NUM_PLANES__];
1204	dml_uint_t SwathHeightC[__DML_NUM_PLANES__];
1205	}; // mode_program_st
1206
1207	struct soc_states_st {
1208	dml_uint_t num_states; /// <brief num of soc pwr states
1209	struct soc_state_bounding_box_st state_array[__DML_MAX_STATE_ARRAY_SIZE__]; /// <brief fixed size array that holds states struct
1210	};
1211
1212	struct UseMinimumDCFCLK_params_st {
1213	enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange;
1214	dml_bool_t *DRRDisplay;
1215	dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
1216	dml_uint_t MaxInterDCNTileRepeaters;
1217	dml_uint_t MaxPrefetchMode;
1218	dml_float_t DRAMClockChangeLatencyFinal;
1219	dml_float_t FCLKChangeLatency;
1220	dml_float_t SREnterPlusExitTime;
1221	dml_uint_t ReturnBusWidth;
1222	dml_uint_t RoundTripPingLatencyCycles;
1223	dml_uint_t ReorderingBytes;
1224	dml_uint_t PixelChunkSizeInKByte;
1225	dml_uint_t MetaChunkSize;
1226	dml_bool_t GPUVMEnable;
1227	dml_uint_t GPUVMMaxPageTableLevels;
1228	dml_bool_t HostVMEnable;
1229	dml_uint_t NumberOfActiveSurfaces;
1230	dml_uint_t HostVMMinPageSize;
1231	dml_uint_t HostVMMaxNonCachedPageTableLevels;
1232	dml_bool_t DynamicMetadataVMEnabled;
1233	dml_bool_t ImmediateFlipRequirement;
1234	dml_bool_t ProgressiveToInterlaceUnitInOPP;
1235	dml_float_t MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation;
1236	dml_float_t PercentOfIdealSDPPortBWReceivedAfterUrgLatency;
1237	dml_uint_t *VTotal;
1238	dml_uint_t *VActive;
1239	dml_uint_t *DynamicMetadataTransmittedBytes;
1240	dml_uint_t *DynamicMetadataLinesBeforeActiveRequired;
1241	dml_bool_t *Interlace;
1242	dml_float_t (*RequiredDPPCLKPerSurface)[__DML_NUM_PLANES__];
1243	dml_float_t *RequiredDISPCLK;
1244	dml_float_t UrgLatency;
1245	dml_uint_t (*NoOfDPP)[__DML_NUM_PLANES__];
1246	dml_float_t *ProjectedDCFCLKDeepSleep;
1247	dml_uint_t (*MaximumVStartup)[__DML_NUM_PLANES__];
1248	dml_uint_t *TotalNumberOfActiveDPP;
1249	dml_uint_t *TotalNumberOfDCCActiveDPP;
1250	dml_uint_t *dpte_group_bytes;
1251	dml_uint_t (*PrefetchLinesY)[__DML_NUM_PLANES__];
1252	dml_uint_t (*PrefetchLinesC)[__DML_NUM_PLANES__];
1253	dml_uint_t (*swath_width_luma_ub_all_states)[__DML_NUM_PLANES__];
1254	dml_uint_t (*swath_width_chroma_ub_all_states)[__DML_NUM_PLANES__];
1255	dml_uint_t *BytePerPixelY;
1256	dml_uint_t *BytePerPixelC;
1257	dml_uint_t *HTotal;
1258	dml_float_t *PixelClock;
1259	dml_uint_t (*PDEAndMetaPTEBytesPerFrame)[__DML_NUM_PLANES__];
1260	dml_uint_t (*DPTEBytesPerRow)[__DML_NUM_PLANES__];
1261	dml_uint_t (*MetaRowBytes)[__DML_NUM_PLANES__];
1262	dml_bool_t *DynamicMetadataEnable;
1263	dml_float_t *ReadBandwidthLuma;
1264	dml_float_t *ReadBandwidthChroma;
1265	dml_float_t DCFCLKPerState;
1266	dml_float_t *DCFCLKState;
1267	};
1268
1269	struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st {
1270	dml_bool_t USRRetrainingRequiredFinal;
1271	enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange;
1272	dml_uint_t *PrefetchMode;
1273	dml_uint_t NumberOfActiveSurfaces;
1274	dml_uint_t MaxLineBufferLines;
1275	dml_uint_t LineBufferSize;
1276	dml_uint_t WritebackInterfaceBufferSize;
1277	dml_float_t DCFCLK;
1278	dml_float_t ReturnBW;
1279	dml_bool_t SynchronizeTimingsFinal;
1280	dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
1281	dml_bool_t *DRRDisplay;
1282	dml_uint_t *dpte_group_bytes;
1283	dml_uint_t *meta_row_height;
1284	dml_uint_t *meta_row_height_chroma;
1285	struct SOCParametersList mmSOCParameters;
1286	dml_uint_t WritebackChunkSize;
1287	dml_float_t SOCCLK;
1288	dml_float_t DCFClkDeepSleep;
1289	dml_uint_t *DETBufferSizeY;
1290	dml_uint_t *DETBufferSizeC;
1291	dml_uint_t *SwathHeightY;
1292	dml_uint_t *SwathHeightC;
1293	dml_uint_t *LBBitPerPixel;
1294	dml_uint_t *SwathWidthY;
1295	dml_uint_t *SwathWidthC;
1296	dml_float_t *HRatio;
1297	dml_float_t *HRatioChroma;
1298	dml_uint_t *VTaps;
1299	dml_uint_t *VTapsChroma;
1300	dml_float_t *VRatio;
1301	dml_float_t *VRatioChroma;
1302	dml_uint_t *HTotal;
1303	dml_uint_t *VTotal;
1304	dml_uint_t *VActive;
1305	dml_float_t *PixelClock;
1306	dml_uint_t *BlendingAndTiming;
1307	dml_uint_t *DPPPerSurface;
1308	dml_float_t *BytePerPixelDETY;
1309	dml_float_t *BytePerPixelDETC;
1310	dml_uint_t *DSTXAfterScaler;
1311	dml_uint_t *DSTYAfterScaler;
1312	dml_bool_t *WritebackEnable;
1313	enum dml_source_format_class *WritebackPixelFormat;
1314	dml_uint_t *WritebackDestinationWidth;
1315	dml_uint_t *WritebackDestinationHeight;
1316	dml_uint_t *WritebackSourceHeight;
1317	dml_bool_t UnboundedRequestEnabled;
1318	dml_uint_t CompressedBufferSizeInkByte;
1319
1320	// Output
1321	struct Watermarks *Watermark;
1322	enum dml_dram_clock_change_support *DRAMClockChangeSupport;
1323	dml_float_t *MaxActiveDRAMClockChangeLatencySupported;
1324	dml_uint_t *SubViewportLinesNeededInMALL;
1325	enum dml_fclock_change_support *FCLKChangeSupport;
1326	dml_float_t *MaxActiveFCLKChangeLatencySupported;
1327	dml_bool_t *USRRetrainingSupport;
1328	dml_float_t *ActiveDRAMClockChangeLatencyMargin;
1329	};
1330
1331	struct CalculateVMRowAndSwath_params_st {
1332	dml_uint_t NumberOfActiveSurfaces;
1333	struct DmlPipe *myPipe;
1334	dml_uint_t *SurfaceSizeInMALL;
1335	dml_uint_t PTEBufferSizeInRequestsLuma;
1336	dml_uint_t PTEBufferSizeInRequestsChroma;
1337	dml_uint_t DCCMetaBufferSizeBytes;
1338	enum dml_use_mall_for_static_screen_mode *UseMALLForStaticScreen;
1339	enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange;
1340	dml_uint_t MALLAllocatedForDCN;
1341	dml_uint_t *SwathWidthY;
1342	dml_uint_t *SwathWidthC;
1343	dml_bool_t GPUVMEnable;
1344	dml_bool_t HostVMEnable;
1345	dml_uint_t HostVMMaxNonCachedPageTableLevels;
1346	dml_uint_t GPUVMMaxPageTableLevels;
1347	dml_uint_t *GPUVMMinPageSizeKBytes;
1348	dml_uint_t HostVMMinPageSize;
1349	dml_bool_t *PTEBufferModeOverrideEn;
1350	dml_bool_t *PTEBufferModeOverrideVal;
1351
1352	// Output
1353	dml_bool_t *PTEBufferSizeNotExceeded;
1354	dml_bool_t *DCCMetaBufferSizeNotExceeded;
1355	dml_uint_t *dpte_row_width_luma_ub;
1356	dml_uint_t *dpte_row_width_chroma_ub;
1357	dml_uint_t *dpte_row_height_luma;
1358	dml_uint_t *dpte_row_height_chroma;
1359	dml_uint_t *dpte_row_height_linear_luma; // VBA_DELTA
1360	dml_uint_t *dpte_row_height_linear_chroma; // VBA_DELTA
1361	dml_uint_t *meta_req_width;
1362	dml_uint_t *meta_req_width_chroma;
1363	dml_uint_t *meta_req_height;
1364	dml_uint_t *meta_req_height_chroma;
1365	dml_uint_t *meta_row_width;
1366	dml_uint_t *meta_row_width_chroma;
1367	dml_uint_t *meta_row_height;
1368	dml_uint_t *meta_row_height_chroma;
1369	dml_uint_t *vm_group_bytes;
1370	dml_uint_t *dpte_group_bytes;
1371	dml_uint_t *PixelPTEReqWidthY;
1372	dml_uint_t *PixelPTEReqHeightY;
1373	dml_uint_t *PTERequestSizeY;
1374	dml_uint_t *PixelPTEReqWidthC;
1375	dml_uint_t *PixelPTEReqHeightC;
1376	dml_uint_t *PTERequestSizeC;
1377	dml_uint_t *dpde0_bytes_per_frame_ub_l;
1378	dml_uint_t *meta_pte_bytes_per_frame_ub_l;
1379	dml_uint_t *dpde0_bytes_per_frame_ub_c;
1380	dml_uint_t *meta_pte_bytes_per_frame_ub_c;
1381	dml_uint_t *PrefetchSourceLinesY;
1382	dml_uint_t *PrefetchSourceLinesC;
1383	dml_uint_t *VInitPreFillY;
1384	dml_uint_t *VInitPreFillC;
1385	dml_uint_t *MaxNumSwathY;
1386	dml_uint_t *MaxNumSwathC;
1387	dml_float_t *meta_row_bw;
1388	dml_float_t *dpte_row_bw;
1389	dml_uint_t *PixelPTEBytesPerRow;
1390	dml_uint_t *PDEAndMetaPTEBytesFrame;
1391	dml_uint_t *MetaRowByte;
1392	dml_bool_t *use_one_row_for_frame;
1393	dml_bool_t *use_one_row_for_frame_flip;
1394	dml_bool_t *UsesMALLForStaticScreen;
1395	dml_bool_t *PTE_BUFFER_MODE;
1396	dml_uint_t *BIGK_FRAGMENT_SIZE;
1397	};
1398
1399	struct CalculateSwathAndDETConfiguration_params_st {
1400	dml_uint_t *DETSizeOverride;
1401	enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange;
1402	dml_uint_t ConfigReturnBufferSizeInKByte;
1403	dml_uint_t ROBBufferSizeInKByte;
1404	dml_uint_t MaxTotalDETInKByte;
1405	dml_uint_t MinCompressedBufferSizeInKByte;
1406	dml_uint_t PixelChunkSizeInKByte;
1407	dml_bool_t ForceSingleDPP;
1408	dml_uint_t NumberOfActiveSurfaces;
1409	dml_uint_t nomDETInKByte;
1410	enum dml_unbounded_requesting_policy UseUnboundedRequestingFinal;
1411	dml_uint_t ConfigReturnBufferSegmentSizeInkByte;
1412	dml_uint_t CompressedBufferSegmentSizeInkByteFinal;
1413	enum dml_output_encoder_class *Output;
1414	dml_float_t *ReadBandwidthLuma;
1415	dml_float_t *ReadBandwidthChroma;
1416	dml_float_t *MaximumSwathWidthLuma;
1417	dml_float_t *MaximumSwathWidthChroma;
1418	enum dml_rotation_angle *SourceScan;
1419	dml_bool_t *ViewportStationary;
1420	enum dml_source_format_class *SourcePixelFormat;
1421	enum dml_swizzle_mode *SurfaceTiling;
1422	dml_uint_t *ViewportWidth;
1423	dml_uint_t *ViewportHeight;
1424	dml_uint_t *ViewportXStart;
1425	dml_uint_t *ViewportYStart;
1426	dml_uint_t *ViewportXStartC;
1427	dml_uint_t *ViewportYStartC;
1428	dml_uint_t *SurfaceWidthY;
1429	dml_uint_t *SurfaceWidthC;
1430	dml_uint_t *SurfaceHeightY;
1431	dml_uint_t *SurfaceHeightC;
1432	dml_uint_t *Read256BytesBlockHeightY;
1433	dml_uint_t *Read256BytesBlockHeightC;
1434	dml_uint_t *Read256BytesBlockWidthY;
1435	dml_uint_t *Read256BytesBlockWidthC;
1436	enum dml_odm_mode *ODMMode;
1437	dml_uint_t *BlendingAndTiming;
1438	dml_uint_t *BytePerPixY;
1439	dml_uint_t *BytePerPixC;
1440	dml_float_t *BytePerPixDETY;
1441	dml_float_t *BytePerPixDETC;
1442	dml_uint_t *HActive;
1443	dml_float_t *HRatio;
1444	dml_float_t *HRatioChroma;
1445	dml_uint_t *DPPPerSurface;
1446	dml_uint_t *swath_width_luma_ub;
1447	dml_uint_t *swath_width_chroma_ub;
1448	dml_uint_t *SwathWidth;
1449	dml_uint_t *SwathWidthChroma;
1450	dml_uint_t *SwathHeightY;
1451	dml_uint_t *SwathHeightC;
1452	dml_uint_t *DETBufferSizeInKByte;
1453	dml_uint_t *DETBufferSizeY;
1454	dml_uint_t *DETBufferSizeC;
1455	dml_bool_t *UnboundedRequestEnabled;
1456	dml_uint_t *compbuf_reserved_space_64b;
1457	dml_uint_t *compbuf_reserved_space_zs;
1458	dml_uint_t *CompressedBufferSizeInkByte;
1459	dml_bool_t *ViewportSizeSupportPerSurface;
1460	dml_bool_t *ViewportSizeSupport;
1461	};
1462
1463	struct CalculateStutterEfficiency_params_st {
1464	dml_uint_t CompressedBufferSizeInkByte;
1465	enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange;
1466	dml_bool_t UnboundedRequestEnabled;
1467	dml_uint_t MetaFIFOSizeInKEntries;
1468	dml_uint_t ZeroSizeBufferEntries;
1469	dml_uint_t PixelChunkSizeInKByte;
1470	dml_uint_t NumberOfActiveSurfaces;
1471	dml_uint_t ROBBufferSizeInKByte;
1472	dml_float_t TotalDataReadBandwidth;
1473	dml_float_t DCFCLK;
1474	dml_float_t ReturnBW;
1475	dml_uint_t CompbufReservedSpace64B;
1476	dml_uint_t CompbufReservedSpaceZs;
1477	dml_float_t SRExitTime;
1478	dml_float_t SRExitZ8Time;
1479	dml_bool_t SynchronizeTimingsFinal;
1480	dml_uint_t *BlendingAndTiming;
1481	dml_float_t StutterEnterPlusExitWatermark;
1482	dml_float_t Z8StutterEnterPlusExitWatermark;
1483	dml_bool_t ProgressiveToInterlaceUnitInOPP;
1484	dml_bool_t *Interlace;
1485	dml_float_t *MinTTUVBlank;
1486	dml_uint_t *DPPPerSurface;
1487	dml_uint_t *DETBufferSizeY;
1488	dml_uint_t *BytePerPixelY;
1489	dml_float_t *BytePerPixelDETY;
1490	dml_uint_t *SwathWidthY;
1491	dml_uint_t *SwathHeightY;
1492	dml_uint_t *SwathHeightC;
1493	dml_float_t *NetDCCRateLuma;
1494	dml_float_t *NetDCCRateChroma;
1495	dml_float_t *DCCFractionOfZeroSizeRequestsLuma;
1496	dml_float_t *DCCFractionOfZeroSizeRequestsChroma;
1497	dml_uint_t *HTotal;
1498	dml_uint_t *VTotal;
1499	dml_float_t *PixelClock;
1500	dml_float_t *VRatio;
1501	enum dml_rotation_angle *SourceScan;
1502	dml_uint_t *BlockHeight256BytesY;
1503	dml_uint_t *BlockWidth256BytesY;
1504	dml_uint_t *BlockHeight256BytesC;
1505	dml_uint_t *BlockWidth256BytesC;
1506	dml_uint_t *DCCYMaxUncompressedBlock;
1507	dml_uint_t *DCCCMaxUncompressedBlock;
1508	dml_uint_t *VActive;
1509	dml_bool_t *DCCEnable;
1510	dml_bool_t *WritebackEnable;
1511	dml_float_t *ReadBandwidthSurfaceLuma;
1512	dml_float_t *ReadBandwidthSurfaceChroma;
1513	dml_float_t *meta_row_bw;
1514	dml_float_t *dpte_row_bw;
1515	dml_float_t *StutterEfficiencyNotIncludingVBlank;
1516	dml_float_t *StutterEfficiency;
1517	dml_uint_t *NumberOfStutterBurstsPerFrame;
1518	dml_float_t *Z8StutterEfficiencyNotIncludingVBlank;
1519	dml_float_t *Z8StutterEfficiency;
1520	dml_uint_t *Z8NumberOfStutterBurstsPerFrame;
1521	dml_float_t *StutterPeriod;
1522	dml_bool_t *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
1523	};
1524
1525	struct CalculatePrefetchSchedule_params_st {
1526	dml_bool_t EnhancedPrefetchScheduleAccelerationFinal;
1527	dml_float_t HostVMInefficiencyFactor;
1528	struct DmlPipe *myPipe;
1529	dml_uint_t DSCDelay;
1530	dml_float_t DPPCLKDelaySubtotalPlusCNVCFormater;
1531	dml_float_t DPPCLKDelaySCL;
1532	dml_float_t DPPCLKDelaySCLLBOnly;
1533	dml_float_t DPPCLKDelayCNVCCursor;
1534	dml_float_t DISPCLKDelaySubtotal;
1535	dml_uint_t DPP_RECOUT_WIDTH;
1536	enum dml_output_format_class OutputFormat;
1537	dml_uint_t MaxInterDCNTileRepeaters;
1538	dml_uint_t VStartup;
1539	dml_uint_t MaxVStartup;
1540	dml_uint_t GPUVMPageTableLevels;
1541	dml_bool_t GPUVMEnable;
1542	dml_bool_t HostVMEnable;
1543	dml_uint_t HostVMMaxNonCachedPageTableLevels;
1544	dml_uint_t HostVMMinPageSize;
1545	dml_bool_t DynamicMetadataEnable;
1546	dml_bool_t DynamicMetadataVMEnabled;
1547	int DynamicMetadataLinesBeforeActiveRequired;
1548	dml_uint_t DynamicMetadataTransmittedBytes;
1549	dml_float_t UrgentLatency;
1550	dml_float_t UrgentExtraLatency;
1551	dml_float_t TCalc;
1552	dml_uint_t PDEAndMetaPTEBytesFrame;
1553	dml_uint_t MetaRowByte;
1554	dml_uint_t PixelPTEBytesPerRow;
1555	dml_float_t PrefetchSourceLinesY;
1556	dml_uint_t VInitPreFillY;
1557	dml_uint_t MaxNumSwathY;
1558	dml_float_t PrefetchSourceLinesC;
1559	dml_uint_t VInitPreFillC;
1560	dml_uint_t MaxNumSwathC;
1561	dml_uint_t swath_width_luma_ub;
1562	dml_uint_t swath_width_chroma_ub;
1563	dml_uint_t SwathHeightY;
1564	dml_uint_t SwathHeightC;
1565	dml_float_t TWait;
1566	dml_uint_t *DSTXAfterScaler;
1567	dml_uint_t *DSTYAfterScaler;
1568	dml_float_t *DestinationLinesForPrefetch;
1569	dml_float_t *DestinationLinesToRequestVMInVBlank;
1570	dml_float_t *DestinationLinesToRequestRowInVBlank;
1571	dml_float_t *VRatioPrefetchY;
1572	dml_float_t *VRatioPrefetchC;
1573	dml_float_t *RequiredPrefetchPixDataBWLuma;
1574	dml_float_t *RequiredPrefetchPixDataBWChroma;
1575	dml_bool_t *NotEnoughTimeForDynamicMetadata;
1576	dml_float_t *Tno_bw;
1577	dml_float_t *prefetch_vmrow_bw;
1578	dml_float_t *Tdmdl_vm;
1579	dml_float_t *Tdmdl;
1580	dml_float_t *TSetup;
1581	dml_uint_t *VUpdateOffsetPix;
1582	dml_uint_t *VUpdateWidthPix;
1583	dml_uint_t *VReadyOffsetPix;
1584	};
1585
1586	struct dml_core_mode_support_locals_st {
1587	dml_bool_t dummy_boolean[2];
1588	dml_uint_t dummy_integer[3];
1589	dml_uint_t dummy_integer_array[22][__DML_NUM_PLANES__];
1590	enum dml_odm_mode dummy_odm_mode[__DML_NUM_PLANES__];
1591	dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__];
1592	dml_uint_t MaxVStartupAllPlanes[2];
1593	dml_uint_t MaximumVStartup[2][__DML_NUM_PLANES__];
1594	dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__];
1595	dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__];
1596	dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__];
1597	dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__];
1598	dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__];
1599	dml_float_t dummy_single[3];
1600	dml_float_t dummy_single_array[__DML_NUM_PLANES__];
1601	struct Watermarks dummy_watermark;
1602	struct SOCParametersList mSOCParameters;
1603	struct DmlPipe myPipe;
1604	struct DmlPipe SurfParameters[__DML_NUM_PLANES__];
1605	dml_uint_t TotalNumberOfActiveWriteback;
1606	dml_uint_t MaximumSwathWidthSupportLuma;
1607	dml_uint_t MaximumSwathWidthSupportChroma;
1608	dml_bool_t MPCCombineMethodAsNeededForPStateChangeAndVoltage;
1609	dml_bool_t MPCCombineMethodAsPossible;
1610	dml_bool_t TotalAvailablePipesSupportNoDSC;
1611	dml_uint_t NumberOfDPPNoDSC;
1612	enum dml_odm_mode ODMModeNoDSC;
1613	dml_float_t RequiredDISPCLKPerSurfaceNoDSC;
1614	dml_bool_t TotalAvailablePipesSupportDSC;
1615	dml_uint_t NumberOfDPPDSC;
1616	enum dml_odm_mode ODMModeDSC;
1617	dml_float_t RequiredDISPCLKPerSurfaceDSC;
1618	dml_bool_t NoChromaOrLinear;
1619	dml_float_t BWOfNonCombinedSurfaceOfMaximumBandwidth;
1620	dml_uint_t NumberOfNonCombinedSurfaceOfMaximumBandwidth;
1621	dml_uint_t TotalNumberOfActiveOTG;
1622	dml_uint_t TotalNumberOfActiveHDMIFRL;
1623	dml_uint_t TotalNumberOfActiveDP2p0;
1624	dml_uint_t TotalNumberOfActiveDP2p0Outputs;
1625	dml_uint_t TotalSlots;
1626	dml_uint_t DSCFormatFactor;
1627	dml_uint_t TotalDSCUnitsRequired;
1628	dml_uint_t ReorderingBytes;
1629	dml_bool_t ImmediateFlipRequiredFinal;
1630	dml_bool_t FullFrameMALLPStateMethod;
1631	dml_bool_t SubViewportMALLPStateMethod;
1632	dml_bool_t PhantomPipeMALLPStateMethod;
1633	dml_bool_t SubViewportMALLRefreshGreaterThan120Hz;
1634	dml_float_t MaxTotalVActiveRDBandwidth;
1635	dml_float_t VMDataOnlyReturnBWPerState;
1636	dml_float_t HostVMInefficiencyFactor;
1637	dml_uint_t NextMaxVStartup;
1638	dml_uint_t MaxVStartup;
1639	dml_bool_t AllPrefetchModeTested;
1640	dml_bool_t AnyLinesForVMOrRowTooLarge;
1641	dml_bool_t is_max_pwr_state;
1642	dml_bool_t is_max_dram_pwr_state;
1643	dml_bool_t dram_clock_change_support;
1644	dml_bool_t f_clock_change_support;
1645	};
1646
1647	struct dml_core_mode_programming_locals_st {
1648	dml_uint_t DSCFormatFactor;
1649	dml_uint_t dummy_integer_array[2][__DML_NUM_PLANES__];
1650	enum dml_output_encoder_class dummy_output_encoder_array[__DML_NUM_PLANES__];
1651	dml_float_t dummy_single_array[2][__DML_NUM_PLANES__];
1652	dml_uint_t dummy_long_array[4][__DML_NUM_PLANES__];
1653	dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__];
1654	dml_bool_t dummy_boolean[1];
1655	struct DmlPipe SurfaceParameters[__DML_NUM_PLANES__];
1656	dml_uint_t ReorderBytes;
1657	dml_float_t VMDataOnlyReturnBW;
1658	dml_float_t HostVMInefficiencyFactor;
1659	dml_uint_t TotalDCCActiveDPP;
1660	dml_uint_t TotalActiveDPP;
1661	dml_uint_t VStartupLines;
1662	dml_uint_t MaxVStartupLines[__DML_NUM_PLANES__]; /// <brief more like vblank for the plane's OTG
1663	dml_uint_t MaxVStartupAllPlanes;
1664	dml_bool_t ImmediateFlipRequirementFinal;
1665	int iteration;
1666	dml_float_t MaxTotalRDBandwidth;
1667	dml_float_t MaxTotalRDBandwidthNoUrgentBurst;
1668	dml_bool_t DestinationLineTimesForPrefetchLessThan2;
1669	dml_bool_t VRatioPrefetchMoreThanMax;
1670	dml_float_t MaxTotalRDBandwidthNotIncludingMALLPrefetch;
1671	dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__];
1672	dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__];
1673	dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__];
1674	dml_bool_t AllPrefetchModeTested;
1675	dml_float_t dummy_unit_vector[__DML_NUM_PLANES__];
1676	dml_float_t NonUrgentMaxTotalRDBandwidth;
1677	dml_float_t NonUrgentMaxTotalRDBandwidthNotIncludingMALLPrefetch;
1678	dml_float_t dummy_single[2];
1679	struct SOCParametersList mmSOCParameters;
1680	dml_float_t Tvstartup_margin;
1681	dml_float_t dlg_vblank_start;
1682	dml_float_t LSetup;
1683	dml_float_t blank_lines_remaining;
1684	dml_float_t old_MIN_DST_Y_NEXT_START;
1685	dml_float_t TotalWRBandwidth;
1686	dml_float_t WRBandwidth;
1687	struct Watermarks dummy_watermark;
1688	struct DmlPipe myPipe;
1689	};
1690
1691	struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st {
1692	dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__];
1693	dml_float_t ActiveFCLKChangeLatencyMargin[__DML_NUM_PLANES__];
1694	dml_float_t USRRetrainingLatencyMargin[__DML_NUM_PLANES__];
1695
1696	dml_bool_t SynchronizedSurfaces[__DML_NUM_PLANES__][__DML_NUM_PLANES__];
1697	dml_float_t EffectiveLBLatencyHidingY;
1698	dml_float_t EffectiveLBLatencyHidingC;
1699	dml_float_t LinesInDETY[__DML_NUM_PLANES__];
1700	dml_float_t LinesInDETC[__DML_NUM_PLANES__];
1701	dml_uint_t LinesInDETYRoundedDownToSwath[__DML_NUM_PLANES__];
1702	dml_uint_t LinesInDETCRoundedDownToSwath[__DML_NUM_PLANES__];
1703	dml_float_t FullDETBufferingTimeY;
1704	dml_float_t FullDETBufferingTimeC;
1705	dml_float_t WritebackDRAMClockChangeLatencyMargin;
1706	dml_float_t WritebackFCLKChangeLatencyMargin;
1707	dml_float_t WritebackLatencyHiding;
1708
1709	dml_uint_t TotalActiveWriteback;
1710	dml_uint_t LBLatencyHidingSourceLinesY[__DML_NUM_PLANES__];
1711	dml_uint_t LBLatencyHidingSourceLinesC[__DML_NUM_PLANES__];
1712	dml_float_t TotalPixelBW;
1713	dml_float_t EffectiveDETBufferSizeY;
1714	dml_float_t ActiveClockChangeLatencyHidingY;
1715	dml_float_t ActiveClockChangeLatencyHidingC;
1716	dml_float_t ActiveClockChangeLatencyHiding;
1717	dml_bool_t FoundCriticalSurface;
1718	dml_uint_t LastSurfaceWithoutMargin;
1719	dml_uint_t FCLKChangeSupportNumber;
1720	dml_uint_t DRAMClockChangeMethod;
1721	dml_uint_t DRAMClockChangeSupportNumber;
1722	dml_uint_t dst_y_pstate;
1723	dml_uint_t src_y_pstate_l;
1724	dml_uint_t src_y_pstate_c;
1725	dml_uint_t src_y_ahead_l;
1726	dml_uint_t src_y_ahead_c;
1727	dml_uint_t sub_vp_lines_l;
1728	dml_uint_t sub_vp_lines_c;
1729	};
1730
1731	struct CalculateVMRowAndSwath_locals_st {
1732	dml_uint_t PTEBufferSizeInRequestsForLuma[__DML_NUM_PLANES__];
1733	dml_uint_t PTEBufferSizeInRequestsForChroma[__DML_NUM_PLANES__];
1734	dml_uint_t PDEAndMetaPTEBytesFrameY;
1735	dml_uint_t PDEAndMetaPTEBytesFrameC;
1736	dml_uint_t MetaRowByteY[__DML_NUM_PLANES__];
1737	dml_uint_t MetaRowByteC[__DML_NUM_PLANES__];
1738	dml_uint_t PixelPTEBytesPerRowY[__DML_NUM_PLANES__];
1739	dml_uint_t PixelPTEBytesPerRowC[__DML_NUM_PLANES__];
1740	dml_uint_t PixelPTEBytesPerRowStorageY[__DML_NUM_PLANES__];
1741	dml_uint_t PixelPTEBytesPerRowStorageC[__DML_NUM_PLANES__];
1742	dml_uint_t PixelPTEBytesPerRowY_one_row_per_frame[__DML_NUM_PLANES__];
1743	dml_uint_t PixelPTEBytesPerRowC_one_row_per_frame[__DML_NUM_PLANES__];
1744	dml_uint_t dpte_row_width_luma_ub_one_row_per_frame[__DML_NUM_PLANES__];
1745	dml_uint_t dpte_row_height_luma_one_row_per_frame[__DML_NUM_PLANES__];
1746	dml_uint_t dpte_row_width_chroma_ub_one_row_per_frame[__DML_NUM_PLANES__];
1747	dml_uint_t dpte_row_height_chroma_one_row_per_frame[__DML_NUM_PLANES__];
1748	dml_bool_t one_row_per_frame_fits_in_buffer[__DML_NUM_PLANES__];
1749
1750	dml_uint_t HostVMDynamicLevels;
1751	};
1752
1753	struct UseMinimumDCFCLK_locals_st {
1754	dml_uint_t dummy1;
1755	dml_uint_t dummy2;
1756	dml_uint_t dummy3;
1757	dml_float_t NormalEfficiency;
1758	dml_float_t TotalMaxPrefetchFlipDPTERowBandwidth[2];
1759
1760	dml_float_t PixelDCFCLKCyclesRequiredInPrefetch[__DML_NUM_PLANES__];
1761	dml_float_t PrefetchPixelLinesTime[__DML_NUM_PLANES__];
1762	dml_float_t DCFCLKRequiredForPeakBandwidthPerSurface[__DML_NUM_PLANES__];
1763	dml_float_t DynamicMetadataVMExtraLatency[__DML_NUM_PLANES__];
1764	dml_float_t MinimumTWait;
1765	dml_float_t DPTEBandwidth;
1766	dml_float_t DCFCLKRequiredForAverageBandwidth;
1767	dml_uint_t ExtraLatencyBytes;
1768	dml_float_t ExtraLatencyCycles;
1769	dml_float_t DCFCLKRequiredForPeakBandwidth;
1770	dml_uint_t NoOfDPPState[__DML_NUM_PLANES__];
1771	dml_float_t MinimumTvmPlus2Tr0;
1772	};
1773
1774	struct CalculatePrefetchSchedule_locals_st {
1775	dml_bool_t MyError;
1776	dml_uint_t DPPCycles;
1777	dml_uint_t DISPCLKCycles;
1778	dml_float_t DSTTotalPixelsAfterScaler;
1779	dml_float_t LineTime;
1780	dml_float_t dst_y_prefetch_equ;
1781	dml_float_t prefetch_bw_oto;
1782	dml_float_t Tvm_oto;
1783	dml_float_t Tr0_oto;
1784	dml_float_t Tvm_oto_lines;
1785	dml_float_t Tr0_oto_lines;
1786	dml_float_t dst_y_prefetch_oto;
1787	dml_float_t TimeForFetchingMetaPTE;
1788	dml_float_t TimeForFetchingRowInVBlank;
1789	dml_float_t LinesToRequestPrefetchPixelData;
1790	dml_uint_t HostVMDynamicLevelsTrips;
1791	dml_float_t trip_to_mem;
1792	dml_float_t Tvm_trips;
1793	dml_float_t Tr0_trips;
1794	dml_float_t Tvm_trips_rounded;
1795	dml_float_t Tr0_trips_rounded;
1796	dml_float_t max_Tsw;
1797	dml_float_t Lsw_oto;
1798	dml_float_t Tpre_rounded;
1799	dml_float_t prefetch_bw_equ;
1800	dml_float_t Tvm_equ;
1801	dml_float_t Tr0_equ;
1802	dml_float_t Tdmbf;
1803	dml_float_t Tdmec;
1804	dml_float_t Tdmsks;
1805	dml_float_t prefetch_sw_bytes;
1806	dml_float_t prefetch_bw_pr;
1807	dml_float_t bytes_pp;
1808	dml_float_t dep_bytes;
1809	dml_float_t min_Lsw_oto;
1810	dml_float_t Tsw_est1;
1811	dml_float_t Tsw_est3;
1812	dml_float_t PrefetchBandwidth1;
1813	dml_float_t PrefetchBandwidth2;
1814	dml_float_t PrefetchBandwidth3;
1815	dml_float_t PrefetchBandwidth4;
1816	};
1817
1818	/// @brief To minimize stack usage; function locals are instead placed into this scratch structure which is allocated per context
1819	struct display_mode_lib_scratch_st {
1820	// Scratch space for function locals
1821	struct dml_core_mode_support_locals_st dml_core_mode_support_locals;
1822	struct dml_core_mode_programming_locals_st dml_core_mode_programming_locals;
1823	struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;
1824	struct CalculateVMRowAndSwath_locals_st CalculateVMRowAndSwath_locals;
1825	struct UseMinimumDCFCLK_locals_st UseMinimumDCFCLK_locals;
1826	struct CalculatePrefetchSchedule_locals_st CalculatePrefetchSchedule_locals;
1827
1828	// Scratch space for function params
1829	struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;
1830	struct CalculateVMRowAndSwath_params_st CalculateVMRowAndSwath_params;
1831	struct UseMinimumDCFCLK_params_st UseMinimumDCFCLK_params;
1832	struct CalculateSwathAndDETConfiguration_params_st CalculateSwathAndDETConfiguration_params;
1833	struct CalculateStutterEfficiency_params_st CalculateStutterEfficiency_params;
1834	struct CalculatePrefetchSchedule_params_st CalculatePrefetchSchedule_params;
1835	};
1836
1837	/// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output
1838	struct display_mode_lib_st {
1839	dml_uint_t project;
1840
1841	//@brief Mode evaluation and programming policy
1842	struct dml_mode_eval_policy_st policy;
1843
1844	//@brief IP/SOC characteristic
1845	struct ip_params_st ip;
1846	struct soc_bounding_box_st soc;
1847	struct soc_states_st states;
1848
1849	//@brief Mode Support and Mode programming struct
1850	// Used to hold input; intermediate and output of the calculations
1851	struct mode_support_st ms; // struct for mode support
1852	struct mode_program_st mp; // struct for mode programming
1853
1854	struct display_mode_lib_scratch_st scratch;
1855	};
1856
1857	struct dml_mode_support_ex_params_st {
1858	struct display_mode_lib_st *mode_lib;
1859	const struct dml_display_cfg_st *in_display_cfg;
1860	dml_uint_t out_lowest_state_idx;
1861	struct dml_mode_support_info_st *out_evaluation_info;
1862	};
1863
1864	typedef struct _vcs_dpi_dml_display_rq_regs_st dml_display_rq_regs_st;
1865	typedef struct _vcs_dpi_dml_display_dlg_regs_st dml_display_dlg_regs_st;
1866	typedef struct _vcs_dpi_dml_display_ttu_regs_st dml_display_ttu_regs_st;
1867	typedef struct _vcs_dpi_dml_display_arb_params_st dml_display_arb_params_st;
1868	typedef struct _vcs_dpi_dml_display_plane_rq_regs_st dml_display_plane_rq_regs_st;
1869
1870	struct _vcs_dpi_dml_display_dlg_regs_st {
1871	dml_uint_t refcyc_h_blank_end;
1872	dml_uint_t dlg_vblank_end;
1873	dml_uint_t min_dst_y_next_start;
1874	dml_uint_t refcyc_per_htotal;
1875	dml_uint_t refcyc_x_after_scaler;
1876	dml_uint_t dst_y_after_scaler;
1877	dml_uint_t dst_y_prefetch;
1878	dml_uint_t dst_y_per_vm_vblank;
1879	dml_uint_t dst_y_per_row_vblank;
1880	dml_uint_t dst_y_per_vm_flip;
1881	dml_uint_t dst_y_per_row_flip;
1882	dml_uint_t ref_freq_to_pix_freq;
1883	dml_uint_t vratio_prefetch;
1884	dml_uint_t vratio_prefetch_c;
1885	dml_uint_t refcyc_per_pte_group_vblank_l;
1886	dml_uint_t refcyc_per_pte_group_vblank_c;
1887	dml_uint_t refcyc_per_meta_chunk_vblank_l;
1888	dml_uint_t refcyc_per_meta_chunk_vblank_c;
1889	dml_uint_t refcyc_per_pte_group_flip_l;
1890	dml_uint_t refcyc_per_pte_group_flip_c;
1891	dml_uint_t refcyc_per_meta_chunk_flip_l;
1892	dml_uint_t refcyc_per_meta_chunk_flip_c;
1893	dml_uint_t dst_y_per_pte_row_nom_l;
1894	dml_uint_t dst_y_per_pte_row_nom_c;
1895	dml_uint_t refcyc_per_pte_group_nom_l;
1896	dml_uint_t refcyc_per_pte_group_nom_c;
1897	dml_uint_t dst_y_per_meta_row_nom_l;
1898	dml_uint_t dst_y_per_meta_row_nom_c;
1899	dml_uint_t refcyc_per_meta_chunk_nom_l;
1900	dml_uint_t refcyc_per_meta_chunk_nom_c;
1901	dml_uint_t refcyc_per_line_delivery_pre_l;
1902	dml_uint_t refcyc_per_line_delivery_pre_c;
1903	dml_uint_t refcyc_per_line_delivery_l;
1904	dml_uint_t refcyc_per_line_delivery_c;
1905	dml_uint_t refcyc_per_vm_group_vblank;
1906	dml_uint_t refcyc_per_vm_group_flip;
1907	dml_uint_t refcyc_per_vm_req_vblank;
1908	dml_uint_t refcyc_per_vm_req_flip;
1909	dml_uint_t dst_y_offset_cur0;
1910	dml_uint_t chunk_hdl_adjust_cur0;
1911	dml_uint_t dst_y_offset_cur1;
1912	dml_uint_t chunk_hdl_adjust_cur1;
1913	dml_uint_t vready_after_vcount0;
1914	dml_uint_t dst_y_delta_drq_limit;
1915	dml_uint_t refcyc_per_vm_dmdata;
1916	dml_uint_t dmdata_dl_delta;
1917	};
1918
1919	struct _vcs_dpi_dml_display_ttu_regs_st {
1920	dml_uint_t qos_level_low_wm;
1921	dml_uint_t qos_level_high_wm;
1922	dml_uint_t min_ttu_vblank;
1923	dml_uint_t qos_level_flip;
1924	dml_uint_t refcyc_per_req_delivery_l;
1925	dml_uint_t refcyc_per_req_delivery_c;
1926	dml_uint_t refcyc_per_req_delivery_cur0;
1927	dml_uint_t refcyc_per_req_delivery_cur1;
1928	dml_uint_t refcyc_per_req_delivery_pre_l;
1929	dml_uint_t refcyc_per_req_delivery_pre_c;
1930	dml_uint_t refcyc_per_req_delivery_pre_cur0;
1931	dml_uint_t refcyc_per_req_delivery_pre_cur1;
1932	dml_uint_t qos_level_fixed_l;
1933	dml_uint_t qos_level_fixed_c;
1934	dml_uint_t qos_level_fixed_cur0;
1935	dml_uint_t qos_level_fixed_cur1;
1936	dml_uint_t qos_ramp_disable_l;
1937	dml_uint_t qos_ramp_disable_c;
1938	dml_uint_t qos_ramp_disable_cur0;
1939	dml_uint_t qos_ramp_disable_cur1;
1940	};
1941
1942	struct _vcs_dpi_dml_display_arb_params_st {
1943	dml_uint_t max_req_outstanding;
1944	dml_uint_t min_req_outstanding;
1945	dml_uint_t sat_level_us;
1946	dml_uint_t hvm_max_qos_commit_threshold;
1947	dml_uint_t hvm_min_req_outstand_commit_threshold;
1948	dml_uint_t compbuf_reserved_space_kbytes;
1949	};
1950
1951	struct _vcs_dpi_dml_display_plane_rq_regs_st {
1952	dml_uint_t chunk_size;
1953	dml_uint_t min_chunk_size;
1954	dml_uint_t meta_chunk_size;
1955	dml_uint_t min_meta_chunk_size;
1956	dml_uint_t dpte_group_size;
1957	dml_uint_t mpte_group_size;
1958	dml_uint_t swath_height;
1959	dml_uint_t pte_row_height_linear;
1960	};
1961
1962	struct _vcs_dpi_dml_display_rq_regs_st {
1963	dml_display_plane_rq_regs_st rq_regs_l;
1964	dml_display_plane_rq_regs_st rq_regs_c;
1965	dml_uint_t drq_expansion_mode;
1966	dml_uint_t prq_expansion_mode;
1967	dml_uint_t mrq_expansion_mode;
1968	dml_uint_t crq_expansion_mode;
1969	dml_uint_t plane1_base_address;
1970	};
1971
1972	#endif
1973