1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright 2023 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: AMD |
24 | * |
25 | */ |
26 | |
27 | #include "display_mode_util.h" |
28 | |
29 | static dml_float_t _log(float in) |
30 | { |
31 | int * const exp_ptr = (int *)(&in); |
32 | int x = *exp_ptr; |
33 | const int log_2 = ((x >> 23) & 255) - 128; |
34 | |
35 | x &= ~(255 << 23); |
36 | x += 127 << 23; |
37 | *exp_ptr = x; |
38 | |
39 | in = ((-1.0f / 3) * in + 2) * in - 2.0f / 3; |
40 | |
41 | return (in + log_2); |
42 | } |
43 | |
44 | dml_bool_t dml_util_is_420(enum dml_source_format_class source_format) |
45 | { |
46 | dml_bool_t val = false; |
47 | |
48 | switch (source_format) { |
49 | case dml_444_16: |
50 | val = 0; |
51 | break; |
52 | case dml_444_32: |
53 | val = 0; |
54 | break; |
55 | case dml_444_64: |
56 | val = 0; |
57 | break; |
58 | case dml_420_8: |
59 | val = 1; |
60 | break; |
61 | case dml_420_10: |
62 | val = 1; |
63 | break; |
64 | case dml_422_8: |
65 | val = 0; |
66 | break; |
67 | case dml_422_10: |
68 | val = 0; |
69 | break; |
70 | default: |
71 | ASSERT(0); |
72 | break; |
73 | } |
74 | return val; |
75 | } |
76 | |
77 | static inline float dcn_bw_pow(float a, float exp) |
78 | { |
79 | float temp; |
80 | /*ASSERT(exp == (int)exp);*/ |
81 | if ((int)exp == 0) |
82 | return 1; |
83 | temp = dcn_bw_pow(a, exp: (int)(exp / 2)); |
84 | if (((int)exp % 2) == 0) { |
85 | return temp * temp; |
86 | } else { |
87 | if ((int)exp > 0) |
88 | return a * temp * temp; |
89 | else |
90 | return (temp * temp) / a; |
91 | } |
92 | } |
93 | |
94 | static inline float dcn_bw_ceil2(const float arg, const float significance) |
95 | { |
96 | ASSERT(significance != 0); |
97 | |
98 | return ((int)(arg / significance + 0.99999)) * significance; |
99 | } |
100 | |
101 | static inline float dcn_bw_floor2(const float arg, const float significance) |
102 | { |
103 | ASSERT(significance != 0); |
104 | |
105 | return ((int)(arg / significance)) * significance; |
106 | } |
107 | |
108 | dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity) |
109 | { |
110 | if (granularity == 0) |
111 | return 0; |
112 | //return (dml_float_t) (ceil(x / granularity) * granularity); |
113 | return (dml_float_t)dcn_bw_ceil2(arg: x, significance: granularity); |
114 | } |
115 | |
116 | dml_float_t dml_floor(dml_float_t x, dml_float_t granularity) |
117 | { |
118 | if (granularity == 0) |
119 | return 0; |
120 | //return (dml_float_t) (floor(x / granularity) * granularity); |
121 | return (dml_float_t)dcn_bw_floor2(arg: x, significance: granularity); |
122 | } |
123 | |
124 | dml_float_t dml_min(dml_float_t x, dml_float_t y) |
125 | { |
126 | if (x != x) |
127 | return y; |
128 | if (y != y) |
129 | return x; |
130 | if (x < y) |
131 | return x; |
132 | else |
133 | return y; |
134 | } |
135 | |
136 | dml_float_t dml_min3(dml_float_t x, dml_float_t y, dml_float_t z) |
137 | { |
138 | return dml_min(x: dml_min(x, y), y: z); |
139 | } |
140 | |
141 | dml_float_t dml_min4(dml_float_t x, dml_float_t y, dml_float_t z, dml_float_t w) |
142 | { |
143 | return dml_min(x: dml_min(x: dml_min(x, y), y: z), y: w); |
144 | } |
145 | |
146 | dml_float_t dml_max(dml_float_t x, dml_float_t y) |
147 | { |
148 | if (x != x) |
149 | return y; |
150 | if (y != y) |
151 | return x; |
152 | if (x > y) |
153 | return x; |
154 | else |
155 | return y; |
156 | } |
157 | dml_float_t dml_max3(dml_float_t x, dml_float_t y, dml_float_t z) |
158 | { |
159 | return dml_max(x: dml_max(x, y), y: z); |
160 | } |
161 | dml_float_t dml_max4(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d) |
162 | { |
163 | return dml_max(x: dml_max(x: a, y: b), y: dml_max(x: c, y: d)); |
164 | } |
165 | dml_float_t dml_max5(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d, dml_float_t e) |
166 | { |
167 | return dml_max(x: dml_max4(a, b, c, d), y: e); |
168 | } |
169 | dml_float_t dml_log(dml_float_t x, dml_float_t base) |
170 | { |
171 | return (dml_float_t) (_log(in: x) / _log(in: base)); |
172 | } |
173 | |
174 | dml_float_t dml_log2(dml_float_t x) |
175 | { |
176 | return (dml_float_t) (_log(in: x) / _log(in: 2)); |
177 | } |
178 | |
179 | dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding) |
180 | { |
181 | // if (bankers_rounding) |
182 | // return (dml_float_t) lrint(val); |
183 | // else { |
184 | // return round(val); |
185 | double round_pt = 0.5; |
186 | double ceil = dml_ceil(x: val, granularity: 1); |
187 | double floor = dml_floor(x: val, granularity: 1); |
188 | |
189 | if (val - floor >= round_pt) |
190 | return ceil; |
191 | else |
192 | return floor; |
193 | // } |
194 | } |
195 | |
196 | dml_float_t dml_pow(dml_float_t base, int exp) |
197 | { |
198 | return (dml_float_t) dcn_bw_pow(a: base, exp); |
199 | } |
200 | |
201 | dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up) |
202 | { |
203 | dml_uint_t remainder; |
204 | |
205 | if (multiple == 0) |
206 | return num; |
207 | |
208 | remainder = num % multiple; |
209 | if (remainder == 0) |
210 | return num; |
211 | |
212 | if (up) |
213 | return (num + multiple - remainder); |
214 | else |
215 | return (num - remainder); |
216 | } |
217 | |
218 | void dml_print_data_rq_regs_st(const dml_display_plane_rq_regs_st *rq_regs) |
219 | { |
220 | dml_print("DML: ===================================== \n" ); |
221 | dml_print("DML: DISPLAY_PLANE_RQ_REGS_ST\n" ); |
222 | dml_print("DML: chunk_size = 0x%x\n" , rq_regs->chunk_size); |
223 | dml_print("DML: min_chunk_size = 0x%x\n" , rq_regs->min_chunk_size); |
224 | dml_print("DML: meta_chunk_size = 0x%x\n" , rq_regs->meta_chunk_size); |
225 | dml_print("DML: min_meta_chunk_size = 0x%x\n" , rq_regs->min_meta_chunk_size); |
226 | dml_print("DML: dpte_group_size = 0x%x\n" , rq_regs->dpte_group_size); |
227 | dml_print("DML: mpte_group_size = 0x%x\n" , rq_regs->mpte_group_size); |
228 | dml_print("DML: swath_height = 0x%x\n" , rq_regs->swath_height); |
229 | dml_print("DML: pte_row_height_linear = 0x%x\n" , rq_regs->pte_row_height_linear); |
230 | dml_print("DML: ===================================== \n" ); |
231 | } |
232 | |
233 | void dml_print_rq_regs_st(const dml_display_rq_regs_st *rq_regs) |
234 | { |
235 | dml_print("DML: ===================================== \n" ); |
236 | dml_print("DML: DISPLAY_RQ_REGS_ST\n" ); |
237 | dml_print("DML: <LUMA> \n" ); |
238 | dml_print_data_rq_regs_st(rq_regs: &rq_regs->rq_regs_l); |
239 | dml_print("DML: <CHROMA> \n" ); |
240 | dml_print_data_rq_regs_st(rq_regs: &rq_regs->rq_regs_c); |
241 | dml_print("DML: drq_expansion_mode = 0x%x\n" , rq_regs->drq_expansion_mode); |
242 | dml_print("DML: prq_expansion_mode = 0x%x\n" , rq_regs->prq_expansion_mode); |
243 | dml_print("DML: mrq_expansion_mode = 0x%x\n" , rq_regs->mrq_expansion_mode); |
244 | dml_print("DML: crq_expansion_mode = 0x%x\n" , rq_regs->crq_expansion_mode); |
245 | dml_print("DML: plane1_base_address = 0x%x\n" , rq_regs->plane1_base_address); |
246 | dml_print("DML: ===================================== \n" ); |
247 | } |
248 | |
249 | void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs) |
250 | { |
251 | dml_print("DML: ===================================== \n" ); |
252 | dml_print("DML: DISPLAY_DLG_REGS_ST \n" ); |
253 | dml_print("DML: refcyc_h_blank_end = 0x%x\n" , dlg_regs->refcyc_h_blank_end); |
254 | dml_print("DML: dlg_vblank_end = 0x%x\n" , dlg_regs->dlg_vblank_end); |
255 | dml_print("DML: min_dst_y_next_start = 0x%x\n" , dlg_regs->min_dst_y_next_start); |
256 | dml_print("DML: refcyc_per_htotal = 0x%x\n" , dlg_regs->refcyc_per_htotal); |
257 | dml_print("DML: refcyc_x_after_scaler = 0x%x\n" , dlg_regs->refcyc_x_after_scaler); |
258 | dml_print("DML: dst_y_after_scaler = 0x%x\n" , dlg_regs->dst_y_after_scaler); |
259 | dml_print("DML: dst_y_prefetch = 0x%x\n" , dlg_regs->dst_y_prefetch); |
260 | dml_print("DML: dst_y_per_vm_vblank = 0x%x\n" , dlg_regs->dst_y_per_vm_vblank); |
261 | dml_print("DML: dst_y_per_row_vblank = 0x%x\n" , dlg_regs->dst_y_per_row_vblank); |
262 | dml_print("DML: dst_y_per_vm_flip = 0x%x\n" , dlg_regs->dst_y_per_vm_flip); |
263 | dml_print("DML: dst_y_per_row_flip = 0x%x\n" , dlg_regs->dst_y_per_row_flip); |
264 | dml_print("DML: ref_freq_to_pix_freq = 0x%x\n" , dlg_regs->ref_freq_to_pix_freq); |
265 | dml_print("DML: vratio_prefetch = 0x%x\n" , dlg_regs->vratio_prefetch); |
266 | dml_print("DML: vratio_prefetch_c = 0x%x\n" , dlg_regs->vratio_prefetch_c); |
267 | dml_print("DML: refcyc_per_pte_group_vblank_l = 0x%x\n" , dlg_regs->refcyc_per_pte_group_vblank_l); |
268 | dml_print("DML: refcyc_per_pte_group_vblank_c = 0x%x\n" , dlg_regs->refcyc_per_pte_group_vblank_c); |
269 | dml_print("DML: refcyc_per_meta_chunk_vblank_l = 0x%x\n" , dlg_regs->refcyc_per_meta_chunk_vblank_l); |
270 | dml_print("DML: refcyc_per_meta_chunk_vblank_c = 0x%x\n" , dlg_regs->refcyc_per_meta_chunk_vblank_c); |
271 | dml_print("DML: refcyc_per_pte_group_flip_l = 0x%x\n" , dlg_regs->refcyc_per_pte_group_flip_l); |
272 | dml_print("DML: refcyc_per_pte_group_flip_c = 0x%x\n" , dlg_regs->refcyc_per_pte_group_flip_c); |
273 | dml_print("DML: refcyc_per_meta_chunk_flip_l = 0x%x\n" , dlg_regs->refcyc_per_meta_chunk_flip_l); |
274 | dml_print("DML: refcyc_per_meta_chunk_flip_c = 0x%x\n" , dlg_regs->refcyc_per_meta_chunk_flip_c); |
275 | dml_print("DML: dst_y_per_pte_row_nom_l = 0x%x\n" , dlg_regs->dst_y_per_pte_row_nom_l); |
276 | dml_print("DML: dst_y_per_pte_row_nom_c = 0x%x\n" , dlg_regs->dst_y_per_pte_row_nom_c); |
277 | dml_print("DML: refcyc_per_pte_group_nom_l = 0x%x\n" , dlg_regs->refcyc_per_pte_group_nom_l); |
278 | dml_print("DML: refcyc_per_pte_group_nom_c = 0x%x\n" , dlg_regs->refcyc_per_pte_group_nom_c); |
279 | dml_print("DML: dst_y_per_meta_row_nom_l = 0x%x\n" , dlg_regs->dst_y_per_meta_row_nom_l); |
280 | dml_print("DML: dst_y_per_meta_row_nom_c = 0x%x\n" , dlg_regs->dst_y_per_meta_row_nom_c); |
281 | dml_print("DML: refcyc_per_meta_chunk_nom_l = 0x%x\n" , dlg_regs->refcyc_per_meta_chunk_nom_l); |
282 | dml_print("DML: refcyc_per_meta_chunk_nom_c = 0x%x\n" , dlg_regs->refcyc_per_meta_chunk_nom_c); |
283 | dml_print("DML: refcyc_per_line_delivery_pre_l = 0x%x\n" , dlg_regs->refcyc_per_line_delivery_pre_l); |
284 | dml_print("DML: refcyc_per_line_delivery_pre_c = 0x%x\n" , dlg_regs->refcyc_per_line_delivery_pre_c); |
285 | dml_print("DML: refcyc_per_line_delivery_l = 0x%x\n" , dlg_regs->refcyc_per_line_delivery_l); |
286 | dml_print("DML: refcyc_per_line_delivery_c = 0x%x\n" , dlg_regs->refcyc_per_line_delivery_c); |
287 | dml_print("DML: refcyc_per_vm_group_vblank = 0x%x\n" , dlg_regs->refcyc_per_vm_group_vblank); |
288 | dml_print("DML: refcyc_per_vm_group_flip = 0x%x\n" , dlg_regs->refcyc_per_vm_group_flip); |
289 | dml_print("DML: refcyc_per_vm_req_vblank = 0x%x\n" , dlg_regs->refcyc_per_vm_req_vblank); |
290 | dml_print("DML: refcyc_per_vm_req_flip = 0x%x\n" , dlg_regs->refcyc_per_vm_req_flip); |
291 | dml_print("DML: chunk_hdl_adjust_cur0 = 0x%x\n" , dlg_regs->chunk_hdl_adjust_cur0); |
292 | dml_print("DML: dst_y_offset_cur1 = 0x%x\n" , dlg_regs->dst_y_offset_cur1); |
293 | dml_print("DML: chunk_hdl_adjust_cur1 = 0x%x\n" , dlg_regs->chunk_hdl_adjust_cur1); |
294 | dml_print("DML: vready_after_vcount0 = 0x%x\n" , dlg_regs->vready_after_vcount0); |
295 | dml_print("DML: dst_y_delta_drq_limit = 0x%x\n" , dlg_regs->dst_y_delta_drq_limit); |
296 | dml_print("DML: refcyc_per_vm_dmdata = 0x%x\n" , dlg_regs->refcyc_per_vm_dmdata); |
297 | dml_print("DML: ===================================== \n" ); |
298 | } |
299 | |
300 | void dml_print_ttu_regs_st(const dml_display_ttu_regs_st *ttu_regs) |
301 | { |
302 | dml_print("DML: ===================================== \n" ); |
303 | dml_print("DML: DISPLAY_TTU_REGS_ST \n" ); |
304 | dml_print("DML: qos_level_low_wm = 0x%x\n" , ttu_regs->qos_level_low_wm); |
305 | dml_print("DML: qos_level_high_wm = 0x%x\n" , ttu_regs->qos_level_high_wm); |
306 | dml_print("DML: min_ttu_vblank = 0x%x\n" , ttu_regs->min_ttu_vblank); |
307 | dml_print("DML: qos_level_flip = 0x%x\n" , ttu_regs->qos_level_flip); |
308 | dml_print("DML: refcyc_per_req_delivery_pre_l = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_pre_l); |
309 | dml_print("DML: refcyc_per_req_delivery_l = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_l); |
310 | dml_print("DML: refcyc_per_req_delivery_pre_c = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_pre_c); |
311 | dml_print("DML: refcyc_per_req_delivery_c = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_c); |
312 | dml_print("DML: refcyc_per_req_delivery_cur0 = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_cur0); |
313 | dml_print("DML: refcyc_per_req_delivery_pre_cur0 = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_pre_cur0); |
314 | dml_print("DML: refcyc_per_req_delivery_cur1 = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_cur1); |
315 | dml_print("DML: refcyc_per_req_delivery_pre_cur1 = 0x%x\n" , ttu_regs->refcyc_per_req_delivery_pre_cur1); |
316 | dml_print("DML: qos_level_fixed_l = 0x%x\n" , ttu_regs->qos_level_fixed_l); |
317 | dml_print("DML: qos_ramp_disable_l = 0x%x\n" , ttu_regs->qos_ramp_disable_l); |
318 | dml_print("DML: qos_level_fixed_c = 0x%x\n" , ttu_regs->qos_level_fixed_c); |
319 | dml_print("DML: qos_ramp_disable_c = 0x%x\n" , ttu_regs->qos_ramp_disable_c); |
320 | dml_print("DML: qos_level_fixed_cur0 = 0x%x\n" , ttu_regs->qos_level_fixed_cur0); |
321 | dml_print("DML: qos_ramp_disable_cur0 = 0x%x\n" , ttu_regs->qos_ramp_disable_cur0); |
322 | dml_print("DML: qos_level_fixed_cur1 = 0x%x\n" , ttu_regs->qos_level_fixed_cur1); |
323 | dml_print("DML: qos_ramp_disable_cur1 = 0x%x\n" , ttu_regs->qos_ramp_disable_cur1); |
324 | dml_print("DML: ===================================== \n" ); |
325 | } |
326 | |
327 | void dml_print_dml_policy(const struct dml_mode_eval_policy_st *policy) |
328 | { |
329 | dml_print("DML: ===================================== \n" ); |
330 | dml_print("DML: DML_MODE_EVAL_POLICY_ST\n" ); |
331 | dml_print("DML: Policy: UseUnboundedRequesting = 0x%x\n" , policy->UseUnboundedRequesting); |
332 | dml_print("DML: Policy: UseMinimumRequiredDCFCLK = 0x%x\n" , policy->UseMinimumRequiredDCFCLK); |
333 | dml_print("DML: Policy: DRAMClockChangeRequirementFinal = 0x%x\n" , policy->DRAMClockChangeRequirementFinal); |
334 | dml_print("DML: Policy: FCLKChangeRequirementFinal = 0x%x\n" , policy->FCLKChangeRequirementFinal); |
335 | dml_print("DML: Policy: USRRetrainingRequiredFinal = 0x%x\n" , policy->USRRetrainingRequiredFinal); |
336 | dml_print("DML: Policy: EnhancedPrefetchScheduleAccelerationFinal = 0x%x\n" , policy->EnhancedPrefetchScheduleAccelerationFinal); |
337 | dml_print("DML: Policy: NomDETInKByteOverrideEnable = 0x%x\n" , policy->NomDETInKByteOverrideEnable); |
338 | dml_print("DML: Policy: NomDETInKByteOverrideValue = 0x%x\n" , policy->NomDETInKByteOverrideValue); |
339 | dml_print("DML: Policy: DCCProgrammingAssumesScanDirectionUnknownFinal = 0x%x\n" , policy->DCCProgrammingAssumesScanDirectionUnknownFinal); |
340 | dml_print("DML: Policy: SynchronizeTimingsFinal = 0x%x\n" , policy->SynchronizeTimingsFinal); |
341 | dml_print("DML: Policy: SynchronizeDRRDisplaysForUCLKPStateChangeFinal = 0x%x\n" , policy->SynchronizeDRRDisplaysForUCLKPStateChangeFinal); |
342 | dml_print("DML: Policy: AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported = 0x%x\n" , policy->AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported); |
343 | dml_print("DML: Policy: AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported = 0x%x\n" , policy->AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported); |
344 | |
345 | for (dml_uint_t i = 0; i < DCN_DML__NUM_PLANE; i++) { |
346 | dml_print("DML: i=%0d, Policy: MPCCombineUse = 0x%x\n" , i, policy->MPCCombineUse[i]); |
347 | dml_print("DML: i=%0d, Policy: ODMUse = 0x%x\n" , i, policy->ODMUse[i]); |
348 | dml_print("DML: i=%0d, Policy: ImmediateFlipRequirement = 0x%x\n" , i, policy->ImmediateFlipRequirement[i]); |
349 | dml_print("DML: i=%0d, Policy: AllowForPStateChangeOrStutterInVBlank = 0x%x\n" , i, policy->AllowForPStateChangeOrStutterInVBlank[i]); |
350 | } |
351 | dml_print("DML: ===================================== \n" ); |
352 | } |
353 | |
354 | void dml_print_mode_support(struct display_mode_lib_st *mode_lib, dml_uint_t j) |
355 | { |
356 | dml_print("DML: MODE SUPPORT: ===============================================\n" ); |
357 | dml_print("DML: MODE SUPPORT: Voltage State %d\n" , j); |
358 | dml_print("DML: MODE SUPPORT: Mode Supported : %s\n" , mode_lib->ms.support.ModeSupport[j] == true ? "Supported" : "NOT Supported" ); |
359 | dml_print("DML: MODE SUPPORT: Scale Ratio And Taps : %s\n" , mode_lib->ms.support.ScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported" ); |
360 | dml_print("DML: MODE SUPPORT: Source Format Pixel And Scan : %s\n" , mode_lib->ms.support.SourceFormatPixelAndScanSupport == true ? "Supported" : "NOT Supported" ); |
361 | dml_print("DML: MODE SUPPORT: Viewport Size : %s\n" , mode_lib->ms.support.ViewportSizeSupport[j] == true ? "Supported" : "NOT Supported" ); |
362 | dml_print("DML: MODE SUPPORT: Link Rate Does Not Match DP Version : %s\n" , mode_lib->ms.support.LinkRateDoesNotMatchDPVersion == false ? "Supported" : "NOT Supported" ); |
363 | dml_print("DML: MODE SUPPORT: Link Rate For Multistream Not Indicated : %s\n" , mode_lib->ms.support.LinkRateForMultistreamNotIndicated == false ? "Supported" : "NOT Supported" ); |
364 | dml_print("DML: MODE SUPPORT: BPP For Multi stream Not Indicated : %s\n" , mode_lib->ms.support.BPPForMultistreamNotIndicated == false ? "Supported" : "NOT Supported" ); |
365 | dml_print("DML: MODE SUPPORT: Multistream With HDMI Or eDP : %s\n" , mode_lib->ms.support.MultistreamWithHDMIOreDP == false ? "Supported" : "NOT Supported" ); |
366 | dml_print("DML: MODE SUPPORT: Exceeded Multistream Slots : %s\n" , mode_lib->ms.support.ExceededMultistreamSlots == false ? "Supported" : "NOT Supported" ); |
367 | dml_print("DML: MODE SUPPORT: MSO Or ODM Split With Non DP Link : %s\n" , mode_lib->ms.support.MSOOrODMSplitWithNonDPLink == false ? "Supported" : "NOT Supported" ); |
368 | dml_print("DML: MODE SUPPORT: Not Enough Lanes For MSO : %s\n" , mode_lib->ms.support.NotEnoughLanesForMSO == false ? "Supported" : "NOT Supported" ); |
369 | dml_print("DML: MODE SUPPORT: LinkCapacitySupport : %s\n" , mode_lib->ms.support.LinkCapacitySupport == true ? "Supported" : "NOT Supported" ); |
370 | dml_print("DML: MODE SUPPORT: P2IWith420 : %s\n" , mode_lib->ms.support.P2IWith420 == false ? "Supported" : "NOT Supported" ); |
371 | dml_print("DML: MODE SUPPORT: DSCOnlyIfNecessaryWithBPP : %s\n" , mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP == false ? "Supported" : "NOT Supported" ); |
372 | dml_print("DML: MODE SUPPORT: DSC422NativeNotSupported : %s\n" , mode_lib->ms.support.DSC422NativeNotSupported == false ? "Supported" : "NOT Supported" ); |
373 | dml_print("DML: MODE SUPPORT: MPCCombineMethodIncompatible : %s\n" , mode_lib->ms.support.MPCCombineMethodIncompatible == false ? "Supported" : "NOT Supported" ); |
374 | dml_print("DML: MODE SUPPORT: ODMCombineTwoToOneSupportCheckOK : %s\n" , mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK == true ? "Supported" : "NOT Supported" ); |
375 | dml_print("DML: MODE SUPPORT: ODMCombineFourToOneSupportCheckOK : %s\n" , mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK == true ? "Supported" : "NOT Supported" ); |
376 | dml_print("DML: MODE SUPPORT: NotEnoughDSCUnits : %s\n" , mode_lib->ms.support.NotEnoughDSCUnits == false ? "Supported" : "NOT Supported" ); |
377 | dml_print("DML: MODE SUPPORT: NotEnoughDSCSlices : %s\n" , mode_lib->ms.support.NotEnoughDSCSlices == false ? "Supported" : "NOT Supported" ); |
378 | dml_print("DML: MODE SUPPORT: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe : %s\n" , mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == false ? "Supported" : "NOT Supported" ); |
379 | dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPStateAndStaticScreen : %s\n" , mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen == false ? "Supported" : "NOT Supported" ); |
380 | dml_print("DML: MODE SUPPORT: DSCCLKRequiredMoreThanSupported : %s\n" , mode_lib->ms.support.DSCCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported" ); |
381 | dml_print("DML: MODE SUPPORT: PixelsPerLinePerDSCUnitSupport : %s\n" , mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport == true ? "Supported" : "NOT Supported" ); |
382 | dml_print("DML: MODE SUPPORT: DTBCLKRequiredMoreThanSupported : %s\n" , mode_lib->ms.support.DTBCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported" ); |
383 | dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPState : %s\n" , mode_lib->ms.support.InvalidCombinationOfMALLUseForPState == false ? "Supported" : "NOT Supported" ); |
384 | dml_print("DML: MODE SUPPORT: ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified : %s\n" , mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified == false ? "Supported" : "NOT Supported" ); |
385 | dml_print("DML: MODE SUPPORT: ROB Support : %s\n" , mode_lib->ms.support.ROBSupport[j] == true ? "Supported" : "NOT Supported" ); |
386 | dml_print("DML: MODE SUPPORT: DISPCLK DPPCLK Support : %s\n" , mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] == true ? "Supported" : "NOT Supported" ); |
387 | dml_print("DML: MODE SUPPORT: Total Available Pipes Support : %s\n" , mode_lib->ms.support.TotalAvailablePipesSupport[j] == true ? "Supported" : "NOT Supported" ); |
388 | dml_print("DML: MODE SUPPORT: Number Of OTG Support : %s\n" , mode_lib->ms.support.NumberOfOTGSupport == true ? "Supported" : "NOT Supported" ); |
389 | dml_print("DML: MODE SUPPORT: Number Of DP2p0 Support : %s\n" , mode_lib->ms.support.NumberOfDP2p0Support == true ? "Supported" : "NOT Supported" ); |
390 | dml_print("DML: MODE SUPPORT: Writeback Latency Support : %s\n" , mode_lib->ms.support.WritebackLatencySupport == true ? "Supported" : "NOT Supported" ); |
391 | dml_print("DML: MODE SUPPORT: Writeback Scale Ratio And Taps Support : %s\n" , mode_lib->ms.support.WritebackScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported" ); |
392 | dml_print("DML: MODE SUPPORT: Cursor Support : %s\n" , mode_lib->ms.support.CursorSupport == true ? "Supported" : "NOT Supported" ); |
393 | dml_print("DML: MODE SUPPORT: Pitch Support : %s\n" , mode_lib->ms.support.PitchSupport == true ? "Supported" : "NOT Supported" ); |
394 | dml_print("DML: MODE SUPPORT: Viewport Exceeds Surface : %s\n" , mode_lib->ms.support.ViewportExceedsSurface == false ? "Supported" : "NOT Supported" ); |
395 | dml_print("DML: MODE SUPPORT: Prefetch Supported : %s\n" , mode_lib->ms.support.PrefetchSupported[j] == true ? "Supported" : "NOT Supported" ); |
396 | dml_print("DML: MODE SUPPORT: VActive Bandwith Support : %s\n" , mode_lib->ms.support.VActiveBandwithSupport[j] == true ? "Supported" : "NOT Supported" ); |
397 | dml_print("DML: MODE SUPPORT: Dynamic Metadata Supported : %s\n" , mode_lib->ms.support.DynamicMetadataSupported[j] == true ? "Supported" : "NOT Supported" ); |
398 | dml_print("DML: MODE SUPPORT: Total Vertical Active Bandwidth Support : %s\n" , mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] == true ? "Supported" : "NOT Supported" ); |
399 | dml_print("DML: MODE SUPPORT: VRatio In Prefetch Supported : %s\n" , mode_lib->ms.support.VRatioInPrefetchSupported[j] == true ? "Supported" : "NOT Supported" ); |
400 | dml_print("DML: MODE SUPPORT: PTE Buffer Size Not Exceeded : %s\n" , mode_lib->ms.support.PTEBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported" ); |
401 | dml_print("DML: MODE SUPPORT: DCC Meta Buffer Size Not Exceeded : %s\n" , mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported" ); |
402 | dml_print("DML: MODE SUPPORT: Non supported DSC Input BPC : %s\n" , mode_lib->ms.support.NonsupportedDSCInputBPC == false ? "Supported" : "NOT Supported" ); |
403 | dml_print("DML: MODE SUPPORT: Exceeded MALL Size : %s\n" , mode_lib->ms.support.ExceededMALLSize == false ? "Supported" : "NOT Supported" ); |
404 | dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n" , ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported" ); |
405 | dml_print("DML: MODE SUPPORT: dram clock change support : %s\n" , mode_lib->scratch.dml_core_mode_support_locals.dram_clock_change_support == true ? "Supported" : "NOT Supported" ); |
406 | dml_print("DML: MODE SUPPORT: f_clock change support : %s\n" , mode_lib->scratch.dml_core_mode_support_locals.f_clock_change_support == true ? "Supported" : "NOT Supported" ); |
407 | dml_print("DML: MODE SUPPORT: USR Retraining Support : %s\n" , (!mode_lib->ms.policy.USRRetrainingRequiredFinal || &mode_lib->ms.support.USRRetrainingSupport[j]) ? "Supported" : "NOT Supported" ); |
408 | dml_print("DML: MODE SUPPORT: ===============================================\n" ); |
409 | } |
410 | |
411 | void dml_print_dml_mode_support_info(const struct dml_mode_support_info_st *support, dml_bool_t fail_only) |
412 | { |
413 | dml_print("DML: ===================================== \n" ); |
414 | dml_print("DML: DML_MODE_SUPPORT_INFO_ST\n" ); |
415 | if (!fail_only || support->ModeIsSupported == 0) |
416 | dml_print("DML: support: ModeIsSupported = 0x%x\n" , support->ModeIsSupported); |
417 | if (!fail_only || support->ImmediateFlipSupport == 0) |
418 | dml_print("DML: support: ImmediateFlipSupport = 0x%x\n" , support->ImmediateFlipSupport); |
419 | if (!fail_only || support->WritebackLatencySupport == 0) |
420 | dml_print("DML: support: WritebackLatencySupport = 0x%x\n" , support->WritebackLatencySupport); |
421 | if (!fail_only || support->ScaleRatioAndTapsSupport == 0) |
422 | dml_print("DML: support: ScaleRatioAndTapsSupport = 0x%x\n" , support->ScaleRatioAndTapsSupport); |
423 | if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) |
424 | dml_print("DML: support: SourceFormatPixelAndScanSupport = 0x%x\n" , support->SourceFormatPixelAndScanSupport); |
425 | if (!fail_only || support->MPCCombineMethodIncompatible == 1) |
426 | dml_print("DML: support: MPCCombineMethodIncompatible = 0x%x\n" , support->MPCCombineMethodIncompatible); |
427 | if (!fail_only || support->P2IWith420 == 1) |
428 | dml_print("DML: support: P2IWith420 = 0x%x\n" , support->P2IWith420); |
429 | if (!fail_only || support->DSCOnlyIfNecessaryWithBPP == 1) |
430 | dml_print("DML: support: DSCOnlyIfNecessaryWithBPP = 0x%x\n" , support->DSCOnlyIfNecessaryWithBPP); |
431 | if (!fail_only || support->DSC422NativeNotSupported == 1) |
432 | dml_print("DML: support: DSC422NativeNotSupported = 0x%x\n" , support->DSC422NativeNotSupported); |
433 | if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) |
434 | dml_print("DML: support: LinkRateDoesNotMatchDPVersion = 0x%x\n" , support->LinkRateDoesNotMatchDPVersion); |
435 | if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1) |
436 | dml_print("DML: support: LinkRateForMultistreamNotIndicated = 0x%x\n" , support->LinkRateForMultistreamNotIndicated); |
437 | if (!fail_only || support->BPPForMultistreamNotIndicated == 1) |
438 | dml_print("DML: support: BPPForMultistreamNotIndicated = 0x%x\n" , support->BPPForMultistreamNotIndicated); |
439 | if (!fail_only || support->MultistreamWithHDMIOreDP == 1) |
440 | dml_print("DML: support: MultistreamWithHDMIOreDP = 0x%x\n" , support->MultistreamWithHDMIOreDP); |
441 | if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1) |
442 | dml_print("DML: support: MSOOrODMSplitWithNonDPLink = 0x%x\n" , support->MSOOrODMSplitWithNonDPLink); |
443 | if (!fail_only || support->NotEnoughLanesForMSO == 1) |
444 | dml_print("DML: support: NotEnoughLanesForMSO = 0x%x\n" , support->NotEnoughLanesForMSO); |
445 | if (!fail_only || support->NumberOfOTGSupport == 0) |
446 | dml_print("DML: support: NumberOfOTGSupport = 0x%x\n" , support->NumberOfOTGSupport); |
447 | if (!fail_only || support->NumberOfDP2p0Support == 0) |
448 | dml_print("DML: support: NumberOfDP2p0Support = 0x%x\n" , support->NumberOfDP2p0Support); |
449 | if (!fail_only || support->NonsupportedDSCInputBPC == 1) |
450 | dml_print("DML: support: NonsupportedDSCInputBPC = 0x%x\n" , support->NonsupportedDSCInputBPC); |
451 | if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0) |
452 | dml_print("DML: support: WritebackScaleRatioAndTapsSupport = 0x%x\n" , support->WritebackScaleRatioAndTapsSupport); |
453 | if (!fail_only || support->CursorSupport == 0) |
454 | dml_print("DML: support: CursorSupport = 0x%x\n" , support->CursorSupport); |
455 | if (!fail_only || support->PitchSupport == 0) |
456 | dml_print("DML: support: PitchSupport = 0x%x\n" , support->PitchSupport); |
457 | if (!fail_only || support->ViewportExceedsSurface == 1) |
458 | dml_print("DML: support: ViewportExceedsSurface = 0x%x\n" , support->ViewportExceedsSurface); |
459 | if (!fail_only || support->ExceededMALLSize == 1) |
460 | dml_print("DML: support: ExceededMALLSize = 0x%x\n" , support->ExceededMALLSize); |
461 | if (!fail_only || support->EnoughWritebackUnits == 0) |
462 | dml_print("DML: support: EnoughWritebackUnits = 0x%x\n" , support->EnoughWritebackUnits); |
463 | if (!fail_only || support->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified == 1) |
464 | dml_print("DML: support: ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = 0x%x\n" , support->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified); |
465 | if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1) |
466 | dml_print("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = 0x%x\n" , support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe); |
467 | if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1) |
468 | dml_print("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = 0x%x\n" , support->InvalidCombinationOfMALLUseForPStateAndStaticScreen); |
469 | if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1) |
470 | dml_print("DML: support: InvalidCombinationOfMALLUseForPState = 0x%x\n" , support->InvalidCombinationOfMALLUseForPState); |
471 | |
472 | if (!fail_only || support->ExceededMultistreamSlots == 1) |
473 | dml_print("DML: support: ExceededMultistreamSlots = 0x%x\n" , support->ExceededMultistreamSlots); |
474 | if (!fail_only || support->ODMCombineTwoToOneSupportCheckOK == 0) |
475 | dml_print("DML: support: ODMCombineTwoToOneSupportCheckOK = 0x%x\n" , support->ODMCombineTwoToOneSupportCheckOK); |
476 | if (!fail_only || support->ODMCombineFourToOneSupportCheckOK == 0) |
477 | dml_print("DML: support: ODMCombineFourToOneSupportCheckOK = 0x%x\n" , support->ODMCombineFourToOneSupportCheckOK); |
478 | if (!fail_only || support->NotEnoughDSCUnits == 1) |
479 | dml_print("DML: support: NotEnoughDSCUnits = 0x%x\n" , support->NotEnoughDSCUnits); |
480 | if (!fail_only || support->NotEnoughDSCSlices == 1) |
481 | dml_print("DML: support: NotEnoughDSCSlices = 0x%x\n" , support->NotEnoughDSCSlices); |
482 | if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0) |
483 | dml_print("DML: support: PixelsPerLinePerDSCUnitSupport = 0x%x\n" , support->PixelsPerLinePerDSCUnitSupport); |
484 | if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1) |
485 | dml_print("DML: support: DSCCLKRequiredMoreThanSupported = 0x%x\n" , support->DSCCLKRequiredMoreThanSupported); |
486 | if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1) |
487 | dml_print("DML: support: DTBCLKRequiredMoreThanSupported = 0x%x\n" , support->DTBCLKRequiredMoreThanSupported); |
488 | if (!fail_only || support->LinkCapacitySupport == 0) |
489 | dml_print("DML: support: LinkCapacitySupport = 0x%x\n" , support->LinkCapacitySupport); |
490 | |
491 | for (dml_uint_t j = 0; j < 2; j++) { |
492 | if (!fail_only || support->DRAMClockChangeSupport[j] == dml_dram_clock_change_unsupported) |
493 | dml_print("DML: support: combine=%d, DRAMClockChangeSupport = %d\n" , j, support->DRAMClockChangeSupport[j]); |
494 | if (!fail_only || support->FCLKChangeSupport[j] == dml_fclock_change_unsupported) |
495 | dml_print("DML: support: combine=%d, FCLKChangeSupport = %d\n" , j, support->FCLKChangeSupport[j]); |
496 | if (!fail_only || support->ROBSupport[j] == 0) |
497 | dml_print("DML: support: combine=%d, ROBSupport = %d\n" , j, support->ROBSupport[j]); |
498 | if (!fail_only || support->PTEBufferSizeNotExceeded[j] == 0) |
499 | dml_print("DML: support: combine=%d, PTEBufferSizeNotExceeded = %d\n" , j, support->PTEBufferSizeNotExceeded[j]); |
500 | if (!fail_only || support->DCCMetaBufferSizeNotExceeded[j] == 0) |
501 | dml_print("DML: support: combine=%d, DCCMetaBufferSizeNotExceeded = %d\n" , j, support->DCCMetaBufferSizeNotExceeded[j]); |
502 | if (!fail_only || support->TotalVerticalActiveBandwidthSupport[j] == 0) |
503 | dml_print("DML: support: combine=%d, TotalVerticalActiveBandwidthSupport = %d\n" , j, support->TotalVerticalActiveBandwidthSupport[j]); |
504 | if (!fail_only || support->USRRetrainingSupport[j] == 0) |
505 | dml_print("DML: support: combine=%d, USRRetrainingSupport = %d\n" , j, support->USRRetrainingSupport[j]); |
506 | if (!fail_only || support->VActiveBandwithSupport[j] == 0) |
507 | dml_print("DML: support: combine=%d, VActiveBandwithSupport = %d\n" , j, support->VActiveBandwithSupport[j]); |
508 | if (!fail_only || support->PrefetchSupported[j] == 0) |
509 | dml_print("DML: support: combine=%d, PrefetchSupported = %d\n" , j, support->PrefetchSupported[j]); |
510 | if (!fail_only || support->DynamicMetadataSupported[j] == 0) |
511 | dml_print("DML: support: combine=%d, DynamicMetadataSupported = %d\n" , j, support->DynamicMetadataSupported[j]); |
512 | if (!fail_only || support->VRatioInPrefetchSupported[j] == 0) |
513 | dml_print("DML: support: combine=%d, VRatioInPrefetchSupported = %d\n" , j, support->VRatioInPrefetchSupported[j]); |
514 | if (!fail_only || support->DISPCLK_DPPCLK_Support[j] == 0) |
515 | dml_print("DML: support: combine=%d, DISPCLK_DPPCLK_Support = %d\n" , j, support->DISPCLK_DPPCLK_Support[j]); |
516 | if (!fail_only || support->TotalAvailablePipesSupport[j] == 0) |
517 | dml_print("DML: support: combine=%d, TotalAvailablePipesSupport = %d\n" , j, support->TotalAvailablePipesSupport[j]); |
518 | if (!fail_only || support->ModeSupport[j] == 0) |
519 | dml_print("DML: support: combine=%d, ModeSupport = %d\n" , j, support->ModeSupport[j]); |
520 | if (!fail_only || support->ViewportSizeSupport[j] == 0) |
521 | dml_print("DML: support: combine=%d, ViewportSizeSupport = %d\n" , j, support->ViewportSizeSupport[j]); |
522 | if (!fail_only || support->ImmediateFlipSupportedForState[j] == 0) |
523 | dml_print("DML: support: combine=%d, ImmediateFlipSupportedForState = %d\n" , j, support->ImmediateFlipSupportedForState[j]); |
524 | } |
525 | } |
526 | |
527 | void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane) |
528 | { |
529 | for (dml_uint_t i = 0; i < num_plane; i++) { |
530 | dml_print("DML: timing_cfg: plane=%d, HTotal = %d\n" , i, timing->HTotal[i]); |
531 | dml_print("DML: timing_cfg: plane=%d, VTotal = %d\n" , i, timing->VTotal[i]); |
532 | dml_print("DML: timing_cfg: plane=%d, HActive = %d\n" , i, timing->HActive[i]); |
533 | dml_print("DML: timing_cfg: plane=%d, VActive = %d\n" , i, timing->VActive[i]); |
534 | dml_print("DML: timing_cfg: plane=%d, VFrontPorch = %d\n" , i, timing->VFrontPorch[i]); |
535 | dml_print("DML: timing_cfg: plane=%d, VBlankNom = %d\n" , i, timing->VBlankNom[i]); |
536 | dml_print("DML: timing_cfg: plane=%d, RefreshRate = %d\n" , i, timing->RefreshRate[i]); |
537 | dml_print("DML: timing_cfg: plane=%d, PixelClock = %f\n" , i, timing->PixelClock[i]); |
538 | dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n" , i, timing->Interlace[i]); |
539 | dml_print("DML: timing_cfg: plane=%d, DRRDisplay = %d\n" , i, timing->DRRDisplay[i]); |
540 | } |
541 | } |
542 | |
543 | void dml_print_dml_display_cfg_plane(const struct dml_plane_cfg_st *plane, dml_uint_t num_plane) |
544 | { |
545 | dml_print("DML: plane_cfg: num_plane = %d\n" , num_plane); |
546 | dml_print("DML: plane_cfg: GPUVMEnable = %d\n" , plane->GPUVMEnable); |
547 | dml_print("DML: plane_cfg: HostVMEnable = %d\n" , plane->HostVMEnable); |
548 | dml_print("DML: plane_cfg: GPUVMMaxPageTableLevels = %d\n" , plane->GPUVMMaxPageTableLevels); |
549 | dml_print("DML: plane_cfg: HostVMMaxPageTableLevels = %d\n" , plane->HostVMMaxPageTableLevels); |
550 | |
551 | for (dml_uint_t i = 0; i < num_plane; i++) { |
552 | dml_print("DML: plane_cfg: plane=%d, GPUVMMinPageSizeKBytes = %d\n" , i, plane->GPUVMMinPageSizeKBytes[i]); |
553 | dml_print("DML: plane_cfg: plane=%d, ForceOneRowForFrame = %d\n" , i, plane->ForceOneRowForFrame[i]); |
554 | dml_print("DML: plane_cfg: plane=%d, PTEBufferModeOverrideEn = %d\n" , i, plane->PTEBufferModeOverrideEn[i]); |
555 | dml_print("DML: plane_cfg: plane=%d, PTEBufferMode = %d\n" , i, plane->PTEBufferMode[i]); |
556 | dml_print("DML: plane_cfg: plane=%d, DETSizeOverride = %d\n" , i, plane->DETSizeOverride[i]); |
557 | dml_print("DML: plane_cfg: plane=%d, UseMALLForStaticScreen = %d\n" , i, plane->UseMALLForStaticScreen[i]); |
558 | dml_print("DML: plane_cfg: plane=%d, UseMALLForPStateChange = %d\n" , i, plane->UseMALLForPStateChange[i]); |
559 | dml_print("DML: plane_cfg: plane=%d, BlendingAndTiming = %d\n" , i, plane->BlendingAndTiming[i]); |
560 | dml_print("DML: plane_cfg: plane=%d, ViewportWidth = %d\n" , i, plane->ViewportWidth[i]); |
561 | dml_print("DML: plane_cfg: plane=%d, ViewportHeight = %d\n" , i, plane->ViewportHeight[i]); |
562 | dml_print("DML: plane_cfg: plane=%d, ViewportWidthChroma = %d\n" , i, plane->ViewportWidthChroma[i]); |
563 | dml_print("DML: plane_cfg: plane=%d, ViewportHeightChroma = %d\n" , i, plane->ViewportHeightChroma[i]); |
564 | dml_print("DML: plane_cfg: plane=%d, ViewportXStart = %d\n" , i, plane->ViewportXStart[i]); |
565 | dml_print("DML: plane_cfg: plane=%d, ViewportXStartC = %d\n" , i, plane->ViewportXStartC[i]); |
566 | dml_print("DML: plane_cfg: plane=%d, ViewportYStart = %d\n" , i, plane->ViewportYStart[i]); |
567 | dml_print("DML: plane_cfg: plane=%d, ViewportYStartC = %d\n" , i, plane->ViewportYStartC[i]); |
568 | dml_print("DML: plane_cfg: plane=%d, ViewportStationary = %d\n" , i, plane->ViewportStationary[i]); |
569 | dml_print("DML: plane_cfg: plane=%d, ScalerEnabled = %d\n" , i, plane->ScalerEnabled[i]); |
570 | dml_print("DML: plane_cfg: plane=%d, HRatio = %3.2f\n" , i, plane->HRatio[i]); |
571 | dml_print("DML: plane_cfg: plane=%d, VRatio = %3.2f\n" , i, plane->VRatio[i]); |
572 | dml_print("DML: plane_cfg: plane=%d, HRatioChroma = %3.2f\n" , i, plane->HRatioChroma[i]); |
573 | dml_print("DML: plane_cfg: plane=%d, VRatioChroma = %3.2f\n" , i, plane->VRatioChroma[i]); |
574 | dml_print("DML: plane_cfg: plane=%d, HTaps = %d\n" , i, plane->HTaps[i]); |
575 | dml_print("DML: plane_cfg: plane=%d, VTaps = %d\n" , i, plane->VTaps[i]); |
576 | dml_print("DML: plane_cfg: plane=%d, HTapsChroma = %d\n" , i, plane->HTapsChroma[i]); |
577 | dml_print("DML: plane_cfg: plane=%d, VTapsChroma = %d\n" , i, plane->VTapsChroma[i]); |
578 | dml_print("DML: plane_cfg: plane=%d, LBBitPerPixel = %d\n" , i, plane->LBBitPerPixel[i]); |
579 | dml_print("DML: plane_cfg: plane=%d, SourceScan = %d\n" , i, plane->SourceScan[i]); |
580 | dml_print("DML: plane_cfg: plane=%d, ScalerRecoutWidth = %d\n" , i, plane->ScalerRecoutWidth[i]); |
581 | dml_print("DML: plane_cfg: plane=%d, NumberOfCursors = %d\n" , i, plane->NumberOfCursors[i]); |
582 | dml_print("DML: plane_cfg: plane=%d, CursorWidth = %d\n" , i, plane->CursorWidth[i]); |
583 | dml_print("DML: plane_cfg: plane=%d, CursorBPP = %d\n" , i, plane->CursorBPP[i]); |
584 | |
585 | dml_print("DML: plane_cfg: plane=%d, DynamicMetadataEnable = %d\n" , i, plane->DynamicMetadataEnable[i]); |
586 | dml_print("DML: plane_cfg: plane=%d, DynamicMetadataLinesBeforeActiveRequired = %d\n" , i, plane->DynamicMetadataLinesBeforeActiveRequired[i]); |
587 | dml_print("DML: plane_cfg: plane=%d, DynamicMetadataTransmittedBytes = %d\n" , i, plane->DynamicMetadataTransmittedBytes[i]); |
588 | } |
589 | } |
590 | |
591 | void dml_print_dml_display_cfg_surface(const struct dml_surface_cfg_st *surface, dml_uint_t num_plane) |
592 | { |
593 | for (dml_uint_t i = 0; i < num_plane; i++) { |
594 | dml_print("DML: surface_cfg: plane=%d, PitchY = %d\n" , i, surface->PitchY[i]); |
595 | dml_print("DML: surface_cfg: plane=%d, SurfaceWidthY = %d\n" , i, surface->SurfaceWidthY[i]); |
596 | dml_print("DML: surface_cfg: plane=%d, SurfaceHeightY = %d\n" , i, surface->SurfaceHeightY[i]); |
597 | dml_print("DML: surface_cfg: plane=%d, PitchC = %d\n" , i, surface->PitchC[i]); |
598 | dml_print("DML: surface_cfg: plane=%d, SurfaceWidthC = %d\n" , i, surface->SurfaceWidthC[i]); |
599 | dml_print("DML: surface_cfg: plane=%d, SurfaceHeightC = %d\n" , i, surface->SurfaceHeightC[i]); |
600 | dml_print("DML: surface_cfg: plane=%d, DCCEnable = %d\n" , i, surface->DCCEnable[i]); |
601 | dml_print("DML: surface_cfg: plane=%d, DCCMetaPitchY = %d\n" , i, surface->DCCMetaPitchY[i]); |
602 | dml_print("DML: surface_cfg: plane=%d, DCCMetaPitchC = %d\n" , i, surface->DCCMetaPitchC[i]); |
603 | dml_print("DML: surface_cfg: plane=%d, DCCRateLuma = %f\n" , i, surface->DCCRateLuma[i]); |
604 | dml_print("DML: surface_cfg: plane=%d, DCCRateChroma = %f\n" , i, surface->DCCRateChroma[i]); |
605 | dml_print("DML: surface_cfg: plane=%d, DCCFractionOfZeroSizeRequestsLuma = %f\n" , i, surface->DCCFractionOfZeroSizeRequestsLuma[i]); |
606 | dml_print("DML: surface_cfg: plane=%d, DCCFractionOfZeroSizeRequestsChroma= %f\n" , i, surface->DCCFractionOfZeroSizeRequestsChroma[i]); |
607 | } |
608 | } |
609 | |
610 | void dml_print_dml_display_cfg_hw_resource(const struct dml_hw_resource_st *hw, dml_uint_t num_plane) |
611 | { |
612 | for (dml_uint_t i = 0; i < num_plane; i++) { |
613 | dml_print("DML: hw_resource: plane=%d, ODMMode = %d\n" , i, hw->ODMMode[i]); |
614 | dml_print("DML: hw_resource: plane=%d, DPPPerSurface = %d\n" , i, hw->DPPPerSurface[i]); |
615 | dml_print("DML: hw_resource: plane=%d, DSCEnabled = %d\n" , i, hw->DSCEnabled[i]); |
616 | dml_print("DML: hw_resource: plane=%d, NumberOfDSCSlices = %d\n" , i, hw->NumberOfDSCSlices[i]); |
617 | } |
618 | dml_print("DML: hw_resource: DLGRefClkFreqMHz = %f\n" , hw->DLGRefClkFreqMHz); |
619 | } |
620 | |
621 | __DML_DLL_EXPORT__ void dml_print_soc_state_bounding_box(const struct soc_state_bounding_box_st *state) |
622 | { |
623 | dml_print("DML: state_bbox: socclk_mhz = %f\n" , state->socclk_mhz); |
624 | dml_print("DML: state_bbox: dscclk_mhz = %f\n" , state->dscclk_mhz); |
625 | dml_print("DML: state_bbox: phyclk_mhz = %f\n" , state->phyclk_mhz); |
626 | dml_print("DML: state_bbox: phyclk_d18_mhz = %f\n" , state->phyclk_d18_mhz); |
627 | dml_print("DML: state_bbox: phyclk_d32_mhz = %f\n" , state->phyclk_d32_mhz); |
628 | dml_print("DML: state_bbox: dtbclk_mhz = %f\n" , state->dtbclk_mhz); |
629 | dml_print("DML: state_bbox: dispclk_mhz = %f\n" , state->dispclk_mhz); |
630 | dml_print("DML: state_bbox: dppclk_mhz = %f\n" , state->dppclk_mhz); |
631 | dml_print("DML: state_bbox: fabricclk_mhz = %f\n" , state->fabricclk_mhz); |
632 | dml_print("DML: state_bbox: dcfclk_mhz = %f\n" , state->dcfclk_mhz); |
633 | dml_print("DML: state_bbox: dram_speed_mts = %f\n" , state->dram_speed_mts); |
634 | dml_print("DML: state_bbox: urgent_latency_pixel_data_only_us = %f\n" , state->urgent_latency_pixel_data_only_us); |
635 | dml_print("DML: state_bbox: urgent_latency_pixel_mixed_with_vm_data_us = %f\n" , state->urgent_latency_pixel_mixed_with_vm_data_us); |
636 | dml_print("DML: state_bbox: urgent_latency_vm_data_only_us = %f\n" , state->urgent_latency_vm_data_only_us); |
637 | dml_print("DML: state_bbox: writeback_latency_us = %f\n" , state->writeback_latency_us); |
638 | dml_print("DML: state_bbox: urgent_latency_adjustment_fabric_clock_component_us = %f\n" , state->urgent_latency_adjustment_fabric_clock_component_us); |
639 | dml_print("DML: state_bbox: urgent_latency_adjustment_fabric_clock_reference_mhz= %f\n" , state->urgent_latency_adjustment_fabric_clock_reference_mhz); |
640 | dml_print("DML: state_bbox: sr_exit_time_us = %f\n" , state->sr_exit_time_us); |
641 | dml_print("DML: state_bbox: sr_enter_plus_exit_time_us = %f\n" , state->sr_enter_plus_exit_time_us); |
642 | dml_print("DML: state_bbox: sr_exit_z8_time_us = %f\n" , state->sr_exit_z8_time_us); |
643 | dml_print("DML: state_bbox: sr_enter_plus_exit_z8_time_us = %f\n" , state->sr_enter_plus_exit_z8_time_us); |
644 | dml_print("DML: state_bbox: dram_clock_change_latency_us = %f\n" , state->dram_clock_change_latency_us); |
645 | dml_print("DML: state_bbox: fclk_change_latency_us = %f\n" , state->fclk_change_latency_us); |
646 | dml_print("DML: state_bbox: usr_retraining_latency_us = %f\n" , state->usr_retraining_latency_us); |
647 | dml_print("DML: state_bbox: use_ideal_dram_bw_strobe = %d\n" , state->use_ideal_dram_bw_strobe); |
648 | } |
649 | |
650 | __DML_DLL_EXPORT__ void dml_print_soc_bounding_box(const struct soc_bounding_box_st *soc) |
651 | { |
652 | dml_print("DML: soc_bbox: dprefclk_mhz = %f\n" , soc->dprefclk_mhz); |
653 | dml_print("DML: soc_bbox: xtalclk_mhz = %f\n" , soc->xtalclk_mhz); |
654 | dml_print("DML: soc_bbox: pcierefclk_mhz = %f\n" , soc->pcierefclk_mhz); |
655 | dml_print("DML: soc_bbox: refclk_mhz = %f\n" , soc->refclk_mhz); |
656 | dml_print("DML: soc_bbox: amclk_mhz = %f\n" , soc->amclk_mhz); |
657 | |
658 | dml_print("DML: soc_bbox: max_outstanding_reqs = %f\n" , soc->max_outstanding_reqs); |
659 | dml_print("DML: soc_bbox: pct_ideal_sdp_bw_after_urgent = %f\n" , soc->pct_ideal_sdp_bw_after_urgent); |
660 | dml_print("DML: soc_bbox: pct_ideal_fabric_bw_after_urgent = %f\n" , soc->pct_ideal_fabric_bw_after_urgent); |
661 | dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_pixel_only = %f\n" , soc->pct_ideal_dram_bw_after_urgent_pixel_only); |
662 | dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_pixel_and_vm = %f\n" , soc->pct_ideal_dram_bw_after_urgent_pixel_and_vm); |
663 | dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_vm_only = %f\n" , soc->pct_ideal_dram_bw_after_urgent_vm_only); |
664 | dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_strobe = %f\n" , soc->pct_ideal_dram_bw_after_urgent_strobe); |
665 | dml_print("DML: soc_bbox: max_avg_sdp_bw_use_normal_percent = %f\n" , soc->max_avg_sdp_bw_use_normal_percent); |
666 | dml_print("DML: soc_bbox: max_avg_fabric_bw_use_normal_percent = %f\n" , soc->max_avg_fabric_bw_use_normal_percent); |
667 | dml_print("DML: soc_bbox: max_avg_dram_bw_use_normal_percent = %f\n" , soc->max_avg_dram_bw_use_normal_percent); |
668 | dml_print("DML: soc_bbox: max_avg_dram_bw_use_normal_strobe_percent = %f\n" , soc->max_avg_dram_bw_use_normal_strobe_percent); |
669 | dml_print("DML: soc_bbox: round_trip_ping_latency_dcfclk_cycles = %d\n" , soc->round_trip_ping_latency_dcfclk_cycles); |
670 | dml_print("DML: soc_bbox: urgent_out_of_order_return_per_channel_pixel_only_bytes = %d\n" , soc->urgent_out_of_order_return_per_channel_pixel_only_bytes); |
671 | dml_print("DML: soc_bbox: urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = %d\n" , soc->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); |
672 | dml_print("DML: soc_bbox: urgent_out_of_order_return_per_channel_vm_only_bytes = %d\n" , soc->urgent_out_of_order_return_per_channel_vm_only_bytes); |
673 | dml_print("DML: soc_bbox: num_chans = %d\n" , soc->num_chans); |
674 | dml_print("DML: soc_bbox: return_bus_width_bytes = %d\n" , soc->return_bus_width_bytes); |
675 | dml_print("DML: soc_bbox: dram_channel_width_bytes = %d\n" , soc->dram_channel_width_bytes); |
676 | dml_print("DML: soc_bbox: fabric_datapath_to_dcn_data_return_bytes = %d\n" , soc->fabric_datapath_to_dcn_data_return_bytes); |
677 | dml_print("DML: soc_bbox: hostvm_min_page_size_kbytes = %d\n" , soc->hostvm_min_page_size_kbytes); |
678 | dml_print("DML: soc_bbox: gpuvm_min_page_size_kbytes = %d\n" , soc->gpuvm_min_page_size_kbytes); |
679 | dml_print("DML: soc_bbox: phy_downspread_percent = %f\n" , soc->phy_downspread_percent); |
680 | dml_print("DML: soc_bbox: dcn_downspread_percent = %f\n" , soc->dcn_downspread_percent); |
681 | dml_print("DML: soc_bbox: smn_latency_us = %f\n" , soc->smn_latency_us); |
682 | dml_print("DML: soc_bbox: mall_allocated_for_dcn_mbytes = %d\n" , soc->mall_allocated_for_dcn_mbytes); |
683 | dml_print("DML: soc_bbox: dispclk_dppclk_vco_speed_mhz = %f\n" , soc->dispclk_dppclk_vco_speed_mhz); |
684 | dml_print("DML: soc_bbox: do_urgent_latency_adjustment = %d\n" , soc->do_urgent_latency_adjustment); |
685 | } |
686 | |
687 | __DML_DLL_EXPORT__ void dml_print_clk_cfg(const struct dml_clk_cfg_st *clk_cfg) |
688 | { |
689 | dml_print("DML: clk_cfg: 0-use_required, 1-use pipe.clks_cfg, 2-use state bbox\n" ); |
690 | dml_print("DML: clk_cfg: dcfclk_option = %d\n" , clk_cfg->dcfclk_option); |
691 | dml_print("DML: clk_cfg: dispclk_option = %d\n" , clk_cfg->dispclk_option); |
692 | |
693 | dml_print("DML: clk_cfg: dcfclk_freq_mhz = %f\n" , clk_cfg->dcfclk_freq_mhz); |
694 | dml_print("DML: clk_cfg: dispclk_freq_mhz = %f\n" , clk_cfg->dispclk_freq_mhz); |
695 | |
696 | for (dml_uint_t i = 0; i < DCN_DML__NUM_PLANE; i++) { |
697 | dml_print("DML: clk_cfg: i=%d, dppclk_option = %d\n" , i, clk_cfg->dppclk_option[i]); |
698 | dml_print("DML: clk_cfg: i=%d, dppclk_freq_mhz = %f\n" , i, clk_cfg->dppclk_freq_mhz[i]); |
699 | } |
700 | } |
701 | |
702 | dml_bool_t dml_is_vertical_rotation(enum dml_rotation_angle Scan) |
703 | { |
704 | dml_bool_t is_vert = false; |
705 | if (Scan == dml_rotation_90 || Scan == dml_rotation_90m || Scan == dml_rotation_270 || Scan == dml_rotation_270m) { |
706 | is_vert = true; |
707 | } else { |
708 | is_vert = false; |
709 | } |
710 | return is_vert; |
711 | } // dml_is_vertical_rotation |
712 | |
713 | dml_uint_t dml_get_cursor_bit_per_pixel(enum dml_cursor_bpp ebpp) |
714 | { |
715 | switch (ebpp) { |
716 | case dml_cur_2bit: |
717 | return 2; |
718 | case dml_cur_32bit: |
719 | return 32; |
720 | case dml_cur_64bit: |
721 | return 64; |
722 | default: |
723 | return 0; |
724 | } |
725 | } |
726 | |
727 | /// @brief Determine the physical pipe to logical plane mapping using the display_cfg |
728 | dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg) |
729 | { |
730 | dml_uint_t num_active_planes = 0; |
731 | |
732 | for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; k++) { |
733 | if (display_cfg->plane.ViewportWidth[k] > 0) |
734 | num_active_planes = num_active_planes + 1; |
735 | } |
736 | #ifdef __DML_VBA_DEBUG__ |
737 | dml_print("DML::%s: num_active_planes = %d\n" , __func__, num_active_planes); |
738 | #endif |
739 | return num_active_planes; |
740 | } |
741 | |
742 | /// @brief Determine the physical pipe to logical plane mapping using the display_cfg |
743 | dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg) |
744 | { |
745 | dml_uint_t num_active_pipes = 0; |
746 | |
747 | for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) { |
748 | num_active_pipes = num_active_pipes + display_cfg->hw.DPPPerSurface[j]; |
749 | } |
750 | |
751 | #ifdef __DML_VBA_DEBUG__ |
752 | dml_print("DML::%s: num_active_pipes = %d\n" , __func__, num_active_pipes); |
753 | #endif |
754 | return num_active_pipes; |
755 | } |
756 | |
757 | dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx) |
758 | { |
759 | dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; |
760 | return plane_idx; |
761 | } |
762 | |
763 | dml_uint_t dml_get_pipe_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t plane_idx) |
764 | { |
765 | dml_uint_t pipe_idx = 0; |
766 | dml_bool_t pipe_found = 0; |
767 | |
768 | ASSERT(plane_idx < __DML_NUM_PLANES__); |
769 | |
770 | for (dml_uint_t i = 0; i < __DML_NUM_PLANES__; i++) { |
771 | if (plane_idx == mode_lib->mp.pipe_plane[i]) { |
772 | pipe_idx = i; |
773 | pipe_found = 1; |
774 | break; |
775 | } |
776 | } |
777 | ASSERT(pipe_found != 0); |
778 | |
779 | return pipe_idx; |
780 | } |
781 | |
782 | void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane) |
783 | { |
784 | dml_uint_t pipe_idx = 0; |
785 | |
786 | for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k) { |
787 | pipe_plane[k] = __DML_PIPE_NO_PLANE__; |
788 | } |
789 | |
790 | for (dml_uint_t plane_idx = 0; plane_idx < __DML_NUM_PLANES__; plane_idx++) { |
791 | for (dml_uint_t i = 0; i < hw->DPPPerSurface[plane_idx]; i++) { |
792 | pipe_plane[pipe_idx] = plane_idx; |
793 | pipe_idx++; |
794 | } |
795 | } |
796 | } |
797 | |
798 | |
799 | |