1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26#include "include/gpio_types.h"
27#include "../hw_factory.h"
28
29
30#include "../hw_gpio.h"
31#include "../hw_ddc.h"
32#include "../hw_hpd.h"
33#include "../hw_generic.h"
34
35#include "hw_factory_dcn315.h"
36
37#include "dcn/dcn_3_1_5_offset.h"
38#include "dcn/dcn_3_1_5_sh_mask.h"
39
40#include "reg_helper.h"
41#include "../hpd_regs.h"
42/* begin *********************
43 * macros to expend register list macro defined in HW object header file */
44
45#define DCN_BASE__INST0_SEG0 0x00000012
46#define DCN_BASE__INST0_SEG1 0x000000C0
47#define DCN_BASE__INST0_SEG2 0x000034C0
48#define DCN_BASE__INST0_SEG3 0x00009000
49#define DCN_BASE__INST0_SEG4 0x02403C00
50#define DCN_BASE__INST0_SEG5 0
51
52/* DCN */
53#define block HPD
54#define reg_num 0
55
56#undef BASE_INNER
57#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
58
59#define BASE(seg) BASE_INNER(seg)
60
61
62
63#define REG(reg_name)\
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
65
66#define SF_HPD(reg_name, field_name, post_fix)\
67 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
68
69#define REGI(reg_name, block, id)\
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
71 reg ## block ## id ## _ ## reg_name
72
73#define SF(reg_name, field_name, post_fix)\
74 .field_name = reg_name ## __ ## field_name ## post_fix
75
76/* macros to expend register list macro defined in HW object header file
77 * end *********************/
78
79
80
81#define hpd_regs(id) \
82{\
83 HPD_REG_LIST(id)\
84}
85
86static const struct hpd_registers hpd_regs[] = {
87 hpd_regs(0),
88 hpd_regs(1),
89 hpd_regs(2),
90 hpd_regs(3),
91 hpd_regs(4),
92};
93
94static const struct hpd_sh_mask hpd_shift = {
95 HPD_MASK_SH_LIST(__SHIFT)
96};
97
98static const struct hpd_sh_mask hpd_mask = {
99 HPD_MASK_SH_LIST(_MASK)
100};
101
102#include "../ddc_regs.h"
103
104 /* set field name */
105#define SF_DDC(reg_name, field_name, post_fix)\
106 .field_name = reg_name ## __ ## field_name ## post_fix
107
108static const struct ddc_registers ddc_data_regs_dcn[] = {
109 ddc_data_regs_dcn2(1),
110 ddc_data_regs_dcn2(2),
111 ddc_data_regs_dcn2(3),
112 ddc_data_regs_dcn2(4),
113 ddc_data_regs_dcn2(5),
114 {
115 DDC_GPIO_VGA_REG_LIST(DATA),
116 .ddc_setup = 0,
117 .phy_aux_cntl = 0,
118 .dc_gpio_aux_ctrl_5 = 0
119 }
120};
121
122static const struct ddc_registers ddc_clk_regs_dcn[] = {
123 ddc_clk_regs_dcn2(1),
124 ddc_clk_regs_dcn2(2),
125 ddc_clk_regs_dcn2(3),
126 ddc_clk_regs_dcn2(4),
127 ddc_clk_regs_dcn2(5),
128 {
129 DDC_GPIO_VGA_REG_LIST(CLK),
130 .ddc_setup = 0,
131 .phy_aux_cntl = 0,
132 .dc_gpio_aux_ctrl_5 = 0
133 }
134};
135
136static const struct ddc_sh_mask ddc_shift[] = {
137 DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
138 DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
139 DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
140 DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
141 DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
142 DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
143};
144
145static const struct ddc_sh_mask ddc_mask[] = {
146 DDC_MASK_SH_LIST_DCN2(_MASK, 1),
147 DDC_MASK_SH_LIST_DCN2(_MASK, 2),
148 DDC_MASK_SH_LIST_DCN2(_MASK, 3),
149 DDC_MASK_SH_LIST_DCN2(_MASK, 4),
150 DDC_MASK_SH_LIST_DCN2(_MASK, 5),
151 DDC_MASK_SH_LIST_DCN2(_MASK, 6)
152};
153
154#include "../generic_regs.h"
155
156/* set field name */
157#define SF_GENERIC(reg_name, field_name, post_fix)\
158 .field_name = reg_name ## __ ## field_name ## post_fix
159
160#define generic_regs(id) \
161{\
162 GENERIC_REG_LIST(id)\
163}
164
165static const struct generic_registers generic_regs[] = {
166 generic_regs(A),
167 generic_regs(B),
168};
169
170static const struct generic_sh_mask generic_shift[] = {
171 GENERIC_MASK_SH_LIST(__SHIFT, A),
172 GENERIC_MASK_SH_LIST(__SHIFT, B),
173};
174
175static const struct generic_sh_mask generic_mask[] = {
176 GENERIC_MASK_SH_LIST(_MASK, A),
177 GENERIC_MASK_SH_LIST(_MASK, B),
178};
179
180static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
181{
182 struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
183
184 generic->regs = &generic_regs[en];
185 generic->shifts = &generic_shift[en];
186 generic->masks = &generic_mask[en];
187 generic->base.regs = &generic_regs[en].gpio;
188}
189
190static void define_ddc_registers(
191 struct hw_gpio_pin *pin,
192 uint32_t en)
193{
194 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
195
196 switch (pin->id) {
197 case GPIO_ID_DDC_DATA:
198 ddc->regs = &ddc_data_regs_dcn[en];
199 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
200 break;
201 case GPIO_ID_DDC_CLOCK:
202 ddc->regs = &ddc_clk_regs_dcn[en];
203 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
204 break;
205 default:
206 ASSERT_CRITICAL(false);
207 return;
208 }
209
210 ddc->shifts = &ddc_shift[en];
211 ddc->masks = &ddc_mask[en];
212
213}
214
215static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
216{
217 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
218
219 hpd->regs = &hpd_regs[en];
220 hpd->shifts = &hpd_shift;
221 hpd->masks = &hpd_mask;
222 hpd->base.regs = &hpd_regs[en].gpio;
223}
224
225
226/* fucntion table */
227static const struct hw_factory_funcs funcs = {
228 .init_ddc_data = dal_hw_ddc_init,
229 .init_generic = dal_hw_generic_init,
230 .init_hpd = dal_hw_hpd_init,
231 .get_ddc_pin = dal_hw_ddc_get_pin,
232 .get_hpd_pin = dal_hw_hpd_get_pin,
233 .get_generic_pin = dal_hw_generic_get_pin,
234 .define_hpd_registers = define_hpd_registers,
235 .define_ddc_registers = define_ddc_registers,
236 .define_generic_registers = define_generic_registers
237};
238/*
239 * dal_hw_factory_dcn10_init
240 *
241 * @brief
242 * Initialize HW factory function pointers and pin info
243 *
244 * @param
245 * struct hw_factory *factory - [out] struct of function pointers
246 */
247void dal_hw_factory_dcn315_init(struct hw_factory *factory)
248{
249 /*TODO check ASIC CAPs*/
250 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
251 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
252 factory->number_of_pins[GPIO_ID_GENERIC] = 4;
253 factory->number_of_pins[GPIO_ID_HPD] = 6;
254 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
255 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
256 factory->number_of_pins[GPIO_ID_SYNC] = 0;
257 factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
258
259 factory->funcs = &funcs;
260}
261

source code of linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c