1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "link_hwss_hpo_dp.h"
26#include "link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
27#include "link_hwss_dio_fixed_vs_pe_retimer.h"
28
29static void dp_hpo_fixed_vs_pe_retimer_set_tx_ffe(struct dc_link *link,
30 const struct dc_lane_settings *hw_lane_settings)
31{
32 const uint8_t vendor_ffe_preset_table[16] = {
33 0x01, 0x41, 0x61, 0x81,
34 0xB1, 0x05, 0x35, 0x65,
35 0x85, 0xA5, 0x09, 0x39,
36 0x59, 0x89, 0x0F, 0x24};
37
38 const uint8_t ffe_mask[4] = {
39 (hw_lane_settings[0].FFE_PRESET.settings.no_deemphasis != 0 ? 0x0F : 0xFF)
40 & (hw_lane_settings[0].FFE_PRESET.settings.no_preshoot != 0 ? 0xF1 : 0xFF),
41 (hw_lane_settings[1].FFE_PRESET.settings.no_deemphasis != 0 ? 0x0F : 0xFF)
42 & (hw_lane_settings[1].FFE_PRESET.settings.no_preshoot != 0 ? 0xF1 : 0xFF),
43 (hw_lane_settings[2].FFE_PRESET.settings.no_deemphasis != 0 ? 0x0F : 0xFF)
44 & (hw_lane_settings[2].FFE_PRESET.settings.no_preshoot != 0 ? 0xF1 : 0xFF),
45 (hw_lane_settings[3].FFE_PRESET.settings.no_deemphasis != 0 ? 0x0F : 0xFF)
46 & (hw_lane_settings[3].FFE_PRESET.settings.no_preshoot != 0 ? 0xF1 : 0xFF)};
47
48 const uint8_t ffe_cfg[4] = {
49 vendor_ffe_preset_table[hw_lane_settings[0].FFE_PRESET.settings.level] & ffe_mask[0],
50 vendor_ffe_preset_table[hw_lane_settings[1].FFE_PRESET.settings.level] & ffe_mask[1],
51 vendor_ffe_preset_table[hw_lane_settings[2].FFE_PRESET.settings.level] & ffe_mask[2],
52 vendor_ffe_preset_table[hw_lane_settings[3].FFE_PRESET.settings.level] & ffe_mask[3]};
53
54 const uint8_t dp_type = dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(link);
55
56 const uint8_t vendor_lttpr_write_data_ffe1[4] = {0x01, 0x50, dp_type, 0x0F};
57 const uint8_t vendor_lttpr_write_data_ffe2[4] = {0x01, 0x55, dp_type, ffe_cfg[0]};
58 const uint8_t vendor_lttpr_write_data_ffe3[4] = {0x01, 0x56, dp_type, ffe_cfg[1]};
59 const uint8_t vendor_lttpr_write_data_ffe4[4] = {0x01, 0x57, dp_type, ffe_cfg[2]};
60 const uint8_t vendor_lttpr_write_data_ffe5[4] = {0x01, 0x58, dp_type, ffe_cfg[3]};
61
62 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
63 &vendor_lttpr_write_data_ffe1[0], sizeof(vendor_lttpr_write_data_ffe1));
64 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
65 &vendor_lttpr_write_data_ffe2[0], sizeof(vendor_lttpr_write_data_ffe2));
66 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
67 &vendor_lttpr_write_data_ffe3[0], sizeof(vendor_lttpr_write_data_ffe3));
68 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
69 &vendor_lttpr_write_data_ffe4[0], sizeof(vendor_lttpr_write_data_ffe4));
70 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
71 &vendor_lttpr_write_data_ffe5[0], sizeof(vendor_lttpr_write_data_ffe5));
72}
73
74static void dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern(struct dc_link *link,
75 struct encoder_set_dp_phy_pattern_param *tp_params)
76{
77 uint8_t clk_src = 0x4C;
78 uint8_t pattern = 0x4F; /* SQ128 */
79
80 const uint8_t vendor_lttpr_write_data_pg0[4] = {0x1, 0x11, 0x0, 0x0};
81 const uint8_t vendor_lttpr_write_data_pg1[4] = {0x1, 0x50, 0x50, clk_src};
82 const uint8_t vendor_lttpr_write_data_pg2[4] = {0x1, 0x51, 0x50, clk_src};
83 const uint8_t vendor_lttpr_write_data_pg3[4] = {0x1, 0x10, 0x58, 0x21};
84 const uint8_t vendor_lttpr_write_data_pg4[4] = {0x1, 0x10, 0x59, 0x21};
85 const uint8_t vendor_lttpr_write_data_pg5[4] = {0x1, 0x1C, 0x58, pattern};
86 const uint8_t vendor_lttpr_write_data_pg6[4] = {0x1, 0x1C, 0x59, pattern};
87 const uint8_t vendor_lttpr_write_data_pg7[4] = {0x1, 0x30, 0x51, 0x20};
88 const uint8_t vendor_lttpr_write_data_pg8[4] = {0x1, 0x30, 0x52, 0x20};
89 const uint8_t vendor_lttpr_write_data_pg9[4] = {0x1, 0x30, 0x54, 0x20};
90 const uint8_t vendor_lttpr_write_data_pg10[4] = {0x1, 0x30, 0x55, 0x20};
91
92 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
93 &vendor_lttpr_write_data_pg0[0], sizeof(vendor_lttpr_write_data_pg0));
94 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
95 &vendor_lttpr_write_data_pg1[0], sizeof(vendor_lttpr_write_data_pg1));
96 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
97 &vendor_lttpr_write_data_pg2[0], sizeof(vendor_lttpr_write_data_pg2));
98 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
99 &vendor_lttpr_write_data_pg3[0], sizeof(vendor_lttpr_write_data_pg3));
100 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
101 &vendor_lttpr_write_data_pg4[0], sizeof(vendor_lttpr_write_data_pg4));
102 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
103 &vendor_lttpr_write_data_pg5[0], sizeof(vendor_lttpr_write_data_pg5));
104 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
105 &vendor_lttpr_write_data_pg6[0], sizeof(vendor_lttpr_write_data_pg6));
106
107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR)
108 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
109 &vendor_lttpr_write_data_pg7[0], sizeof(vendor_lttpr_write_data_pg7));
110
111 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
112 &vendor_lttpr_write_data_pg8[0], sizeof(vendor_lttpr_write_data_pg8));
113
114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR)
115 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
116 &vendor_lttpr_write_data_pg9[0], sizeof(vendor_lttpr_write_data_pg9));
117
118 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
119 &vendor_lttpr_write_data_pg10[0], sizeof(vendor_lttpr_write_data_pg10));
120}
121
122static bool dp_hpo_fixed_vs_pe_retimer_set_override_test_pattern(struct dc_link *link,
123 const struct link_resource *link_res, struct encoder_set_dp_phy_pattern_param *tp_params,
124 const struct link_hwss *link_hwss)
125{
126 struct encoder_set_dp_phy_pattern_param hw_tp_params = { 0 };
127 const uint8_t vendor_lttpr_exit_manual_automation_0[4] = {0x1, 0x11, 0x0, 0x06};
128
129 if (!link->dpcd_caps.lttpr_caps.main_link_channel_coding.bits.DP_128b_132b_SUPPORTED)
130 return false;
131
132 if (tp_params == NULL)
133 return false;
134
135 if (!IS_DP_PHY_SQUARE_PATTERN(tp_params->dp_phy_pattern)) {
136 // Deprogram overrides from previously set square wave override
137 if (link->current_test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM ||
138 link->current_test_pattern == DP_TEST_PATTERN_D102)
139 link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,
140 &vendor_lttpr_exit_manual_automation_0[0],
141 sizeof(vendor_lttpr_exit_manual_automation_0));
142 else if (IS_DP_PHY_SQUARE_PATTERN(link->current_test_pattern))
143 dp_dio_fixed_vs_pe_retimer_exit_manual_automation(link);
144
145 return false;
146 }
147
148 hw_tp_params.dp_phy_pattern = DP_TEST_PATTERN_PRBS31;
149 hw_tp_params.dp_panel_mode = tp_params->dp_panel_mode;
150
151 if (link_hwss->ext.set_dp_link_test_pattern)
152 link_hwss->ext.set_dp_link_test_pattern(link, link_res, &hw_tp_params);
153
154 dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern(link, tp_params);
155
156 return true;
157}
158
159static void set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *link,
160 const struct link_resource *link_res,
161 struct encoder_set_dp_phy_pattern_param *tp_params)
162{
163 if (!dp_hpo_fixed_vs_pe_retimer_set_override_test_pattern(
164 link, link_res, tp_params, link_hwss: get_hpo_dp_link_hwss())) {
165 link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
166 link_res->hpo_dp_link_enc, tp_params);
167 }
168 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
169}
170
171static void set_hpo_fixed_vs_pe_retimer_dp_lane_settings(struct dc_link *link,
172 const struct link_resource *link_res,
173 const struct dc_link_settings *link_settings,
174 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
175{
176 // Don't update our HW FFE when outputting phy test patterns
177 if (IS_DP_PHY_PATTERN(link->pending_test_pattern)) {
178 // Directly program FIXED_VS retimer FFE for SQ128 override
179 if (IS_DP_PHY_SQUARE_PATTERN(link->pending_test_pattern)) {
180 dp_hpo_fixed_vs_pe_retimer_set_tx_ffe(link, hw_lane_settings: &lane_settings[0]);
181 }
182 } else {
183 link_res->hpo_dp_link_enc->funcs->set_ffe(
184 link_res->hpo_dp_link_enc,
185 link_settings,
186 lane_settings[0].FFE_PRESET.raw);
187 }
188}
189
190static void enable_hpo_fixed_vs_pe_retimer_dp_link_output(struct dc_link *link,
191 const struct link_resource *link_res,
192 enum signal_type signal,
193 enum clock_source_id clock_source,
194 const struct dc_link_settings *link_settings)
195{
196 if (link_settings->lane_count == LANE_COUNT_FOUR)
197 enable_dio_fixed_vs_pe_retimer_program_4lane_output(link);
198
199 enable_hpo_dp_link_output(link, link_res, signal, clock_source, link_settings);
200}
201
202static const struct link_hwss hpo_fixed_vs_pe_retimer_dp_link_hwss = {
203 .setup_stream_encoder = setup_hpo_dp_stream_encoder,
204 .reset_stream_encoder = reset_hpo_dp_stream_encoder,
205 .setup_stream_attribute = setup_hpo_dp_stream_attribute,
206 .disable_link_output = disable_hpo_dp_link_output,
207 .setup_audio_output = setup_hpo_dp_audio_output,
208 .enable_audio_packet = enable_hpo_dp_audio_packet,
209 .disable_audio_packet = disable_hpo_dp_audio_packet,
210 .ext = {
211 .set_throttled_vcp_size = set_hpo_dp_throttled_vcp_size,
212 .set_hblank_min_symbol_width = set_hpo_dp_hblank_min_symbol_width,
213 .enable_dp_link_output = enable_hpo_fixed_vs_pe_retimer_dp_link_output,
214 .set_dp_link_test_pattern = set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern,
215 .set_dp_lane_settings = set_hpo_fixed_vs_pe_retimer_dp_lane_settings,
216 .update_stream_allocation_table = update_hpo_dp_stream_allocation_table,
217 },
218};
219
220bool requires_fixed_vs_pe_retimer_hpo_link_hwss(const struct dc_link *link)
221{
222 return requires_fixed_vs_pe_retimer_dio_link_hwss(link);
223}
224
225const struct link_hwss *get_hpo_fixed_vs_pe_retimer_dp_link_hwss(void)
226{
227 return &hpo_fixed_vs_pe_retimer_dp_link_hwss;
228}
229

source code of linux/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c