1 | /* |
2 | * Copyright 2020 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef _DCN31_RESOURCE_H_ |
27 | #define _DCN31_RESOURCE_H_ |
28 | |
29 | #include "core_types.h" |
30 | |
31 | #define TO_DCN31_RES_POOL(pool)\ |
32 | container_of(pool, struct dcn31_resource_pool, base) |
33 | |
34 | extern struct _vcs_dpi_ip_params_st dcn3_1_ip; |
35 | |
36 | struct dcn31_resource_pool { |
37 | struct resource_pool base; |
38 | }; |
39 | |
40 | bool dcn31_validate_bandwidth(struct dc *dc, |
41 | struct dc_state *context, |
42 | bool fast_validate); |
43 | void dcn31_calculate_wm_and_dlg( |
44 | struct dc *dc, struct dc_state *context, |
45 | display_e2e_pipe_params_st *pipes, |
46 | int pipe_cnt, |
47 | int vlevel); |
48 | int dcn31_populate_dml_pipes_from_context( |
49 | struct dc *dc, struct dc_state *context, |
50 | display_e2e_pipe_params_st *pipes, |
51 | bool fast_validate); |
52 | void |
53 | dcn31_populate_dml_writeback_from_context(struct dc *dc, |
54 | struct resource_context *res_ctx, |
55 | display_e2e_pipe_params_st *pipes); |
56 | void |
57 | dcn31_set_mcif_arb_params(struct dc *dc, |
58 | struct dc_state *context, |
59 | display_e2e_pipe_params_st *pipes, |
60 | int pipe_cnt); |
61 | |
62 | struct resource_pool *dcn31_create_resource_pool( |
63 | const struct dc_init_data *init_data, |
64 | struct dc *dc); |
65 | |
66 | /*temp: B0 specific before switch to dcn313 headers*/ |
67 | #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL |
68 | #define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e |
69 | #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
70 | #define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f |
71 | #define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
72 | |
73 | //PHYPLLF_PIXCLK_RESYNC_CNTL |
74 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
75 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 |
76 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
77 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8 |
78 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 |
79 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
80 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L |
81 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
82 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L |
83 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L |
84 | |
85 | //PHYPLLG_PIXCLK_RESYNC_CNTL |
86 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
87 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 |
88 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
89 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8 |
90 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 |
91 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
92 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L |
93 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
94 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L |
95 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L |
96 | #endif |
97 | #endif /* _DCN31_RESOURCE_H_ */ |
98 | |